THE FUTURE OF GPU DATA MANAGEMENT. Michael Wolfe, May 9, 2017

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1 THE FUTURE OF GPU DATA MANAGEMENT Michael Wolfe, May 9, 2017

2 CPU CACHE Hardware managed What data to cache? Where to store the cached data? What data to evict when the cache fills up? When to store data back to system DRAM? (coherence) What address to use to access cached data? How to optimize programs to increase locality? 2

3 CPU CACHE core What data? Where to store? What to evict? Coherence? What address to use? How to optimize? memory 3

4 SCRATCHPAD MEMORY Software managed What data to cache? Where to store the cached data? What data to evict when the cache fills up? When to store data back to system DRAM? (if ever) What address to use to access cached data? How to increase use of scratchpad? 4

5 SCRATCHPAD MEMORY core What data? Where to store? What to evict? Coherence? What address to use? How to optimize? memory 5

6 GPU DEVICE MEMORY CPU DDR GPU GDDR or HBM What data? Where to store? What to evict? Coherence? What address to use? How to optimize? 6

7 GPU DEVICE MEMORY Software managed, for correctness as well as performance What data to cache? Where to store the cached data? What data to evict when the cache fills up? When to store data back to system DRAM? What address to use to access cached data? How to increase use of scratchpad? 7

8 OPENACC DEVICE MEMORY What: Data directives CPU System Memory GPU Device Memory Where: Anywhere Evict: Error Coherence: Update Address: Device address but same name Optimize: Correctness 8

9 GPU DEVICE MEMORY OpenACC What data to cache? Data directives and clauses. Where to store the cached data? Anywhere in device memory. What data to evict when the cache fills up? Program error. When to store data back to system DRAM? Update directives, end of data region. What address to use to access cached data? Device address!= host address. How to increase use of scratchpad? Must use device memory. 9

10 OPENACC USING MANAGED MEMORY -ta=tesla:managed on K80 What: Allocated CPU System Memory GPU Device Memory Where: Driver managed Evict: Error Coherence: Driver Address: Host address Optimize: Locality works malloc cost synchronization 10

11 CUDA UNIFIED (MANAGED) MEMORY Driver managed on K80 What data to cache? All dynamically allocated. Where to store the cached data? Driver managed. What data to evict when the cache fills up? Runtime error. When to store data back to system DRAM? Driver managed. What address to use to access cached data? Host address. How to increase use of device memory? Locality works. 11

12 CUDA UNIFIED (MANAGED) MEMORY OpenACC ta=tesla on K80 What data to cache? All dynamically allocated data (malloc, new, allocate). Where to store the cached data? Driver managed. What data to evict when the cache fills up? Runtime error. When to store data back to system DRAM? Driver managed. What address to use to access cached data? Host address. How to increase use of device memory? Locality works. 12

13 CUDA UNIFIED (MANAGED) MEMORY Driver managed on K80 Allocation is expensive, allocates both device and host pinned memory Can only allocate up to size of device memory All data migrated to device for each kernel launch (and paged back) Host must not access managed data while GPU is active Data movement is fast (host pinned memory) 13

14 OPENACC USING MANAGED MEMORY -ta=tesla:managed on P100 What: Allocated CPU System Memory GPU Device Memory Where: Driver managed Evict: Driver managed Coherence: Driver Address: Host address Optimize: Locality works malloc cost 14

15 CUDA UNIFIED (MANAGED) MEMORY Driver managed on P100 What data to cache? All dynamically allocated. Where to store the cached data? Driver managed. What data to evict when the cache fills up? Driver managed. When to store data back to system DRAM? Driver managed. What address to use to access cached data? Host address. How to increase use of device memory? Locality works. 15

16 CUDA UNIFIED (MANAGED) MEMORY Driver managed on P100 Allocation is expensive, allocates host pinned memory Can allocate more memory than GPU (oversubscription) Data is paged to GPU (and paged back) Host may access managed data while GPU is active User can set preferences and prefetching policies 16

17 SPECACCEL OPENACC Performance ratio, managed memory vs. directives 100% 80% 60% 40% 20% 0% POWER8+NVLink and P100 GPU, PGI 17.1 compilers PGI 17.1 Compilers OpenACC SPEC ACCEL 1.1 performance measured March, SPEC and the benchmark name SPEC ACCEL are registered trademarks of the Standard Performance Evaluation Corporation. 17

18 356.SP PERFORMANCE ANOMALY 100% 80% 60% 40% 20% 0% POWER8 18

19 356.SP PERFORMANCE ANOMALY 100% 80% 60% 40% 20% 0% POWER8 Haswell 19

20 356.SP PERFORMANCE W/ POOL ALLOCATOR 100% 80% 60% 40% 20% 0% POWER8 Haswell 20

21 356.SP PERFORMANCE W/ POOL ALLOCATOR 100% 80% 60% 40% 20% 0% POWER8 Haswell 21

22 CUDA UNIFIED MEMORY ON PASCAL & BEYOND Future HMM OS Option Works for static data, global data, dynamically allocated data All memory treated as managed Data is paged to GPU (and paged back) Host may access managed data while GPU is active User can set preferences and prefetching policies 22

23 SUFFICIENT? Why use OpenACC data directives at all? Portability to environments where Unified Memory isn t supported Useful to runtime as hints to set preferences or to prefetch data Moving large blocks is much more efficient than demand paging 23

24 THE FUTURE GPU Device Memory as a Cache Compile for multicore (let hardware cache manage data) Compile for GPU (let driver manage data) Add data directives as needed (for correctness and performance) 24

OpenACC Course. Office Hour #2 Q&A

OpenACC Course. Office Hour #2 Q&A OpenACC Course Office Hour #2 Q&A Q1: How many threads does each GPU core have? A: GPU cores execute arithmetic instructions. Each core can execute one single precision floating point instruction per cycle