Optimizing Cache Coherent Subsystem Architecture for Heterogeneous Multicore SoCs

Transcription

1 Optimizing Cache Coherent Subsystem Architecture for Heterogeneous Multicore SoCs Niu Feng Technical Specialist, ARM Tech Symposia 2016

2 Agenda Introduction Challenges: Optimizing cache coherent subsystem architecture for heterogeneous multicore SoCs Solution components Architecture prototype simulation and analysis Cache coherent architecture models (processors, interconnect, and memory subsystems) Case study illustration Summary / Q&A 2 2

3 Growth in heterogeneity being driven by automotive? New data for training Updated model CPUs + HW Accelerators CPUs + HW Accelerators 3 3

4 How to best communicate between processing elements? System-level constraint is becoming inter-cluster communication Complex communication semantics Latency and bandwidth requirements Software complexity, portability and scalability Power consumption (DRAM) Hardware cache coherence can simplify and optimize the system But many accelerators don t have a cache! Heterogeneous subsystem architectures enable both CPU1 L2 CPU2 L2 Cache Coherent Interconnect DRAM Acc1 Acc2 Non-Coherent Subsystem 4 4 4

5 Approach Using virtual prototypes with cache-coherent architecture performance models to enable Capture of application workloads (data and address) Efficient turn-around time for exploration System level analysis visibility for optimization Validation with high accuracy Case study featuring: Synopsys Platform Architect ARM Fast Models and ARM Cycle Models Arteris Ncore cache coherent interconnect CPU1 L2 CPU2 L2 Cache Coherent Interconnect DRAM Acc1 Acc2 Non-Coherent Subsystem 5 5

6 Agenda Introduction Challenges: Optimizing cache coherent subsystem architecture for heterogeneous multicore SoCs Solution components Architecture prototype simulation and analysis Cache coherent architecture models (processors, interconnect, and memory subsystems) Case study illustration Summary / Q&A 6 6

7 Synopsys Platform Architect User Traffic, Scenarios for Exploration Architecture Model Library Traffic-driven workload modeling Comprehensive library of generic and vendor specific architecture models Graphical assembly and analysis to explore SoC architecture tradeoffs Runtime configuration for simulation sweeping and sensitivity analysis Achieve system performance, power, and cost goals without over/under design Deployed by leading companies worldwide to optimize SoC architecture and reduce the risk of under- and over-design 7 7

8 Virtual prototype solution flow Workload capture Exploration Optimization Validation Fast Models Spec Generic interconnect model Ncore interconnect model Cycle Models Task Graphs and VPUs Platform Architect GCCI DDR DDR DDR 8

9 ARM Fast Models Fast, functionally complete models of all ARM IP 10s to 100s of MIPS speed to enable OS boots and software development Accuracy to run even the lowest level unmodified binaries Timing annotation to aid system optimization Earliest availability models Architecture models represent ISA Unmatched functionality Caches, TrustZone, Virtualization, Crypto, Multi-core/multi-cluster SystemC TLM interfaces to ensure wide compatibility Fixed virtual platforms to model reference systems Library includes: Cortex-A CPUs Cortex-R CPUs Cortex-M CPUs CoreLink CCI Interconnect CoreLink CCN/CMN Interconnect Mali GPUs Mali Display Processors Mali Video Processors ARM PrimeCells And more 9

10 ARM Cycle Models 10 ARM RTL ARM Cycle Model Studio ARM Cycle Model Instrumentation Compiled directly from ARM implementation RTL 100% implementation accurate All registers maintained Fully instrumented for in-depth analysis TARMAC trace generation Interactive debugging with DS-5 Pipelines, caches, memories, performance counters, etc VCD & FSDB format waveforms Pin and TLM level integrations Integrated with Synopsys PA and VDK Configurable 24/7 using ARM IP Exchange Available for a wide range of ARM IP including CPU & Coherent Interconnect

11 Agenda Introduction Challenges: Optimizing cache coherent subsystem architecture for heterogeneous multicore SoCs Solution components Architecture prototype simulation and analysis Cache coherent architecture models (processors, interconnect, and memory subsystems) Case study illustration Summary / Q&A 11

12 Case Study Illustration CPU1 L2 CPU2 L2 Vision Accelerators Acc1 Acc2 Use case: Vision SoC CPUs for general processing Accelerators for real-time image and data processing Cache Coherent Interconnect DRAM Non-Coherent Subsystem Goals Optimize interconnect configuration to achieve target bandwidth and latency Minimize power and cost (cache size and DDR frequency) Validate results 12

13 Generate Capture Workload model creation and mapping SW application SW execution trace CPU software profile Data-processing application Vision software profile spec.docx spec.vsd spec.xlsx VPU platform TGG Vision Task Graph Map Map CPU Task Graph 13 13

14 Platform model for exploration CPU Task Graph Quad core VPU 4 processing resources Shared L2 cache Vision Task Graph Accelerator VPU Single resource No cache Generic cache coherent interconnect (GCCI) 2x fully coherent CPU ports 2x ACE-lite accelerator ports with/without cache Configurable snoop DDR controller 3 AXI4 ports Configurable DDR 14

15 Scenario: DRAM or cache? PROBLEM Many systems with HW accelerators use pipeline processing Dedicated SRAMs cost area DRAM accesses are too slow and power hungry SOLUTION Enable caching for accelerators hardware without a cache (can be system cache or proxy cache) Advantages Better for sharing data between non-coherent agents (HW accelerators) and coherent agents (CPU and GPU clusters) Better for sharing data between custom processing elements (pipelining!) Using a cache minimizes communication through DRAM Better latency, bandwidth and power 15

16 Scenario: DRAM vs. cache latency ❸ Cache Coherent Interconnect CPU1 CPU2 Cache ($) Cache ($) Coherent agent interface Coherent agent interface ❶ Acc1 ❷ Acc2 In addition to lower latency: Lower power than DRAM Less area than SRAMs Directory Snoop filter Snoop filter Coherent memory interface CC Transport Interconnect Coherent memory interface Proxy cache ($) Non-coherent bridge Non-Coherent Interconnect Latency is the Key Metric DRAM 16

17 With Cache DRAM Only Scenario: DRAM vs. cache Significant deadline violation Accelerator utilization CPU utilization Poor cache performance High DDR utilization, especially when accelerators are active End-to-end deadline achieved Accelerator utilization CPU utilization Good cache performance Reduced end-to-end latency Low DDR utilization 17

18 Optimization Confirm results from exploration phase Replace Generic Cache Coherent Interconnect (GCCI) with accurate Ncore model Tuning of design and configuration parameters Outstanding transaction limits Quality of Service GCCI DDR DDR 18 18

19 Accurate model Generic model Confirm results from exploration phase Deadline trace VPU utilization 19 19

20 Validation Confirm results from optimization and exploration phase Replace task-based workload model running on VPU with actual Software running on ARM Cycle models Final Tuning of design and configuration parameters 20

21 Case study results CPU1 L2 CPU2 L2 Vision Accelerators Acc1 Acc2 Use case: Vision SoC CPUs for general processing Accelerators for real-time image and data processing Cache Coherent Interconnect DRAM Non-Coherent Subsystem Goals Optimize interconnect configuration to achieve target bandwidth and latency Minimize power and cost (cache size and DDR frequency) Validate results 21 21

22 Agenda Introduction Challenges: Optimizing cache coherent subsystem architecture for heterogeneous multicore SoCs Solution components Architecture prototype simulation and analysis Cache coherent architecture models (processors, interconnect, and memory subsystems) Case study illustration Summary / Q&A 22 22

23 Summary Optimizing Cache Coherent Subsystem Architecture for Heterogeneous Multicore SoCs CPU1 L2 CPU2 L2 Acc1 Acc2 Use virtual prototypes with cache-coherent architecture performance models to enable Capture of application workloads Efficient turn-around time for exploration System level analysis visibility for optimization Validation with high accuracy Cache Coherent Interconnect DRAM Non-Coherent Subsystem 23 23

24 Thank you! Bill Neifert Pat Sheridan Matthew Mangan

25 The trademarks featured in this presentation are registered and/or unregistered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. All other marks featured may be trademarks of their respective owners. Copyright 2016 ARM Limited