Coexistence of Time-Triggered and Event-Triggered Traffic in Switched Full-Duplex Ethernet Networks

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1 Coexistence of Time-Triggered and Event-Triggered Traffic in Switched Full-Duplex Ethernet Networks Joachim Hillebrand, Mehrnoush Rahmani and Richard Bogenberger BMW Group Research and Technology Hanauer Strasse Munich, Germany Eckehard Steinbach Technische Universität München Institute of Communication Networks Media Technology Group Munich, Germany Abstract In the recent years, the Ethernet technology has grown rapidly, mainly due to its applicability in local area networks. High data rates, low cost, collision reduction with the full-duplex approach and the elimination of chaining limits inherent in hubbed Ethernet networks have made the switched Ethernet a dominant network technology. Although the switch technology has improved significantly, the delays appearing in the switches are still not acceptable for time critical applications. This is specially the case when several cascaded switches are applied. Within the scope of developing a new network architecture for the in-vehicle communication, the time constraints of a switched Ethernet network are addressed in this paper. In order to comply with the delay bounds of time critical applications in the automotive field, a cost-effective approach is proposed and analyzed for several cascaded switches. I. INTRODUCTION In current automotive communication systems, the network architecture consists of several independent bus systems, where each of them is optimized for individual applications. Electronic Control Units (ECUs) for control applications are connected to CAN [1] or Flexray [2] bus systems. On the other hand, ECUs for multimedia applications are utilizing the MOST bus [3] for audio transmissions and various pointto-point links for video transmissions. This architecture of parallel bus systems leads to increased cost and complexity. In this paper we study the possibility of using a single Full- Duplex-Switched-Ethernet (FDSE) network to satisfy those manifold applications. In general, the communication concepts can be classified into two categories: Time-triggered communication and eventtriggered communication [4]. In the time-triggered communication concept the nodes obtain network access at specific time periods, also called time slots. Since it is ensured that there is no other network traffic during that time slot, the assigned transmitting network node can exclusively use the network resources at that time. This leads to very short delay times in the transmission. An example for such a system would be the Flexray bus [2], where in practice 4 to 20 network nodes communicate by using total cycle times of 1 to 5 milliseconds. A different approach is followed in event-triggered networks. Here, the nodes may obtain network access at any time instant. Therefore, it is generally not possible to transmit eventtriggered traffic over a time-triggered network. Since eventtriggered traffic may happen at any time, it would disrupt time-triggered traffic in dedicated time slots [5]. A very special representative of an event-triggered network is the Full-Duplex Switched Ethernet (FDSE). FDSE network nodes have an exclusive point-to-point link connected to a central Ethernet switch. Even low-cost solutions of the FDSE show high switching performance with low latency and jitter in the range of tens of microseconds [6]. When two end nodes exchange traffic over a simple star topology with one switch, it is ensured that other nodes are not interfered by the traffic due to the switching capabilities in the central switch. Based on realistic automotive network scenarios, we assume the following: Traffic from non-safety-critical multimedia applications is considered as event-triggered traffic. Event-triggered nodes do not need to have functionality to detect time slots Event-triggered traffic is not utilized for high priority control applications unlike the time-triggered traffic The amount of time-triggered traffic is small compared to the amount of event-triggered traffic such as bulk and multimedia traffic The number of time-triggered nodes is limited to the controlled environment Allowed delay and jitter for time-triggered traffic is larger than switch latencies (Analyzed in Section III). Several approaches [7] have been introduced for real-time Ethernet switched networks, especially in the automation field. However, those solutions are optimized for industrial control applications where bulk and multimedia traffic are not present. They either employ specific hardware like ProfiNet [8] and EtherCAT [9], or adapt protocols limited for industrial use like the Ethernet Industrial Protocol [10]. The cost of such solutions does not scale to the automotive sector, where a large number of samples is needed for a model range of cars. Another interesting approach is introduced by RTNet [11] that provides a more flexible solution for time critical applications with standardized hardware components. However, RTNet does not allow to connect event-triggered network participants to a switch connected to time-triggered

2 nodes. In this paper, we introduce a low cost and flexible switching mechanism for FDSE networks that can be utilized by both, time-triggered and event-triggered data. II. STATE-OF-THE-ART OF COMMUNICATION CONCEPTS A. Deterministic communication In switched full-duplex Ethernet, data communication is typically not deterministic. Determinism is a property that is very closely linked to real time capability. It describes the exact predictability of a system s time behavior. If it is possible to predict the temporal behavior of a system in all states, then the system is strictly deterministic. Applied to switched Ethernet, determinism can be achieved when [12] 1) the switching delay never exceeds an upper delay bound and 2) no frames are dropped. As mentioned before, in the recent years a number of real time Ethernet variants have emerged in the automation field that can ensure determinism. However, most of these approaches [13] are not built upon a switched network. Some of them may work in a network with one switch, but just a few of them are able to support several cascaded switches. The way to achieve determinism strongly depends on whether the network is designed based on time-triggered or eventtriggered concepts [5]. The following sections describe those concepts from a general point of view. A specific discussion on switched Ethernet and its time behavior will be given afterwards. B. Time-triggered networks In time-triggered networks, network nodes only obtain network access at specific time periods, also called time slots (see figure 1). Therefore, a quasi-deterministic behavior for data transmission can be achieved. The time-triggered concept Fig. 1. Time slots in a time-triggered network potentially provides a good packet loss detection, since, e.g., missing messages are immediately detected [5]. Due to these characteristics, time-triggered networks are primarily used for control engineering applications. The transmission delay time from application to application in a time-triggered network is not necessarily deterministic, because data is transferred through the whole protocol stack and queued in the network node until an appropriate time slot is available. A time-triggered network behaves like a shared medium, even if a star topology (RTnet[11], Flexray [2]) with switches is employed. If possible, network elements inside a time-triggered network are designed for minimal delay times without queues (e.g. FlexRay star coupler). In this way, it can be ensured that data is always transmitted in its respective time slot. In practice, time-triggered networks are used with only a small number of network nodes because of the limited number of time slots. All processes and their time specifications must be known in advance. Accordingly, a drawback of time-triggered approaches is the lack of flexibility e.g. in the data rate and the restrictive design process. An important element in time-triggered networks is the synchronization mechanism. It synchronizes all network nodes in order to ensure that only one member accesses the network at a time. In the following, an overview is given on potential synchronization mechanisms together with their characteristics. 1) Synchronization mechanisms: a) NTP/SNTP: Network Time Protocol is the most well-known synchronization method. It relies on sophisticated mechanisms to access national time. NTP [14] supports the peer to peer communication and adjusts the local clock in each participating peer. SNTP [15] targets simpler synchronization purposes. Both are used for WAN and LAN synchronization where microsecond accuracy is not required and millisecond precision is sufficient. However, some vendors in the automation field have managed to include NTP/SNTP into Fast Ethernet switches [16] with time accuracies better than 1µs. b) IEEE 1588: The standard IEEE 1588 [17] specifies a protocol for a precise clock synchronization for networked measure and control systems. The protocol is called PTP (Precision Time Protocol). It realizes highly precise synchronizations in the microsecond range. The achievable accuracy mainly depends on the kind of implementation. In order to achieve better accuracy, time stamps should be generated in the hardware or close to the hardware. PTP is based on the master/slave principle. The master clock sends synchronization messages to the slave clocks with the exact sending time and the protocol stack latency. Thus, the slave can adjust its clock to the transmission time. c) TDMA-based synchronization: Similar to some deterministic Ethernet realizations such as the RTnet[11], the synchronization of the network participants can be performed by a time slot-based MAC discipline, the so called Time Division Multiple Access (TDMA). The synchronization mechanism of TDMA is performed in a master/slave principle. The timing master issues synchronization messages in the beginning of each TDMA cycle. Thus, the network nodes are able to manage the transmission time of their payload packets relative to the master s periodic synchronization messages.

3 TDMA-based synchronization is mostly used in small shared medium networks, where synchronization frames are not burdened by queuing delays. C. Event-triggered networks In event-triggered networks, network nodes may obtain network access at any time instant. There is no time synchronization between network nodes and therefore, network delay occurs due to media access and queuing mechanisms in the network (see Figure 2). Because of this Fig. 3. Priority queues in a switch port conveying a combination of large and small packets. The delay is caused if a small packet enters the highest priority queue while a large packet from a lower priority queue is being sent. Figure 4 shows such a case where a continuous sequence of small packets is interrupted by the occurrence of a large packet. Fig. 2. Occurrence of event B during transmission time of message A behavior, event-triggered networks are generally characterized as non-deterministic. However, they can be made deterministic when designing a network according to certain restrictions. An example is AFDX (Avionics Full-Duplex Switched Ethernet, [18]). In contrast to control engineering applications which are realized by the Time-triggered concept, applications in event-triggered networks come historically from the IT-world. They are designed in a way that they can tolerate an unknown duration of the network delay. A big advantage of event-triggered networks is the fast reaction to asynchronous events occurring at unknown times. Dependent on the network throughput capacity and the network load, event-triggered networks sometimes show a better real-time performance in comparison to the timetriggered systems. Network elements in an event-triggered network have less complexity, because they do not need to be equipped with time synchronization components. III. ANALYSIS OF SWITCH LATENCIES A. Quality of Service (QoS) and Head-of-Line Blocking (HoLB) Today s Ethernet switches may support priority scheduling by containing two or more output queues per port, where the high priority queue(s) is(are) reserved for time critical data offering improved Quality of Service (QoS). Depending on different possible scheduling schemes, the switch scheduler alternates between the priority queues (see Figure 3). Priority identification can be performed based on physical Ethernet ports, MAC addresses, priority tagging according to IEEE 802.1p [19] or higher layer information. Independent of the applied scheduling algorithm, packets in the queue with the highest priority can be delayed by packets in lower priority queues due to head-of-line blocking (HoLB). Head-of-line blocking is a common problem for networks Fig. 4. Head-of-line blocking The worst case delay will happen if the transmission of an Ethernet packet with the maximum length (i.e bytes) has just started. In the case of 100 Mbit/s data rate the extra delay will be 122 µs, which is a significant amount of time for some time critical applications. In a star topology with Full-Duplex Ethernet, head-of-line blocking only occurs when different traffic flows collide in an output port of a switch. It should be mentioned that time critical end nodes are usually realized in embedded systems and only feature a single traffic flow. Therefore, head-of-line blocking does not occur on the last output port towards such devices. Figure 5 shows an example of a network in star topology. It can be seen that QoS problems caused by head-of-line blocking have to be considered between switches as well as on the links to network nodes with more than one application process. Additionally, broadcast and multicast traffic have a strong influence on all output queues in the network. Packet sizes of the broadcast traffic are traditionally rather small since broadcasting is used by ARP (Address Resolution Protocol), routing protocols etc. Unlike the broadcast traffic, the Multicast traffic may have large packet sizes, in particular when used for multimedia streaming. This may entail unacceptable delay times due to the long head-of-line blockings. Several approaches are proposed in the literature to solve the head-of-line blocking problem in switched Ethernet networks. However, most of them require both software and hardware modifications. A good example is the time-triggered Ethernet implementation presented in [20]. An intelligent scheduling

4 Fig. 5. An example for Connections affected by head-of-line blocking mechanism interrupts the transmission of low prioritized data when data with higher priority has to be sent. The data with lower priority will be stored in the switch and sent to its destination address as soon as the high priority data is completely transmitted. B. Worst case switch latency calculation with priorities Figure 6 shows how a single frame is delayed by a storeand-forward switch. Network transmission capacity (10 Mbit/s, 100 Mbit/s, 1000 Mbit/s) Scheduling scheme (round-robin scheduling, strict priority scheduling) Packet size of time-triggered and event-triggered packets Head-of-line blocking Switch forwarding method (store-and-forward, cut through) An example for the potentially large switch delay can be found in [21] where the worst case delay of t sw =228 µs consists of the following components: t sf = 16 µs: Store-and-forward delay t sp = 10 µs: Minimum switch latency t holb = 122 µs: Head-of-line blocking t queue = 80 µs: Assuming that five real-time packets are already in the same priority queue. In a time slot method, this delay does not occur, since it is ensured that only one real-time frame may enter the queue at a time. It can be seen that the largest contribution to the worst-case delay stems from the head-of-line blocking. The average delay is significantly lower and lies in the range of 10 to 50 µs for 100 Mbit/s switches [6]. In the case of cascaded switches, the network can be designed by using different segments in order to reduce the end to end transmission delay. A reasonable way is to use network segments with higher throughput capacity for inter-switch connections where the data traffic is higher and segments with lower transmission rates for connections to the end nodes. Figure 7 shows this proposal with two switches using the time delay values from Figure 6. Fig. 6. Latency for one 100 Mbit/s switch without influence of other frames and empty queues For an empty input queue, a frame has to wait in the input queue only until all of its own bytes have been received (store and forward delay t sf = t 1 t 0 ). When the frame has been fully received it is processed by the switch fabric and forwarded to the respective output port (switch processing time t sp = t 2 t 1 ). In the same way as for the input ports, a store and forward delay is added by the output port (t sf = t 3 t 2 ). The total switch delay t sw however, is the time span from t 1 to t 3, since the input queues of receiving switches and the output queues of sending switches are filled at the same time. Hence, when also considering the head-of-line blocking the switch delay time can be written as: t sw = t sf + t sp + t holb (1) In general, the delay for a high priority packet when passing through an Ethernet switch depends on: Fig. 7. Latency for two switches and different transmission rates The 1000 Mbit/s inter-switch connection speeds up the data transmission. The 5 µs transmission time for a 64 byte frame at 100 Mbit/s segments is thus reduced to 0.5 µs. Accordingly, by an optimized network design the problem of transmission delay can be significantly reduced. We have so far presented the concepts of time-triggered and event-triggered networks. An introduction to the switches and their time behavior in switched Ethernet networks has also

5 been given. In the next section, a new approach is presented that satisfies the requirements of both, time-triggered and event-triggered applications. The mentioned head-of-line blocking issue is explicitly analyzed. IV. COOPERATIVE TIME SLOT MECHANISM In this section we propose a new mechanism to ensure coexistence of time- and event-triggered traffic over FDSE. connected to the switch. The clock generator can be realized by all three synchronization mechanisms mentioned in the Section 3. In the case of TDMA-based synchronization, the clock is treated like a time-triggered node itself, because the synchronization takes place in predefined time slots. However, when time synchronization is performed at arbitrary times, e.g. by using NTP or IEEE1588, potential queuing delays of synchronization packets lead to decreased clock accuracy. A. Time-triggered traffic in FDSE networks When using a time slot mechanism with switches, it has to be ensured that frames are always transmitted within the respective time slot intervals. Figure 8 shows an example of four time slots with different path delays. Frame A in the first time slot represents the frame at the sending node, whereas A denotes the respective frame at the receiving node. Depending on the topology, the delay on path A may consist of one or several switch delays. The frame size for timetriggered transmissions may vary as much as the transmission still fits into the respective time slot (time slot B). For cutthrough switches, it may also be possible that sending and receiving frames overlap (time slot C). The special case shown in time slot D is hypothetical for a case without switches. In some cases, the timing requirements of distributed control applications are very strict and only the case shown in time slot D would comply with the requirements. These cases are out of scope of this paper. Fig. 9. Cooperative time slot mechanism Fig. 8. Example for time slots in a delay-affected network In the following, we consider a case similar to the above mentioned A and B frame transmissions, i.e. there are several cascaded store and forward switches between the sender and receiver nodes. B. Time- and event-triggered traffic in FDSE networks In order to manage both, time-triggered and the eventtriggered applications in a FDSE network, we propose differently prioritized queues for switch ports. As a compromise, two queues per each port, one for the time-triggered and one for the event-triggered data seem to be sufficient. We call this approach Cooperative time slot mechanism, because it enables the interconnection of time-triggered and eventtriggered devices via one switch. Figure 9 shows this idea for one switch, two event-triggered nodes and two time-triggered nodes. The time slots are generated by a clock generator As mentioned in Section 5, the incoming packets are assigned to appropriate queues depending on their priorities. Time-triggered packets are assigned with high priority while event-triggered packets have a low priority. If a time-triggered node sends a data packet to another time-triggered node, it first uses its respective time slot to access the network at a predefined time. In the switch, the data packet will be forwarded to the respective high-priority output queue. By using a priority scheduling mechanism in the switch, high priority packets are transmitted earlier than event-triggered packets queued in the low-priority output queue at the same output port. However, time-triggered packets are still influenced by head-of-line blocking from event-triggered packets. Event-triggered nodes may send traffic at any time, since they do not need to be aware of time slots. They mark their traffic with a lower priority, e.g., by using IEEE 802.1p tags. 1) Performance analysis for cascaded switches with a constant data rate: In order to determine the efficiency of the cooperative time slot mechanism, we calculate the worst case latency for the time-triggered data communication. Being the pessimistic upper bound, the worst-case latency is a very important value in order to obtain a certification of the approach for automotive systems. A common method to calculate worst case latencies is Network Calculus [22]. In our calculation, we

6 do not utilise this approach because the environment allows a simplified calculation. The reason for this simplification is, that the worst-case latency does not depend on any input traffic specification. The time-slot mechanism ensures that only one time-triggered packet can arrive at a certain time interval. The use of strict priority scheduling also guarantees that there is never more than one packet in the high priority queue. Therefore, the calculation for the worst case latency can be done by making certain assumptions about the network we are dealing with. Following assumptions are set forth: All switches in the network are store and forward switches with the values defined for the switch delay t sw in equation (1) All receiving and sending ports are functioning independently (HW router and full-duplex) Packet source and sink are separated by n switches The generated time slots are adjacent to each other, there are no time gaps between them Equation (2) gives the store and forward delay as a function of the packet size for time-triggered packets (P TT ) in bytes and the transmission bitrate b in bits/s. In the same way, Equation (3) considers the fact that head-of-line blocking is caused by frames with the size P ET. t sf = P TT 8 b t holb = P ET 8 (3) b In a time slot method, the maximum number of timetriggered nodes depends on the cycle time t cycle, the number of cascaded switches n as well as the worst case switch delay t sw. Considering the assumptions mentioned above, equations (2), (3) and a constant data rate between the source and sink, we achieve k for the possible number of time-triggered nodes in the network: t n t sw = cycle n (t sf +t sp+t holb ) t = ( cycle PT n T 8 b +t sp+ P ET 8 b k = t cycle (2) ) (4) Maximum time triggered nodes Number of cascaded switches Fig. 10. Maximum number of time-triggered nodes with t sp= 10 µs, P TT = 64 bytes, P ET = 1518 bytes, t cycle = 2 ms and b = 100 Mbit/s as a function of the number of switches number of time-triggered nodes and switches according to the results achieved in Figure 10. In the same way, the number of possible time-triggered nodes in a switched network can be calculated depending on the size of event-triggered packets entailing head-of-line blocking. Figure 11 shows the result assuming three switches between the packet source and sink. According to Figure 11, the larger Maximum time triggered nodes In the worst case, the event-triggered packet P ET entailing head-of-line blocking has the maximum packet size, e.g., 1518 bytes for Ethernet packets while the time-triggered packet P TT is small, e.g., 64 bytes. By applying equation (4) and the minimum switch processing time t sp = 10 µs from [21], we achieve the result presented in Figure 10 for the number of time-triggered nodes dependent on the number of cascaded switches in the network. It can be seen that the possible number of time-triggered nodes decreases by increasing the number of switches. This result confirms our statement that the delay caused by switches influences the entire transmission time. In order to fulfill the deterministic communication requirements in a switched full-duplex Ethernet network a trade-off should be made between the Event triggered frame size Fig. 11. Maximum number of time-triggered nodes with t sp= 10 µs, P TT = 64 bytes, n = 3, t cycle = 2 ms and b = 100 Mbit/s as a function of P ET the event-triggered frame sizes are, the lower the number of time-triggered nodes should be to be able to fulfill the deterministic communication requirements. To sum up, the cooperative time slot mechanism supports a limited number of time-triggered nodes in coexistence with event-triggered traffic. The maximum number of time-triggered nodes can be increased by limiting the number of cascaded switches or the event-triggered frame sizes.

7 50 2) Performance improvement with high data rate interswitch connections: So far, we analyzed the performance of the cooperative time slot mechanism for time-triggered applications in a network with a single throughput capacity, e.g. 100 Mbit/s. However, as mentioned in the last section, the performance of a switched network can be improved by optimizing its design. According to Figure 7, we propose a design with two different throughput capacities, i.e., 1000 Mbit/s segments for the inter-switch connections and 100 Mbit/s segments for the connections to end nodes. Considering this proposal for the network design, we continue our calculations in the following. The number of possible time-triggered nodes k can now be calculated as: Maximum time triggered nodes Event triggered frame size k = t cycle ( n t sp+ P T T 8 b + P ET 8 PT ) 1 b +(n 1) T 8 1 b + P ET 8 2 b 2 (5) Fig. 13. Maximum number of time-triggered nodes with t sp= 10 µs, P TT = 64 bytes, n = 3, t cycle = 2 ms and b = 100 Mbit/s as a function of P ET (solid curve) compared with a network with different bit rates b 1 = 100 Mbit/s and b 2 = 1000 Mbit/s (dashed curve). Where b 1 is equal to 100 Mbit/s and b 2 is 1000 Mbit/s. Figures 12 and 13 show the corresponding performance Maximum time triggered nodes Number of cascaded switches Fig. 12. Maximum number of time-triggered nodes with t sp= 10 µs, P TT = 64 bytes, P ET = 1518 bytes, t cycle = 2 ms and b = 100 Mbit/s as a function of the number of switches (solid curve) compared with a network with different bit rates b 1 = 100 Mbit/s and b 2 = 1000 Mbit/s (dashed curve). improvements compared with the results achieved with only 100 Mbit/s segments. It can be seen that by optimizing the network design, the number of possible time-triggered nodes increases significantly for the same number of cascaded switches and event-triggered frame size compared to the results achieved with the constant bit rate. V. CONCLUSIONS AND FUTURE WORK In this paper, the principles of switched full-duplex Ethernet networks for deterministic communication systems have been presented. General requirements of deterministic communication systems have been analyzed. The two main network design concepts, time-triggered and event-triggered principles have been introduced. The time behavior of switches and the influence of switch delays on the entire transmission path have been analyzed and calculated for several cascaded store and forward switches. Head-of-line blocking turned out to be the main switch delay factor with values more than 100 µs. A new approach called Cooperative Time Slot Mechanism has been introduced. By taking advantage of parallel queuing mechanisms in switches, the method allows time-triggered and event-triggered traffic to pass switches without interferences. The approach is based on the assumption that the eventtriggered traffic is made up of bulk or multimedia traffic with generally lower priority than the time-triggered traffic. The analysis of delay restrictions shows the possibility to design such a network by limiting the number of switches, or limiting the size of event-triggered frames, or by adding high data rate inter-switch connections. Based on the choice of parameters, a network can be realized to support timetriggered and event-triggered traffic without the need for two separate networks. The approach works with all standard FDSE switches featuring strict priority queuing on their output ports. In the future work, we will analyze the possibilities to add event-triggered traffic with high priority to the cooperative time slot mechanism. In addition, we will study mechanisms to support distributed control applications with very strict timing requirements. Furthermore, applicable synchronization mechanisms for the time-triggered traffic will be investigated.

8 REFERENCES [1] Robert Bosch GmbH. CAN Specification, Version 2.0, [2] FlexRay Consortium. FlexRay Communications System, Protocol Specification, Version 2.1, [3] OASIS Silicon Systems. MOST Media Oriented System Transport, Multimedia and Control Networking Technology, Rev. 2.4, [4] Nicolas Navet et al. Trends in automotive communication systems. Proceedings of IEEE, 93(6), June [5] Amos Albert. Comparison of event-triggered and time-triggered concepts with regard to distributed control systems. Embedded World 2004, pages , [6] John Wernicke. Simulative analysis of QoS in avionics networks for reliably low latency. wernicke.html, [7] Kai Lorenz Arndt Lüder, editor. IAONA Handbook - Industrial Ethernet. Industrial Automation, Open Networking Alliance e.v., Universittsplatz 2, Magdeburg, Germany, 3rd edition, [8] Siemens AG. IEC/PAS Real-time Ethernet PROFINET IO. International Electrotechnical Commission (IEC), webstore/webstore.nsf/artnum/034395, [9] EtherCAT Technology Group (ETG). Ethercat ethernet control automation technology, publicly available specification. International Electrotechnical Commission (IEC), webstore.nsf/artnum/034392, [10] ODVA Association. Common industrial protocol (cip). org. [11] Jan Kiszka et al. RTNet - a flexible hard real-time networking framework. Emerging Technologies and Factory Automation 2005, EFTA 2005, 1, [12] Dinesh C. Verma, Hui Zhang and Domenico Ferrari. Delay jitter control for real-time communication in a packet switching network. In Proceedings of Tricom 91, [13] Lueder A and K. Lorentz. IAONA Handbook Industrial Ethernet, [14] David L. Mills. RFC 1305, Network Time Protocol (Version 3), Specification, Implementation and Analysis. IETF, [15] J. Burbank et al. RFC 4330, Simple Network Time Protocol (SNTP) Version 4 for IPv4, IPv6 and OSI. IETF, [16] On time networks. [17] Dominic Bechaz Hans Weibel. Ieee 1588 implementation and performance of time stamping techniques. Conference on IEEE 1588, [18] Condor Engineering. AFDX / ARINC 664 Tutorial ( ). http: // [19] IEEE Project 802. IEEE 802.1p: Supplement to MAC Bridges: Traffic calss expediting and dynamic multicast filtering. Incorp. in IEEE Standard 802.1D, Part 3: Media Access Control (MAC) Bridges, [20] Peter Grillinger Hermann Kopetz, Astrit Ademaj and Klaus Steinhammer. The time-triggered ethernet (tte) design. Vienna University of Technology, Real-Time Systems Group, Proceedings of the Eighth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 05), [21] Oe. Holmeide and T. Skeie. VoIP drives the Realtime Ethernet. Industrial Ethernet Book (IEB), 5, [22] Jean-Yves Le Boudec and Patrick Thiran. Network calculus: a theory of deterministic queuing systems for the internet. Springer-Verlag New York, Inc., New York, NY, USA, 2001.