Lecture 8: Virtual Memory. Today: DRAM innovations, virtual memory (Sections )

Transcription

1 Lecture 8: Virtual Memory Today: DRAM innovations, virtual memory (Sections ) 1

2 DRAM Technology Trends Improvements in technology (smaller devices) DRAM capacities double every two years, but latency does not change much Power wall: 25-40% of datacenter power can be attributed to the DRAM system Will soon hit a density wall; may have to be replaced by other technologies (phase change memory, STT-RAM) Interconnects may have to be photonic to overcome the bandwidth limitation imposed by pins on the chip 2

3 Latency and Power Wall Latency and power can be both improved by employing smaller arrays; incurs a penalty in density and cost Latency and power can be both improved by increasing the row buffer hit rate; requires intelligent mapping of data to rows, clever scheduling of requests, etc. Power can be reduced by minimizing overfetch either read fewer chips or read parts of a row; incur penalties in area or bandwidth 3

4 Density Wall New emerging non-volatile memories that have better scalability; instead of storing data in the form of charge, data encoded in cell resistance (phase change memory) or in electron spin (spin torque transfer STT-RAM) Phase change memory: the cell can be either amorphous (high resistance, represents zero) or crystalline (low resistance, represents one) Data is written by heating the material and cooling it at different rates (with electrical pulses); short intense pulse amorphous; long medium pulse crystalline 4

5 Phase Change Memory Can also have multi-level cells; each resistance value represents a different encoding; enables scalability Each cell can only be written about 10 times; need many tricks to improve endurance: write on change, shift bits within a row, re-map data to rows, etc. Reads are relatively quick (~50 ns), writes are very slow (~1000 ns) Has potential to replace DRAM, disk, or both in at least some classes of computers 8 5

6 Photonics A single waveguide carries light that was generated off-chip to multiple nodes The nodes can act as transmitters or receivers; transmitters can vary the amplitude of a light signal based on the input electrical signal Since multiple light wavelengths can be multiplexed on a waveguide and because each wavelength can carry a different signal, photonic interconnects have high bandwidth The E O and O E conversion overhead means that the photonic signal must travel far enough to out-do an electrical interconnect in terms of latency and power 6

7 Virtual Memory Processes deal with virtual memory they have the illusion that a very large address space is available to them There is only a limited amount of physical memory that is shared by all processes a process places part of its virtual memory in this physical memory and the rest is stored on disk Thanks to locality, disk access is likely to be uncommon The hardware ensures that one process cannot access the memory of a different process 7

8 Address Translation The virtual and physical memory are broken up into pages 8KB page size Virtual address Translated to phys page number virtual page number 13 page offset Physical address physical page number 13 page offset Physical memory 8

9 Memory Hierarchy Properties A virtual memory page can be placed anywhere in physical memory (fully-associative) Replacement is usually LRU (since the miss penalty is huge, we can invest some effort to minimize misses) A page table (indexed by virtual page number) is used for translating virtual to physical page number The memory-disk hierarchy can be either inclusive or exclusive and the write policy is writeback 9

10 TLB Since the number of pages is very high, the page table capacity is too large to fit on chip A translation lookaside buffer (TLB) caches the virtual to physical page number translation for recent accesses A TLB miss requires us to access the page table, which may not even be found in the cache two expensive memory look-ups to access one word of data! A large page size can increase the coverage of the TLB and reduce the capacity of the page table, but also increases memory wastage 10

11 TLB and Cache Is the cache indexed with virtual or physical address? To index with a physical address, we will have to first look up the TLB, then the cache longer access time Multiple virtual addresses can map to the same physical address can we ensure that these different virtual addresses will map to the same location in cache? Else, there will be two different copies of the same physical memory word Does the tag array store virtual or physical addresses? Since multiple virtual addresses can map to the same physical address, a virtual tag comparison can flag a miss even if the correct physical memory word is present 11

12 Virtually Indexed Caches 24-bit virtual address, 4KB page size 12 bits offset and 12 bits virtual page number To handle the example below, the cache must be designed to use only 12 index bits for example, make the 64KB cache 16-way Page coloring can ensure that some bits of virtual and physical address match abcdef abbdef Virtually indexed cache cdef bdef Page in physical memory Data cache that needs 16 index bits 64KB direct-mapped or 128KB 2-way 12

13 Cache and TLB Pipeline Virtual page number TLB Physical page number Virtual address Virtual index Tag array Offset Data array Physical tag comparion Physical tag Virtually Indexed; Physically Tagged Cache 13

14 Lecture 8: Virtual Memory, Large Caches Today: virtual memory, shared/pvt caches, NUCA caches 14

15 Virtual Memory Processes deal with virtual memory they have the illusion that a very large address space is available to them There is only a limited amount of physical memory that is shared by all processes a process places part of its virtual memory in this physical memory and the rest is stored on disk Thanks to locality, disk access is likely to be uncommon The hardware ensures that one process cannot access the memory of a different process 15

16 Address Translation The virtual and physical memory are broken up into pages 8KB page size Virtual address Translated to phys page number virtual page number 13 page offset Physical address physical page number 13 page offset Physical memory 16

17 Memory Hierarchy Properties A virtual memory page can be placed anywhere in physical memory (fully-associative) Replacement is usually LRU (since the miss penalty is huge, we can invest some effort to minimize misses) A page table (indexed by virtual page number) is used for translating virtual to physical page number The memory-disk hierarchy can be either inclusive or exclusive and the write policy is writeback 17

18 TLB Since the number of pages is very high, the page table capacity is too large to fit on chip A translation lookaside buffer (TLB) caches the virtual to physical page number translation for recent accesses A TLB miss requires us to access the page table, which may not even be found in the cache two expensive memory look-ups to access one word of data! A large page size can increase the coverage of the TLB and reduce the capacity of the page table, but also increases memory wastage 18

19 TLB and Cache Is the cache indexed with virtual or physical address? To index with a physical address, we will have to first look up the TLB, then the cache longer access time Multiple virtual addresses can map to the same physical address can we ensure that these different virtual addresses will map to the same location in cache? Else, there will be two different copies of the same physical memory word Does the tag array store virtual or physical addresses? Since multiple virtual addresses can map to the same physical address, a virtual tag comparison can flag a miss even if the correct physical memory word is present 19

20 Virtually Indexed Caches 24-bit virtual address, 4KB page size 12 bits offset and 12 bits virtual page number To handle the example below, the cache must be designed to use only 12 index bits for example, make the 64KB cache 16-way Page coloring can ensure that some bits of virtual and physical address match abcdef abbdef Virtually indexed cache cdef bdef Page in physical memory Data cache that needs 16 index bits 64KB direct-mapped or 128KB 2-way 20

21 Cache and TLB Pipeline Virtual page number TLB Physical page number Virtual address Virtual index Tag array Offset Data array Physical tag comparion Physical tag Virtually Indexed; Physically Tagged Cache 21

22 Superpages If a program s working set size is 16 MB and page size is 8KB, there are 2K frequently accessed pages a 128-entry TLB will not suffice By increasing page size to 128KB, TLB misses will be eliminated disadvantage: memory wastage, increase in page fault penalty Can we change page size at run-time? Note that a single page has to be contiguous in physical memory 22

23 Superpages Implementation At run-time, build superpages if you find that contiguous virtual pages are being accessed at the same time For example, virtual pages may be frequently accessed coalesce these pages into a single superpage of size 128KB that has a single entry in the TLB The physical superpage has to be in contiguous physical memory the 16 physical pages have to be moved so they are contiguous virtual physical virtual physical 23

24 Ski Rental Problem Promoting a series of contiguous virtual pages into a superpage reduces TLB misses, but has a cost: copying physical memory into contiguous locations Page usage statistics can determine if pages are good candidates for superpage promotion, but if cost of a TLB miss is x and cost of copying pages is Nx, when do you decide to form a superpage? If ski rentals cost $20 and new skis cost $200, when do I decide to buy new skis? If I rent 10 times and then buy skis, I m guaranteed to not spend more than twice the optimal amount 24

25 Protection The hardware and operating system must co-operate to ensure that different processes do not modify each other s memory The hardware provides special registers that can be read in user mode, but only modified by instrs in supervisor mode A simple solution: the physical memory is divided between processes in contiguous chunks by the OS and the bounds are stored in special registers the hardware checks every program access to ensure it is within bounds 25

26 Intel Montecito Cache Two cores, each with a private 12 MB L3 cache and 1 MB L2 Naffziger et al., Journal of Solid-State Circuits,

27 Intel 80-Core Prototype Polaris Prototype chip with an entire die of SRAM cache stacked upon the cores 27

28 Memory interface Example Intel Studies C L1 C L1 C L1 C L1 C L1 C L1 C L1 C L1 L2 L2 L2 Interconnect L2 L3 IO interface From Zhao et al., CMP-MSI Workshop 2007 L3 Cache sizes up to 32 MB 28

29 Shared Vs. Private Caches in Multi-Core What are the pros/cons to a shared L2 cache? P1 P2 P3 P4 P1 P2 P3 P4 L1 L1 L1 L1 L1 L1 L1 L1 L2 L2 L2 L2 L2 29

30 Shared Vs. Private Caches in Multi-Core Advantages of a shared cache: Space is dynamically allocated among cores No wastage of space because of replication Potentially faster cache coherence (and easier to locate data on a miss) Advantages of a private cache: small L2 faster access time private bus to L2 less contention 30

31 UCA and NUCA The small-sized caches so far have all been uniform cache access: the latency for any access is a constant, no matter where data is found For a large multi-megabyte cache, it is expensive to limit access time by the worst case delay: hence, non-uniform cache architecture 31

32 Large NUCA Issues to be addressed for Non-Uniform Cache Access: Mapping CPU Migration Search Replication 32