Mohsen Imani. University of California San Diego. System Energy Efficiency Lab seelab.ucsd.edu

Size: px
Start display at page:

Download "Mohsen Imani. University of California San Diego. System Energy Efficiency Lab seelab.ucsd.edu"

Transcription

1 Mohsen Imani University of California San Diego Winter 2016

2 Technology Trend for IoT ngs/2014/ _304c_hill.pdf 2

3 Motivation IoT significantly increases the amount of computation and data generation Amount of generated information surpassed 1.8 zettabytes which will be increased by 50% in 2020! The rate of data generation is beyond the capability of current computing systems. Energy efficient data storage and computing! 3

4 Motivation How to improve IoT storage and computation? Efficient large storage to store big data Non-volatile memory Energy efficient computing Approximate computing Near data computing (in-memory processing) Neuromorphic computing (parallel processing) Efficient computing with NVMs! 4

5 NVM Requirements in IoT Context Non-volatile memory requirement for IoT devices? Minimize cost and area Field programmability Minimize start-up time Low voltage, low power Provide secure data storage 5

6 NVM Requirements in IoT Context Minimize Cost and Area Because many IoT devices will have to be very inexpensive and small Minimize any additional wafer processing cost due to extra masks or processing Field Programmability For setting user preferences or updating keys need to be programmable during: chip manufacturing, test, when installed in end-user equipment Minimize start-up time NVM should be fast enough to allow executing code directly Avoiding the need to copy code to RAM for execution and reducing boot-up time 6

7 NVM Requirements in IoT Context Low Voltage, Low Power IoT ecosystem will run on small batteries Battery replacement may be difficult or even impossible Devices convert motion, light, heat or an electromagnetic field into the electrical energy needed to power the sensor Embedded memory with low standby and operating power dissipation Provide Secure Data Storage Many applications involving the exchange of sensitive data, such as financial transactions Memory must have a high level of physical security and be extremely difficult to reverse engineer 7

8 Traditional Memory Hierarchies Why SRAM as Cache? Why DRAM as main memory? Why Flash as SSD? Why HDD as Secondary storage? Speed Density Non-volatility + Price Price 8

9 NVRAM Comparison High density, low leakage, non-volatile 9

10 STT-RAM: Spin-Transfer Torque RAM STT-RAM: Spin-Transfer Torque RAM The spin torque direction of electrons to flip a bit in a magnetic tunneling junction (MTJ) Advantage: High read performance High endurance! Disadvantage: Write energy: high amount of current needed to reorient the magnetization for most commercial applications Write latency: low ON/OFF resistance ratio (~2) Asymmetric write: writing 1s needs much more time and energy than writing zero (a) The Structure of MTJ (b) Parallel: bit 0 (low Resistance) (c) Anti-Parallel: bit 1 (high Resistance)

11 Domain Wall Memory (DWM) Domain Wall Memory (DWM) Similar to STT-RAM structure Advantage: Needs only one tunneling barrier and fixed layer area saving Disadvantage: Complexity in design, Write delay Ferromagnetic tape Domain Wall Free Layer Domain Fixed Layer MTJ Extra Domains 11

12 Shift-based DWM Shift-based DWM Write by shifting data of one of the two fixed layers with the desirable direction comp Advantage: fast write operation than DWM Disadvantage: Complexity on design Polarized direction (a) 1-bit DWM Fast (b) Multi-bit DWM Area efficient, but needs extra latency for shifting

13 PCM: Phase Change Memory Phase Change Memory (PCM) Flips a bit by changing the state of material Crystalline (SET) and amorphous (RESET) phase Advantage: Better scalability than other emerging technologies. Very high density! Disadvantage: Slow in write (asymmetric write operation) Low endurance (10 7 ) PCM Cell Phases Candidate for DRAM replacement PCM Operations

14 ReRAM: Resistive RAM Types: Access-based and crossbar ReRAM Access-based ReRAM (1T-1R) A dialectric, which is normally insulating can be made to conduct through after application of a sufficiently high voltage Advantage: Very fast in both read and write ~ 20ns Very high density Disadvantage: Limited endurance (10 5 ) Working mechanism of ReRAM 14

15 ReRAM: Resistive RAM Crossbar ReRAM (1T-nR) Advantage: Highly scalable Can be implemented at the top of the chip with in 3D architecture Very low energy consumption Low cost Replace with Cache? DRAM? Flash? Hard? Disadvantage: Much slower than 1T-1R ~us Crossbar ReRAM

16 Crossbar RRAM in IoT Crossbar 1T-nR 1T-1R 16

17 Existing NV Memory Technology Comparison 17

18 NVMs Comparison STT-RAM: SRAM cache replacement PCRAM: DRAM main memory and storage ReRAM: NAND Flash, embedded NOR

19 Approximate Computing Why today s systems waste time, energy, and complexity to provide uniformly fresh operation for applications that do not require it? The idea that we are hindering computer systems efficiency by demanding too much accuracy from them. IoT applications are fundamentally approximate such as machine learning, speech recognition, search, graphics, and physical simulation 19

20 Approximation Where approximation can apply? CPU GPU Accelerators Storage In which level? Circuit Architecture Software 20

21 Circuit Level Approximation Applying voltage overscaling on circuits New nano-scaled technologies and variability issues! Probability of having multiple errors in different process corners Designing approximate building blocks with very lower energy consumption E.g. 4-bit XOR gates accept wrong answer in some set of inputs Mostly focus on adder and multiplier which are building block of DSPs, ALUs, etc. 21

22 GPU-Acceleration Several streaming IoT applications need to be accelerated using parallel processors such as GPUs Requires energy efficient computing Lookup table (associative memory): Promising memory to reduce the energy consumption of parallel processing Pre-stores frequent patterns and their corresponding output Retrieve them in runtime in case of repeating 22

23 Associative Memory Integration Searches associative memory (TCAM) in parallel with FPU processing in a single cycle Hit in TCAM stops FPU computation using clock gating This hit activates the corresponding row of ReRAM memory to read the result of computation Is there any approximation? 23

24 Limitation of Associative Memory TCAM consumes high energy consumption for each search, with high switching activity They need to search entire table so fast in single cycle! How to reduce their energy? using NVM based TCAM Zero leakage power for keeping the data Very high density The energy is still high because of high match-line activity 24

25 Approximate Computing Applying voltage overscaling on TCAM Accept the data matching with 1-2 bits hamming distance E.g input matches with Pros: Very low TCAM search energy under voltage overscaling Increasing TCAM hit-rate higher average time that FPU is clock gated! High energy saving!! 25

26 Approximate Computing Approximate matches degrade computation accuracy, because we consider =4! For multimedia application PSNR >30dB guarantees the accuracy 26

27 Approximate Computing How to reduce accuracy degradation? Relaxing the computation on least significant bits Accepting NO mismatch on MSBs E.g ~ but Is NOT Voltage Relaxation Buffer MLs TCAM Cell TCAM Cell TCAM Cell Applications have different accuracy requirements Tunable approximation TCAM Cell TCAM Cell TCAM Cell Sense Amplifiers EnL Framework to support new applications TCAM Cell TCAM Cell TCAM Cell 27

28 Approximate Computing Bitline-configurable achieve to 43.6% energy savings Row-configurable achieves 44.5% energy savings Acceptable quality loss of 10% 28

29 Other State of The Art Techniques How we can speed up computation with less impact on accuracy? Neuromorphic Computing Approximation reduces computation energy consumption. What about data movement energy? Near Data Computing 29

30 Neuromorphic Computing Computation which works based on human neurons, also called brain-inspired computing All bits have the same impact on computation Fast and parallel computing High potential to reduce the computation error on approximation or process variation Can be implemented on crossbar memristive devices Requires building block to do basic computations such as dot product, XOR, etc. 30

31 Near Data Computing Processing in-memory Bring computation closer to data From computer-centric to data-centric model Old concept, but renewed interest due to: New technologies (NVM, 3D) Technology trends Big data 31

32 Summary IoT increases the rate of data generation over the world which requires: Energy efficient computing Large and efficient storage Non-volatile memories can be used to improve both energy efficiency and storage systems High density NVM storage with nearly zero leakage power Approximate computing, near data computing and neuromorphic computing using NVM-devices 32

Memory in Embedded Systems. Tajana Simunic Rosing Department of Computer Science and Engineering University of California, San Diego.

Memory in Embedded Systems. Tajana Simunic Rosing Department of Computer Science and Engineering University of California, San Diego. Memory in Embedded Systems Tajana Simunic Rosing Department of Computer Science and Engineering University of California, San Diego. Hardware platform architecture Traditional Memory Hierarchies Why SRAM

More information

Emerging NV Storage and Memory Technologies --Development, Manufacturing and

Emerging NV Storage and Memory Technologies --Development, Manufacturing and Emerging NV Storage and Memory Technologies --Development, Manufacturing and Applications-- Tom Coughlin, Coughlin Associates Ed Grochowski, Computer Storage Consultant 2014 Coughlin Associates 1 Outline

More information

Test and Reliability of Emerging Non-Volatile Memories

Test and Reliability of Emerging Non-Volatile Memories Test and Reliability of Emerging Non-Volatile Memories Elena Ioana Vătăjelu, Lorena Anghel TIMA Laboratory, Grenoble, France Outline Emerging Non-Volatile Memories Defects and Fault Models Test Algorithms

More information

CSE140: Components and Design Techniques for Digital Systems. Register Transfer Level (RTL) Design. Tajana Simunic Rosing

CSE140: Components and Design Techniques for Digital Systems. Register Transfer Level (RTL) Design. Tajana Simunic Rosing CSE140: Components and Design Techniques for Digital Systems Register Transfer Level (RTL) Design Tajana Simunic Rosing RTL Design Process Example: Simple data encryption/decryption device B =1, set offset

More information

Emerging NVM Enabled Storage Architecture:

Emerging NVM Enabled Storage Architecture: Emerging NVM Enabled Storage Architecture: From Evolution to Revolution. Yiran Chen Electrical and Computer Engineering University of Pittsburgh Sponsors: NSF, DARPA, AFRL, and HP Labs 1 Outline Introduction

More information

CS 320 February 2, 2018 Ch 5 Memory

CS 320 February 2, 2018 Ch 5 Memory CS 320 February 2, 2018 Ch 5 Memory Main memory often referred to as core by the older generation because core memory was a mainstay of computers until the advent of cheap semi-conductor memory in the

More information

Architectural Aspects in Design and Analysis of SOTbased

Architectural Aspects in Design and Analysis of SOTbased Architectural Aspects in Design and Analysis of SOTbased Memories Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril & Mehdi Tahoori INSTITUTE OF COMPUTER ENGINEERING (ITEC) CHAIR FOR DEPENDABLE NANO COMPUTING

More information

Unleashing MRAM as Persistent Memory

Unleashing MRAM as Persistent Memory Unleashing MRAM as Persistent Memory Andrew J. Walker PhD Spin Transfer Technologies Contents The Creaking Pyramid Challenges with the Memory Hierarchy What and Where is MRAM? State of the Art pmtj Unleashing

More information

CSE140: Components and Design Techniques for Digital Systems. Register Transfer Level (RTL) Design. Tajana Simunic Rosing

CSE140: Components and Design Techniques for Digital Systems. Register Transfer Level (RTL) Design. Tajana Simunic Rosing CSE140: Components and Design Techniques for Digital Systems Register Transfer Level (RTL) Design Tajana Simunic Rosing Welcome to CSE 140! Where we are going today: RTL examples, Memory Upcoming: HW6

More information

Will Phase Change Memory (PCM) Replace DRAM or NAND Flash?

Will Phase Change Memory (PCM) Replace DRAM or NAND Flash? Will Phase Change Memory (PCM) Replace DRAM or NAND Flash? Dr. Mostafa Abdulla High-Speed Engineering Sr. Manager, Micron Marc Greenberg Product Marketing Director, Cadence August 19, 2010 Flash Memory

More information

Lecture 8: Virtual Memory. Today: DRAM innovations, virtual memory (Sections )

Lecture 8: Virtual Memory. Today: DRAM innovations, virtual memory (Sections ) Lecture 8: Virtual Memory Today: DRAM innovations, virtual memory (Sections 5.3-5.4) 1 DRAM Technology Trends Improvements in technology (smaller devices) DRAM capacities double every two years, but latency

More information

Toward a Memory-centric Architecture

Toward a Memory-centric Architecture Toward a Memory-centric Architecture Martin Fink EVP & Chief Technology Officer Western Digital Corporation August 8, 2017 1 SAFE HARBOR DISCLAIMERS Forward-Looking Statements This presentation contains

More information

Magnetoresistive RAM (MRAM) Jacob Lauzon, Ryan McLaughlin

Magnetoresistive RAM (MRAM) Jacob Lauzon, Ryan McLaughlin Magnetoresistive RAM (MRAM) Jacob Lauzon, Ryan McLaughlin Agenda Current solutions Why MRAM? What is MRAM? History How it works Comparisons Outlook Current Memory Types Memory Market primarily consists

More information

MRAM Developer Day 2018 MRAM Update

MRAM Developer Day 2018 MRAM Update MRAM Developer Day 2018 MRAM Update Barry Hoberman August 2018 1 Disclaimer Observations and opinions >35 years experience in wide variety of memory >12 years experience in MRAM 2012-2017 CEO/Chairman

More information

Resistive Configurable Associative Memory for Approximate Computing

Resistive Configurable Associative Memory for Approximate Computing Resistive Configurable Associative Memory for Approximate Computing Mohsen Imani CSE, UC San Diego La Jolla, CA 9293, USA moimani@ucsd.edu Abbas Rahimi EECS, UC Berkeley Berkeley, CA 9472, USA abbas@eecs.berkeley.edu

More information

MTJ-Based Nonvolatile Logic-in-Memory Architecture

MTJ-Based Nonvolatile Logic-in-Memory Architecture 2011 Spintronics Workshop on LSI @ Kyoto, Japan, June 13, 2011 MTJ-Based Nonvolatile Logic-in-Memory Architecture Takahiro Hanyu Center for Spintronics Integrated Systems, Tohoku University, JAPAN Laboratory

More information

AC-DIMM: Associative Computing with STT-MRAM

AC-DIMM: Associative Computing with STT-MRAM AC-DIMM: Associative Computing with STT-MRAM Qing Guo, Xiaochen Guo, Ravi Patel Engin Ipek, Eby G. Friedman University of Rochester Published In: ISCA-2013 Motivation Prevalent Trends in Modern Computing:

More information

Recent Advancements in Spin-Torque Switching for High-Density MRAM

Recent Advancements in Spin-Torque Switching for High-Density MRAM Recent Advancements in Spin-Torque Switching for High-Density MRAM Jon Slaughter Everspin Technologies 7th International Symposium on Advanced Gate Stack Technology, September 30, 2010 Everspin Technologies,

More information

Novel Nonvolatile Memory Hierarchies to Realize "Normally-Off Mobile Processors" ASP-DAC 2014

Novel Nonvolatile Memory Hierarchies to Realize Normally-Off Mobile Processors ASP-DAC 2014 Novel Nonvolatile Memory Hierarchies to Realize "Normally-Off Mobile Processors" ASP-DAC 2014 Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe Toshiba Corporation, R&D Center Advanced

More information

The Internet of Things and Batteries, Hackers and CPU Architects, oh, and NVM. Lucian Shifren ARM R&D San Jose CA

The Internet of Things and Batteries, Hackers and CPU Architects, oh, and NVM. Lucian Shifren ARM R&D San Jose CA The Internet of Things and Batteries, Hackers and CPU Architects, oh, and NVM Lucian Shifren ARM R&D San Jose CA 1 What is the Internet of Things? Buzzword Trend Convenient Categorization Industrial Consumer

More information

Phase Change Memory An Architecture and Systems Perspective

Phase Change Memory An Architecture and Systems Perspective Phase Change Memory An Architecture and Systems Perspective Benjamin C. Lee Stanford University bcclee@stanford.edu Fall 2010, Assistant Professor @ Duke University Benjamin C. Lee 1 Memory Scaling density,

More information

Memory technology and optimizations ( 2.3) Main Memory

Memory technology and optimizations ( 2.3) Main Memory Memory technology and optimizations ( 2.3) 47 Main Memory Performance of Main Memory: Latency: affects Cache Miss Penalty» Access Time: time between request and word arrival» Cycle Time: minimum time between

More information

Future computer Architectures: Computing in Memory

Future computer Architectures: Computing in Memory Future computer Architectures: Computing in Memory Said Hamdioui Delft University of Technology The Netherlands ASCI Spring School on Heterogeneous Computing Systems May 29 - June 1, 2017 1 Outline Motivation

More information

Area, Power, and Latency Considerations of STT-MRAM to Substitute for Main Memory

Area, Power, and Latency Considerations of STT-MRAM to Substitute for Main Memory Area, Power, and Latency Considerations of STT-MRAM to Substitute for Main Memory Youngbin Jin, Mustafa Shihab, and Myoungsoo Jung Computer Architecture and Memory Systems Laboratory Department of Electrical

More information

Persistent Memory Productization driven by AI & ML. Danny Sabour VP Marketing, Avalanche Technology

Persistent Memory Productization driven by AI & ML. Danny Sabour VP Marketing, Avalanche Technology Persistent Memory Productization driven by AI & ML Danny Sabour VP Marketing, Avalanche Technology Persistent Memory Usage from Cloud to Node CLOUD Compute Storage Deep Learning Training Big data processing

More information

MRAM, XPoint, ReRAM PM Fuel to Propel Tomorrow s Computing Advances

MRAM, XPoint, ReRAM PM Fuel to Propel Tomorrow s Computing Advances MRAM, XPoint, ReRAM PM Fuel to Propel Tomorrow s Computing Advances Jim Handy Objective Analysis Tom Coughlin Coughlin Associates The Market is at a Nexus PM 2 Emerging Memory Technologies MRAM: Magnetic

More information

Using Non-Volatile Memory for Computation-in-Memory

Using Non-Volatile Memory for Computation-in-Memory Using Non-Volatile Memory for Computation-in-Memory Wei -Ti Liu LucidPort Technology, Inc. www.lucidport.com Flash Memory Summit 2018 Santa Clara, CA 1 Using Non-Volatile Memory for Computation-in-Memory

More information

! Memory Overview. ! ROM Memories. ! RAM Memory " SRAM " DRAM. ! This is done because we can build. " large, slow memories OR

! Memory Overview. ! ROM Memories. ! RAM Memory  SRAM  DRAM. ! This is done because we can build.  large, slow memories OR ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 2: April 5, 26 Memory Overview, Memory Core Cells Lecture Outline! Memory Overview! ROM Memories! RAM Memory " SRAM " DRAM 2 Memory Overview

More information

Versatile RRAM Technology and Applications

Versatile RRAM Technology and Applications Versatile RRAM Technology and Applications Hagop Nazarian Co-Founder and VP of Engineering, Crossbar Inc. Santa Clara, CA 1 Agenda Overview of RRAM Technology RRAM for Embedded Memory Mass Storage Memory

More information

Cascaded Channel Model, Analysis, and Hybrid Decoding for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM)

Cascaded Channel Model, Analysis, and Hybrid Decoding for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM) 1/16 Cascaded Channel Model, Analysis, and Hybrid Decoding for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM) Kui Cai 1, K.A.S Immink 2, and Zhen Mei 1 Advanced Coding and Signal Processing

More information

Large and Fast: Exploiting Memory Hierarchy

Large and Fast: Exploiting Memory Hierarchy CSE 431: Introduction to Operating Systems Large and Fast: Exploiting Memory Hierarchy Gojko Babić 10/5/018 Memory Hierarchy A computer system contains a hierarchy of storage devices with different costs,

More information

Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative

Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative Emre Kültürsay *, Mahmut Kandemir *, Anand Sivasubramaniam *, and Onur Mutlu * Pennsylvania State University Carnegie Mellon University

More information

3D Xpoint Status and Forecast 2017

3D Xpoint Status and Forecast 2017 3D Xpoint Status and Forecast 2017 Mark Webb MKW 1 Ventures Consulting, LLC Memory Technologies Latency Density Cost HVM ready DRAM ***** *** *** ***** NAND * ***** ***** ***** MRAM ***** * * *** 3DXP

More information

CMP annual meeting, January 23 rd, 2014

CMP annual meeting, January 23 rd, 2014 J.P.Nozières, G.Prenat, B.Dieny and G.Di Pendina Spintec, UMR-8191, CEA-INAC/CNRS/UJF-Grenoble1/Grenoble-INP, Grenoble, France CMP annual meeting, January 23 rd, 2014 ReRAM V wr0 ~-0.9V V wr1 V ~0.9V@5ns

More information

Semiconductor Memory Classification. Today. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. CPU Memory Hierarchy.

Semiconductor Memory Classification. Today. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. CPU Memory Hierarchy. ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec : April 4, 7 Memory Overview, Memory Core Cells Today! Memory " Classification " ROM Memories " RAM Memory " Architecture " Memory core " SRAM

More information

Storage and Memory Infrastructure to Support 5G Applications. Tom Coughlin President, Coughlin Associates

Storage and Memory Infrastructure to Support 5G Applications. Tom Coughlin President, Coughlin Associates Storage and Memory Infrastructure to Support 5G Applications Tom Coughlin President, Coughlin Associates www.tomcoughlin.com Outline 5G and its Implementation Storage and Memory Technologies Emerging Non

More information

Lecture 18: Memory Systems. Spring 2018 Jason Tang

Lecture 18: Memory Systems. Spring 2018 Jason Tang Lecture 18: Memory Systems Spring 2018 Jason Tang 1 Topics Memory hierarchy Memory operations Cache basics 2 Computer Organization Computer Processor Memory Devices Control Datapath Input Output So far,

More information

Alternative Non-Volatile Memory Adoption Timeline

Alternative Non-Volatile Memory Adoption Timeline Alternative Non-Volatile Memory Adoption Timeline Mark Webb MKW Ventures, LLC Flash Memory Summit 2015 Santa Clara, CA 1 Technologies Many NVM technologies exist today. NOR: low density, low growth, incredibly

More information

Couture: Tailoring STT-MRAM for Persistent Main Memory. Mustafa M Shihab Jie Zhang Shuwen Gao Joseph Callenes-Sloan Myoungsoo Jung

Couture: Tailoring STT-MRAM for Persistent Main Memory. Mustafa M Shihab Jie Zhang Shuwen Gao Joseph Callenes-Sloan Myoungsoo Jung Couture: Tailoring STT-MRAM for Persistent Main Memory Mustafa M Shihab Jie Zhang Shuwen Gao Joseph Callenes-Sloan Myoungsoo Jung Executive Summary Motivation: DRAM plays an instrumental role in modern

More information

Intel s s Memory Strategy for the Wireless Phone

Intel s s Memory Strategy for the Wireless Phone Intel s s Memory Strategy for the Wireless Phone Stefan Lai VP and Co-Director, CTM Intel Corporation Nikkei Microdevices Memory Symposium January 26 th, 2005 Agenda Evolution of Memory Requirements Evolution

More information

Emerging NVM Memory Technologies

Emerging NVM Memory Technologies Emerging NVM Memory Technologies Yuan Xie Associate Professor The Pennsylvania State University Department of Computer Science & Engineering www.cse.psu.edu/~yuanxie yuanxie@cse.psu.edu Position Statement

More information

ReRAM Status and Forecast 2017

ReRAM Status and Forecast 2017 ReRAM Status and Forecast 2017 Mark Webb The Latency Spectrum and Gaps More Like Memory More Like Storage CPU/ SRAM DRAM Storage Class Memory GAP NAND SLC to TLC HDD TAPE 1ns 10ns 100ns 1us 10us 100us

More information

(Advanced) Computer Organization & Architechture. Prof. Dr. Hasan Hüseyin BALIK (5 th Week)

(Advanced) Computer Organization & Architechture. Prof. Dr. Hasan Hüseyin BALIK (5 th Week) + (Advanced) Computer Organization & Architechture Prof. Dr. Hasan Hüseyin BALIK (5 th Week) + Outline 2. The computer system 2.1 A Top-Level View of Computer Function and Interconnection 2.2 Cache Memory

More information

Memory Systems IRAM. Principle of IRAM

Memory Systems IRAM. Principle of IRAM Memory Systems 165 other devices of the module will be in the Standby state (which is the primary state of all RDRAM devices) or another state with low-power consumption. The RDRAM devices provide several

More information

EMERGING NON VOLATILE MEMORY

EMERGING NON VOLATILE MEMORY EMERGING NON VOLATILE MEMORY Innovative components for neuromorphic architecture Leti, technology research institute Contact: leti.contact@cea.fr Neuromorphic architecture Brain-inspired computing has

More information

ECE 341. Lecture # 16

ECE 341. Lecture # 16 ECE 341 Lecture # 16 Instructor: Zeshan Chishti zeshan@ece.pdx.edu November 24, 2014 Portland State University Lecture Topics The Memory System Basic Concepts Semiconductor RAM Memories Organization of

More information

NAND Flash Memory. Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University

NAND Flash Memory. Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University NAND Flash Memory Jinkyu Jeong (Jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong (jinkyu@skku.edu) Flash

More information

Memory memories memory

Memory memories memory Memory Organization Memory Hierarchy Memory is used for storing programs and data that are required to perform a specific task. For CPU to operate at its maximum speed, it required an uninterrupted and

More information

Computer Organization and Assembly Language (CS-506)

Computer Organization and Assembly Language (CS-506) Computer Organization and Assembly Language (CS-506) Muhammad Zeeshan Haider Ali Lecturer ISP. Multan ali.zeeshan04@gmail.com https://zeeshanaliatisp.wordpress.com/ Lecture 2 Memory Organization and Structure

More information

Register Transfer Level (RTL) Design

Register Transfer Level (RTL) Design CSE4: Components and Design Techniques for Digital Systems Register Transfer Level (RTL) Design Mohsen Imani Topics for today Another example of RTL design RTL circuit delays and clock HLSM array and Register

More information

I/O CANNOT BE IGNORED

I/O CANNOT BE IGNORED LECTURE 13 I/O I/O CANNOT BE IGNORED Assume a program requires 100 seconds, 90 seconds for main memory, 10 seconds for I/O. Assume main memory access improves by ~10% per year and I/O remains the same.

More information

COMPRESSION ARCHITECTURE FOR BIT-WRITE REDUCTION IN NON-VOLATILE MEMORY TECHNOLOGIES. David Dgien. Submitted to the Graduate Faculty of

COMPRESSION ARCHITECTURE FOR BIT-WRITE REDUCTION IN NON-VOLATILE MEMORY TECHNOLOGIES. David Dgien. Submitted to the Graduate Faculty of COMPRESSION ARCHITECTURE FOR BIT-WRITE REDUCTION IN NON-VOLATILE MEMORY TECHNOLOGIES by David Dgien B.S. in Computer Engineering, University of Pittsburgh, 2012 Submitted to the Graduate Faculty of the

More information

Contents. Memory System Overview Cache Memory. Internal Memory. Virtual Memory. Memory Hierarchy. Registers In CPU Internal or Main memory

Contents. Memory System Overview Cache Memory. Internal Memory. Virtual Memory. Memory Hierarchy. Registers In CPU Internal or Main memory Memory Hierarchy Contents Memory System Overview Cache Memory Internal Memory External Memory Virtual Memory Memory Hierarchy Registers In CPU Internal or Main memory Cache RAM External memory Backing

More information

Hybrid STT CMOS Designs for Reverse engineering Prevention

Hybrid STT CMOS Designs for Reverse engineering Prevention Hybrid STT CMOS Designs for Reverse engineering Prevention Theodore Winograd George Mason University Hassan Salmani* Howard University Hamid Mahmoodi San Francisco State University Kris Gaj George Mason

More information

Scalable High Performance Main Memory System Using PCM Technology

Scalable High Performance Main Memory System Using PCM Technology Scalable High Performance Main Memory System Using PCM Technology Moinuddin K. Qureshi Viji Srinivasan and Jude Rivers IBM T. J. Watson Research Center, Yorktown Heights, NY International Symposium on

More information

ECE 152 Introduction to Computer Architecture

ECE 152 Introduction to Computer Architecture Introduction to Computer Architecture Main Memory and Virtual Memory Copyright 2009 Daniel J. Sorin Duke University Slides are derived from work by Amir Roth (Penn) Spring 2009 1 Where We Are in This Course

More information

Improving Energy Efficiency of Write-asymmetric Memories by Log Style Write

Improving Energy Efficiency of Write-asymmetric Memories by Log Style Write Improving Energy Efficiency of Write-asymmetric Memories by Log Style Write Guangyu Sun 1, Yaojun Zhang 2, Yu Wang 3, Yiran Chen 2 1 Center for Energy-efficient Computing and Applications, Peking University

More information

The Engine. SRAM & DRAM Endurance and Speed with STT MRAM. Les Crudele / Andrew J. Walker PhD. Santa Clara, CA August

The Engine. SRAM & DRAM Endurance and Speed with STT MRAM. Les Crudele / Andrew J. Walker PhD. Santa Clara, CA August The Engine & DRAM Endurance and Speed with STT MRAM Les Crudele / Andrew J. Walker PhD August 2018 1 Contents The Leaking Creaking Pyramid STT-MRAM: A Compelling Replacement STT-MRAM: A Unique Endurance

More information

Organization. 5.1 Semiconductor Main Memory. William Stallings Computer Organization and Architecture 6th Edition

Organization. 5.1 Semiconductor Main Memory. William Stallings Computer Organization and Architecture 6th Edition William Stallings Computer Organization and Architecture 6th Edition Chapter 5 Internal Memory 5.1 Semiconductor Main Memory 5.2 Error Correction 5.3 Advanced DRAM Organization 5.1 Semiconductor Main Memory

More information

William Stallings Computer Organization and Architecture 6th Edition. Chapter 5 Internal Memory

William Stallings Computer Organization and Architecture 6th Edition. Chapter 5 Internal Memory William Stallings Computer Organization and Architecture 6th Edition Chapter 5 Internal Memory Semiconductor Memory Types Semiconductor Memory RAM Misnamed as all semiconductor memory is random access

More information

SOLVING MANUFACTURING CHALLENGES AND BRINGING SPIN TORQUE MRAM TO THE MAINSTREAM

SOLVING MANUFACTURING CHALLENGES AND BRINGING SPIN TORQUE MRAM TO THE MAINSTREAM SEMICON Taipei SOLVING MANUFACTURING CHALLENGES AND BRINGING SPIN TORQUE MRAM TO THE MAINSTREAM Joe O Hare, Marketing Director Sanjeev Aggarwal, Ph.D., VP Manufacturing & Process Everspin Company Highlights

More information

Phase Change Memory An Architecture and Systems Perspective

Phase Change Memory An Architecture and Systems Perspective Phase Change Memory An Architecture and Systems Perspective Benjamin Lee Electrical Engineering Stanford University Stanford EE382 2 December 2009 Benjamin Lee 1 :: PCM :: 2 Dec 09 Memory Scaling density,

More information

Lecture-14 (Memory Hierarchy) CS422-Spring

Lecture-14 (Memory Hierarchy) CS422-Spring Lecture-14 (Memory Hierarchy) CS422-Spring 2018 Biswa@CSE-IITK The Ideal World Instruction Supply Pipeline (Instruction execution) Data Supply - Zero-cycle latency - Infinite capacity - Zero cost - Perfect

More information

An Architecture-level Cache Simulation Framework Supporting Advanced PMA STT-MRAM

An Architecture-level Cache Simulation Framework Supporting Advanced PMA STT-MRAM An Architecture-level Cache Simulation Framework Supporting Advanced PMA STT-MRAM Bi Wu, Yuanqing Cheng,YingWang, Aida Todri-Sanial, Guangyu Sun, Lionel Torres and Weisheng Zhao School of Software Engineering

More information

The Evolving NAND Flash Business Model for SSD. Steffen Hellmold VP BD, SandForce

The Evolving NAND Flash Business Model for SSD. Steffen Hellmold VP BD, SandForce The Evolving NAND Flash Business Model for SSD Steffen Hellmold VP BD, SandForce Solid State Storage - Vision Solid State Storage in future Enterprise Compute Anything performance sensitive goes solid

More information

ECEN 449 Microprocessor System Design. Memories

ECEN 449 Microprocessor System Design. Memories ECEN 449 Microprocessor System Design Memories 1 Objectives of this Lecture Unit Learn about different types of memories SRAM/DRAM/CAM /C Flash 2 1 SRAM Static Random Access Memory 3 SRAM Static Random

More information

Annual Update on Flash Memory for Non-Technologists

Annual Update on Flash Memory for Non-Technologists Annual Update on Flash Memory for Non-Technologists Jay Kramer, Network Storage Advisors & George Crump, Storage Switzerland August 2017 1 Memory / Storage Hierarchy Flash Memory Summit 2017 2 NAND Flash

More information

Daniele Ielmini DEI - Politecnico di Milano, Milano, Italy Outline. Solid-state disk (SSD) Storage class memory (SCM)

Daniele Ielmini DEI - Politecnico di Milano, Milano, Italy Outline. Solid-state disk (SSD) Storage class memory (SCM) Beyond NVMs Daniele Ielmini DEI - Politecnico di Milano, Milano, Italy ielmini@elet.polimi.it Outline Storage applications Solid-state disk (SSD) Storage class memory (SCM) Logic applications: Crossbar

More information

SOLVING THE DRAM SCALING CHALLENGE: RETHINKING THE INTERFACE BETWEEN CIRCUITS, ARCHITECTURE, AND SYSTEMS

SOLVING THE DRAM SCALING CHALLENGE: RETHINKING THE INTERFACE BETWEEN CIRCUITS, ARCHITECTURE, AND SYSTEMS SOLVING THE DRAM SCALING CHALLENGE: RETHINKING THE INTERFACE BETWEEN CIRCUITS, ARCHITECTURE, AND SYSTEMS Samira Khan MEMORY IN TODAY S SYSTEM Processor DRAM Memory Storage DRAM is critical for performance

More information

Don t Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration

Don t Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration Don t Forget the : Automatic Block RAM Modelling, Optimization, and Architecture Exploration S. Yazdanshenas, K. Tatsumura *, and V. Betz University of Toronto, Canada * Toshiba Corporation, Japan : An

More information

CS 261 Fall Mike Lam, Professor. Memory

CS 261 Fall Mike Lam, Professor. Memory CS 261 Fall 2016 Mike Lam, Professor Memory Topics Memory hierarchy overview Storage technologies SRAM DRAM PROM / flash Disk storage Tape and network storage I/O architecture Storage trends Latency comparisons

More information

Flash Memory Overview: Technology & Market Trends. Allen Yu Phison Electronics Corp.

Flash Memory Overview: Technology & Market Trends. Allen Yu Phison Electronics Corp. Flash Memory Overview: Technology & Market Trends Allen Yu Phison Electronics Corp. 25,000 20,000 15,000 The NAND Market 40% CAGR 10,000 5,000 ($Million) - 2001 2002 2003 2004 2005 2006 2007 2008 2009

More information

MEMORY BHARAT SCHOOL OF BANKING- VELLORE

MEMORY BHARAT SCHOOL OF BANKING- VELLORE A memory is just like a human brain. It is used to store data and instructions. Computer memory is the storage space in computer where data is to be processed and instructions required for processing are

More information

Fault Injection Attacks on Emerging Non-Volatile Memories

Fault Injection Attacks on Emerging Non-Volatile Memories Lab of Green and Secure Integrated Circuit Systems (LOGICS) Fault Injection Attacks on Emerging Non-Volatile Memories Mohammad Nasim Imtiaz Khan and Swaroop Ghosh School of Electrical Engineering and Computer

More information

Markets for 3D-Xpoint Applications, Performance and Revenue

Markets for 3D-Xpoint Applications, Performance and Revenue Markets for 3D-Xpoint Applications, Performance and Revenue Mark Webb MKW Ventures Consulting, LLC Santa Clara, CA 1 Contents Persistent Memory Options What is 3D Xpoint The hype-reality challenge of xpoint

More information

Computing with Spintronics: Circuits and architectures

Computing with Spintronics: Circuits and architectures Purdue University Purdue e-pubs Open Access Dissertations Theses and Dissertations Fall 2014 Computing with Spintronics: Circuits and architectures Rangharajan Venkatesan Purdue University Follow this

More information

Adding CEA-LETI Non Volatile Memories for new design exploration

Adding CEA-LETI Non Volatile Memories for new design exploration Adding CEA-LETI Non Volatile Memories for new design exploration Etienne NOWAK CEA-Leti Head of the Advanced Memory Device Laboratory etienne.nowak@cea.fr NON VOLATILE MEMORY (NVM) MARKET TRENDS Low/No

More information

Internal Memory. Computer Architecture. Outline. Memory Hierarchy. Semiconductor Memory Types. Copyright 2000 N. AYDIN. All rights reserved.

Internal Memory. Computer Architecture. Outline. Memory Hierarchy. Semiconductor Memory Types. Copyright 2000 N. AYDIN. All rights reserved. Computer Architecture Prof. Dr. Nizamettin AYDIN naydin@yildiz.edu.tr nizamettinaydin@gmail.com Internal Memory http://www.yildiz.edu.tr/~naydin 1 2 Outline Semiconductor main memory Random Access Memory

More information

EMDBAM: A Low-Power Dual Bit Associative Memory with Match Error and Mask Control

EMDBAM: A Low-Power Dual Bit Associative Memory with Match Error and Mask Control Abstract: EMDBAM: A Low-Power Dual Bit Associative Memory with Match Error and Mask Control A ternary content addressable memory (TCAM) speeds up the search process in the memory by searching through prestored

More information

A Low-Power Hybrid Magnetic Cache Architecture Exploiting Narrow-Width Values

A Low-Power Hybrid Magnetic Cache Architecture Exploiting Narrow-Width Values A Low-Power Hybrid Magnetic Cache Architecture Exploiting Narrow-Width Values Mohsen Imani, Abbas Rahimi, Yeseong Kim, Tajana Rosing Computer Science and Engineering, UC San Diego, La Jolla, CA 92093,

More information

Embedded Systems: Hardware Components (part I) Todor Stefanov

Embedded Systems: Hardware Components (part I) Todor Stefanov Embedded Systems: Hardware Components (part I) Todor Stefanov Leiden Embedded Research Center Leiden Institute of Advanced Computer Science Leiden University, The Netherlands Outline Generic Embedded System

More information

ECE 486/586. Computer Architecture. Lecture # 2

ECE 486/586. Computer Architecture. Lecture # 2 ECE 486/586 Computer Architecture Lecture # 2 Spring 2015 Portland State University Recap of Last Lecture Old view of computer architecture: Instruction Set Architecture (ISA) design Real computer architecture:

More information

ECEN 449 Microprocessor System Design. Memories. Texas A&M University

ECEN 449 Microprocessor System Design. Memories. Texas A&M University ECEN 449 Microprocessor System Design Memories 1 Objectives of this Lecture Unit Learn about different types of memories SRAM/DRAM/CAM Flash 2 SRAM Static Random Access Memory 3 SRAM Static Random Access

More information

Scalable Many-Core Memory Systems Lecture 3, Topic 2: Emerging Technologies and Hybrid Memories

Scalable Many-Core Memory Systems Lecture 3, Topic 2: Emerging Technologies and Hybrid Memories Scalable Many-Core Memory Systems Lecture 3, Topic 2: Emerging Technologies and Hybrid Memories Prof. Onur Mutlu http://www.ece.cmu.edu/~omutlu onur@cmu.edu HiPEAC ACACES Summer School 2013 July 17, 2013

More information

Lecture: Memory, Multiprocessors. Topics: wrap-up of memory systems, intro to multiprocessors and multi-threaded programming models

Lecture: Memory, Multiprocessors. Topics: wrap-up of memory systems, intro to multiprocessors and multi-threaded programming models Lecture: Memory, Multiprocessors Topics: wrap-up of memory systems, intro to multiprocessors and multi-threaded programming models 1 Refresh Every DRAM cell must be refreshed within a 64 ms window A row

More information

A REVIEW ON INTEGRATION OF SPIN RAM IN FPGA CIRCUITS

A REVIEW ON INTEGRATION OF SPIN RAM IN FPGA CIRCUITS A REVIEW ON INTEGRATION OF SPIN RAM IN FPGA CIRCUITS Parth Dhall, Ruchi Varshney Department of E&C Engineering, Moradabad Institute of Technology, Moradabad, Uttar Pradesh, India ABSTRACT In this paper,

More information

emram: From Technology to Applications David Eggleston VP Embedded Memory

emram: From Technology to Applications David Eggleston VP Embedded Memory emram: From Technology to Applications David Eggleston VP Embedded Memory 10,000 foot view What are we trying to achieve? 2 Memory is Know Remembering. Think Events 3 Memory is Code Persistence. Data State

More information

Storage. CS 3410 Computer System Organization & Programming

Storage. CS 3410 Computer System Organization & Programming Storage CS 3410 Computer System Organization & Programming These slides are the product of many rounds of teaching CS 3410 by Deniz Altinbuke, Kevin Walsh, and Professors Weatherspoon, Bala, Bracy, and

More information

Maximize energy efficiency in a normally-off system using NVRAM. Stéphane Gros Yeter Akgul

Maximize energy efficiency in a normally-off system using NVRAM. Stéphane Gros Yeter Akgul Maximize energy efficiency in a normally-off system using NVRAM Stéphane Gros Yeter Akgul Summary THE COMPANY THE CONTEXT THE TECHNOLOGY THE SYSTEM THE CO-DEVELOPMENT CONCLUSION May 31, 2017 2 Summary

More information

Analysts Weigh In On Persistent Memory

Analysts Weigh In On Persistent Memory Analysts Weigh In On Persistent Memory Moderator: Michael Oros, Executive Director, SNIA Today s Presenters Jim Handy and Tom Coughlin on How Persistent Memory Will Succeed Randy Kerns with An Analyst

More information

COSC 243. Memory and Storage Systems. Lecture 10 Memory and Storage Systems. COSC 243 (Computer Architecture)

COSC 243. Memory and Storage Systems. Lecture 10 Memory and Storage Systems. COSC 243 (Computer Architecture) COSC 243 1 Overview This Lecture Source: Chapters 4, 5, and 6 (10 th edition) Next Lecture Control Unit and Microprogramming 2 Electromagnetic Induction Move a magnet through a coil to induce a current

More information

Lecture 17 Introduction to Memory Hierarchies" Why it s important " Fundamental lesson(s)" Suggested reading:" (HP Chapter

Lecture 17 Introduction to Memory Hierarchies Why it s important  Fundamental lesson(s) Suggested reading: (HP Chapter Processor components" Multicore processors and programming" Processor comparison" vs." Lecture 17 Introduction to Memory Hierarchies" CSE 30321" Suggested reading:" (HP Chapter 5.1-5.2)" Writing more "

More information

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1> Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building

More information

Emerging IC Packaging Platforms for ICT Systems - MEPTEC, IMAPS and SEMI Bay Area Luncheon Presentation

Emerging IC Packaging Platforms for ICT Systems - MEPTEC, IMAPS and SEMI Bay Area Luncheon Presentation Emerging IC Packaging Platforms for ICT Systems - MEPTEC, IMAPS and SEMI Bay Area Luncheon Presentation Dr. Li Li Distinguished Engineer June 28, 2016 Outline Evolution of Internet The Promise of Internet

More information

CSEE 3827: Fundamentals of Computer Systems. Storage

CSEE 3827: Fundamentals of Computer Systems. Storage CSEE 387: Fundamentals of Computer Systems Storage The big picture General purpose processor (e.g., Power PC, Pentium, MIPS) Internet router (intrusion detection, pacet routing, etc.) WIreless transceiver

More information

Developing a Prototyping Board for Emerging Memory

Developing a Prototyping Board for Emerging Memory Developing a Prototyping Board for Emerging Memory 2013. 10. 25 Sungjoo Yoo Embedded System Architecture Lab. POSTECH Introduction scaling problem [ITRS, 2012] Year 2012 2013 2014 2015 2016 2017 2018 2019

More information

Semiconductor Memory II Future Memory Trend

Semiconductor Memory II Future Memory Trend Semiconductor Memory II Future Memory Trend Seong-Ook Jung 2010. 4. 2. sjung@yonsei.ac.kr VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering Contents 1. Future memory trend

More information

Don t Forget the Memory. Dean Klein, VP Memory System Development Micron Technology, Inc.

Don t Forget the Memory. Dean Klein, VP Memory System Development Micron Technology, Inc. Don t Forget the Memory Dean Klein, VP Memory System Development Micron Technology, Inc. Memory is Everywhere 2 One size DOES NOT fit all 3 Question: How many different memories does your computer use?

More information

Embedded Systems Design: A Unified Hardware/Software Introduction. Outline. Chapter 5 Memory. Introduction. Memory: basic concepts

Embedded Systems Design: A Unified Hardware/Software Introduction. Outline. Chapter 5 Memory. Introduction. Memory: basic concepts Hardware/Software Introduction Chapter 5 Memory Outline Memory Write Ability and Storage Permanence Common Memory Types Composing Memory Memory Hierarchy and Cache Advanced RAM 1 2 Introduction Memory:

More information

Embedded Systems Design: A Unified Hardware/Software Introduction. Chapter 5 Memory. Outline. Introduction

Embedded Systems Design: A Unified Hardware/Software Introduction. Chapter 5 Memory. Outline. Introduction Hardware/Software Introduction Chapter 5 Memory 1 Outline Memory Write Ability and Storage Permanence Common Memory Types Composing Memory Memory Hierarchy and Cache Advanced RAM 2 Introduction Embedded

More information