Simulation Analysis of Permutation Passibility behavior of Multi-stage Interconnection Networks

Transcription

1 Simulation Analysis of Permutation Passibility behavior of Multi-stage Interconnection Networks A Thesis Report Submitted in the partial fulfillment of the requirements for the award of the degree of ME in Software Engineering Submitted by Yukti Jindal M.E. (Software Engineering) Under the supervision of: Mrs. Rinkle Aggarwal Lecturer Computer Science and Engineering Department Thapar Institute of Engineering and Technology Computer Science and Engineering Department Thapar Institute of Engineering and Technology Deemed University Patiala 1

2 DECLARATION I declare that the work presented in this thesis is, to the best of my knowledge, original and my own work, except as acknowledged in the text, and that it has not been submitted, either in whole or part, for a degree at this, or any other, university. Yukti Jindal Regd. No CERTIFICATE

3 This is to certify that the thesis work entitled, Simulation Analysis of Permutation Passibility behavior of Multi-stage Interconnection Networks submitted by Yukti Jindal, in the partial fulfillment of the requirement for the award of degree of Master of Engineering in Software Engineering at Thapar Institute of Engineering & Technology (Deemed University), Patiala, is a record of candidate s own work carried out by her under my supervision and guidance. Mrs. Rinkle Aggarwal Lecturer, CSED TIET, Patiala Ms. Seema Bawa Head, CSED TIET, Patiala Dr. D.S. Bawa Dean, Academic Affairs TIET, Patiala The M.E. (Thesis) viva-voce examination of Yukti Jindal, Regd. No. 8011, M.E. (Software Engineering), Thapar Institute of Engineering & Technology (Deemed University), Patiala has been held on Supervisor External Examiner ACKNOWLEDGEMENTS I wish to express my sincere gratitude Mrs. Rinkle Aggarwal, Lecturer, Computer Science and Engg. Department, for providing invaluable guidance, suggestions and

4 sympathetic attitude, which inspired me to submit this thesis report on time. I also wish to express my gratitude to Mr. Rajesh Bhatia, Lecturer, Computer Science and Engg. Department, for her valuable advises and suggestions. I am also thankful to Ms. Seema Bawa, Head, Computer Science and Engg. Department, for her kind help and cooperation. I would also like to thank all the staff members of Computer Science and Engineering Department for providing me all the facilities required for the completion of this work. I would like to extend my special thanks to Mr. Himanshu Aggarwal, Lecturer, Computer Science and Engg. Department in Punjabi Univ for providing me invaluable support. I am deeply indebted to my parents,sister and brother for the inspiration and ever encouraging moral support, which enabled me to pursue my studies. Yukti Jindal CONTENTS Declaration (ii) Certificate.....(iii) Acknowledgment.....(iv) Page no.

5 Contents....(v) List of Figures.. (ix) Abstract.....(x) Chapter 1.1 Introduction Introduction to parallel systems Classification of parallel systems Multicomputer Multiprocessors Tightly coupled systems Loosely coupled systems Network Concepts Problem definition Organization of thesis Chapter Interconnection Networks Introduction

6 . Interconnection Networks Design dimensions Switching methodology Operating Modes Control strategy Network topology Chapter Multistage Interconnection Networks Introduction 1. Classification of Multistage interconnection networks Classification according to Path Multipath networks Unique path Classification according to Switches Regular networks Irregular networks Classification according to Control Flip controlled networks Distributed control networks Other classification Blocking networks Non blocking networks Type of connections in MINs Routing in MINs Routing tags

7 .. Type of routing in MINs Non adaptive routing Adaptive routing Dynamic Routing Fault tolerance.... Chapter A survey of MINs Introduction.... Unique- path MINs Crossbar Network Omega Network Generalized Cube Network Shuffle Exchange network Multi-path Static Regular MINs Benes Network Multipath Regular Dynamic MINs Augmented Shuffle Exchange MINs Irregular MINs Four-Tree Network (FT)..8.. Modified Four tree network..0 Chapter Permutation Passabiltiy in MINs...1 Introduction..

8 . Simulation Analysis.... Simulation of Permutation Passability in Regular Networks..1 ASEN network... FT Network.... Modified FT Network..0 Chapter Algorithm for Calculating the Permutation Passabiltiy Behavior of MINs..1 Introduction Algorithm for ASEN Network Virtual Inputs..... Graph Matrix... Outline of input, Computation and Output Parameters..... Illustrated Example of an Algorithm Algorithm for the ASEN network.... Algorithm for FT Network..1 Virtual Inputs Graph Matrix.8.. Outline of Input, Computation and Output Parameters Illustrated Example of an Algorithm Algorithm for the FT network..... Algorithm for Modified FT Network Virtual Inputs Graph Matrix. 8.. Outline of input, Computation and Output Parameters Illustrated Example of an Algorithm Algorithm for the Modified FT network..8. Pseudocode..89 8

9 ..1 Pseudocode for ASEN Network...89 Chapter Conclusion and Further Scope Conclusions Further Scope.9 References. 9 9

10 LIST OF FIGURES Figure no. Figure name Page no..1. Fully connected network 10. Mesh (a) -D mesh network with width 1 (b) -D mesh network with width (c) -D mesh network. Simple Ring network 1. (b) Chordal Ring network 1. Hypercubes of dimension zero through four 1.1 A multistage interconnection network 1. Communication in a bi-directional MIN. The communication indicated at 18.1 Conceptual view of a single stage interconnection network. Classification of MINs. Crossbar Network 9. Omega Network 0. Generalized Cube Network 1. A perfect shuffle. A Inverse shuffle.8. Benes Network.9 ASEN 10

11 .10. FT Modified FT 1 ABSTRACT There are many different ways to organize computational structures to exploit parallelism. Many research efforts around the world are being conducted with the purpose of determining that hardware and software organizations that are best suited for general purpose parallel processing. The communication subsystems linking processors/memory modules and input/output controllers in a parallel processing system is one of its most important architecture features and has a profound impact on system capabilities, performance, size and cost. An interconnection network of the processors provides the desired connectivity and performance at minimum cost is required for communication in parallel processing systems with a large number of components. Multistage interconnection networks play an important role in the parallel computing systems. In multistage interconnection networks the fixed inter stage connections between adjacent stages exist with a number of switches at each stage that are dynamically set to establish the desired connection to route the requests from the inputs to outputs. The distribution of switches as well as their complexity is very important in designing multistage interconnection networks. The important features in the study of multistage interconnection networks are estimation of complexity, fault tolerant, communication efficiency, performance and 11

12 cost. In this thesis, a survey of various regular and irregular multistage interconnection networks is made. A new algorithm has been developed for finding the permutation passiability behavior of some regular as well as irregular networks. The permutation passibility behavior of existing regular and irregular networks is analyzed and also the simulation of permutation possibility behavior of some regular as well as irregular networks is defined. 1

13 CHAPTER 1 Introduction 1.1 Introduction to parallel systems High performance Computing Systems can be designed using parallel or distributed processing. There is considerable research in these areas due to following reasons: œ Technological development in the area of VLSI chips. œ Significant software parallelism is inherent in many scientific and engineering applications. A parallel computer is a collection of processing elements that cooperate to solve large problems fast. A parallel system means a set of different processors or computers interconnected together to improve performance. Use of more than one processing units at a time to enhance the overall output is called multiprocessing or multicomputing. The performance of a computer depends directly on the time required to perform a basic operation and the number of these basic operations that can be performed concurrently. High performance computing systems can be designed using parallel processing. The principle target in designing any parallel system is to reduce the communication overheads between both, the processors as well as the memory. Following are the desirable characteristics for the communication between processors and memory units: œ High speed œ High reliability œ On-line reparability œ Good performance even under faults œ Low cost œ Simple routing control œ Full access capability 1

14 However, multiple processor systems have a number of potential disadvantages, probably the most important being the very real problem of using the processing power in an efficient manner. This involves a number of factors such as, the ability to decompose a problem into an optimum number of modules, their size, and to define them in such a way that communication between processors may be carried out with the absolute minimum wait time and minimum delay time across the communication network. This communication network is a link between different processors as well as memory modules. 1. Classification of parallel systems Generally parallel systems[1] are of two categories, multicomputers and multiprocessors 1..1 Multicomputer A multicomputer comprises a number of computers, or nodes, linked by an interconnection network. Each computer executes its own program. This program may access local memory or may send and receive messages over the network i.e. message passing. Messages are used to communicate with other computers or, equivalently, to read and write remote memories. In the idealized network, the cost of messages passing between two nodes is independent of both, node location and other network traffic, but does depend on message length. Therefore, multicomputers means different computers, not sharing memory, connected by some communication link, with ring, linear bus, linear star, linear bus and tree topologies, used generally for those applications which require less inter-processor interaction because the interaction among the processors ids through messages passing between source and destination processors or computers. Store and forward techniques are to pass on the message from a source to a destination. Thus, there are a lot of communication overhead involved. 1

15 1.. Multiprocessors In a computer system it is common to connect multiple components, such as processors and memory. Except for the memory with embedded processors (called PIM), processors do not have memory does not include a processor in it. Multiprocessors are a common architecture today, so there is also the need to connect more than one processor with more than one-memory modules in an efficient manner. Multiprocessor[] computer architectures consisting of interconnected, multiple processors, are basically of two types Tightly coupled systems: In these systems, all the processors share primary memory and any communication usually take place through their shared global memory. The access time from any of the processors to memory is the same. In addition to the primary memory each processor has its own local memory Loosely coupled systems: In these systems, the processors do not share memory but each processor has its own memory. In these systems, all the communication between processors is done by passing messages across the network those interconnect processors. If a processor wants to access data in another processor s memory, it must send message through the communication subsystem, requesting the other processor to send these data. Partitioning and allocation of program and data into segment play crucial role in overall performance of an application in case of loosely coupled systems. Usually, tightly coupled systems are referred to as parallel processing systems and loosely coupled systems are referred to as distributed computing systems or simply distributed systems. 1

16 1. Network Concepts œ Network Topology : The lay-out of the network. The common topologies are Static (point-to-point networks) Dynamic (indirect networks) œ Node Neighborhood : Two nodes are neighbors if there is a link connecting them. œ Node degree : Number of channels connected to one node œ Diameter of network : Maximum shortest path between two nodes œ Network redundancy (fault tolerance) : Amount of alternative paths between two nodes œ Network scalability : Measure for expandability of the network œ Node symmetry : A node symmetric network has no distinguished node, that is, the view of the rest of the network is the same from any node. Rings, fully connected networks, and hypercubes are all node symmetric. Trees and stars are not. œ Network functionality : Measure for support of routing, fault tolerance, synchronization, message combining etc. œ Network throughput : Amount of transferred data/unit time œ Network latency : Worst case delay for transfer of a unit (empty) message through the network. 1. Problem definition Multistage interconnection networks play an important role in the parallel computing systems. A Multistage interconnection networks consist of more than one stages of interconnection elements and links. Reliability and efficiency in terms of speed of operations and the costs are major considerations in the design of multistage interconnection networks. A lot of work has already been done in the design and analysis of regular and irregular networks. Since irregular networks, in general, are less costly and multipath in nature as compared to regular multistage interconnection networks. So 1

17 analysis of irregular multistage interconnection networks is important.a study of different multistage interconnection networks is made here. Permutation possibility is an important parameter to study the behavior of any multistage interconnection networks. Permutation passibility means how many input requests are simultaneously able to pass through a given network and reach successfully at the intended destination. Some of the requests will pass through the most favorable path, others have to be routed through an alternative paths are available or paths are busy in serving some other requests. In this thesis, permutation passibility behavior of existing regular and irregular networks is analyzed and also the simulation of permutation possibility behavior of some regular as well as irregular networks is defined. 1. Organization of thesis Chapter covers interconnection networks. The details of multistage interconnection networks are given in Chapter. A survey of existing regular and irregular multistage interconnection networks is covered in Chapter. Chapter deals with permutation passibilty of irregular networks and Chapter covers the algorithm for calculating the permutation passibiltiy behavior of MINs. The last Chapter is regarding the Conclusion and future scope of the work. 1

18 CHAPTER Interconnection Networks.1 Introduction There is one way for processors to communicate data is to use a shared memory and shared variables. However this is unrealistic for large numbers of processors. A more realistic assumption is that each processor has its own private memory and data communication takes place-using message passing via an Interconnection networks.. Interconnection Networks Interconnection networks[] make a major factor to differentiate modern multiprocessor architectures. They can be categorized according to a number of criteria such as topology, routing strategy and switching technique. Interconnection network is a complex connection of switches and links permitting processors in a multiprocessor system to communicate among themselves or with memory modules. It is the path, the data must travel in order to access memory in a shred memory computer or to communicate with another processor in distributed memory environment. The performance criteria for interconnection networks is: œ Fast communication œ Low cost œ Reliability during failures œ Efficiency œ Bandwidth 18

19 However, there is no network that would optimize all the performance criteria. But there are several different configurations, which provide trade-offs in terms of cost and efficiency.. Design dimensions The interconnection network plays a central role in determining the overall performance of a multicomputer system. If the network cannot provide adequate performance, for a particular application, nodes will frequently be forced to wait for data to arrive. The key design dimensions for interconnection networks are switching methodology, operational mode, control strategy and network topology, The space of interconnection networks can be represented by Cartesian product of all these dimensions i.e. operational mode, control strategy, switching methodology and network topology. The choice of a particular interconnection network depends upon the application demands, technology supports and cost effectiveness...1 Switching methodology Two major switching methodologies are circuiting switching and packet switching. In circuit switching a physical path is actually established between a source and a destination. This path exists as long as the data transmission of data. In packet switching, data is broken into packets and routed through the interconnection network without establishing a physical connection path. These packets are transmitted from source to the destination in store and forward manner, which introduce delay at each of the switching point. This delay depends on the traffic in the network along its path to the destination. Packet switching is more efficient for many short data messages. Combining the capabilities of both circuit switching and packet switching, the third type of switching methodology can be called integrated switching. 19

20 .. Operating Modes Operating modes can be either synchronous or asynchronous or a combination of the two. Synchronous communication is needed for either a data manipulating function or for a data instruction broadcast. Synchronous control techniques are characterized by a global clock, which broadcast clock signals to all devices in a system so that the entire system operates in a lock-step fashion. Asynchronous communication is needed for multi processing in which connection request is issued dynamically. Asynchronous techniques do not utilize a single global clock, but rather distribute the control function throughout the system, often utilizing many individual clocks for timing. Control and coordination of the various parts of the system are accomplished via some form of communication. Thus the interconnection network can operate synchronously-off of a global clock or it may have distributed control down to the level of the individual switches. The advantage of a single global clock for control is expandability and flexibility... Control strategy A typical interconnection network consists of a no. of switching elements and interconnecting links. Interconnection functions are realized by properly setting control of switching elements. The control setting function, for interconnection networks, can be managed by centralized controller or by individual switching element. The control strategy in the first case is centralized control and in the second case it is a distributed control strategy. 0

21 .. Network topology A network can be represented by a graph in which nodes indicate switches and edges represent communication link. Interconnection networks are built up of switching elements topology is the pattern in which the individual switches are connected to other elements, like processors, memories and other switches. Direct topologies connect each switch directly to a node, while in indirect topologies at least some of switches connect to other. The topologies can be categorized into two groups, static and dynamic. In static topology, links between two processors are passive and dedicated buses cannot be reconfigured for direct connection to other processors. Static interconnection networks are mainly used in message-passing architectures Some of the more important networks include œ Fully connected or all-to all œ Mesh œ Rings œ Hypercube œ Shuffle Exchange 1

22 œ Fully connected or all-to-all This is the most powerful interconnection network (topology): each node is directly connected to all other nodes. Fig..1.Fully connected network Each node has N-1 connections (N-1 nearest neighbors) giving a total of N (N-1) / connections for the network. Even though this is the best network to have the high number of connections per node mean this network can only be implemented for small values of N. Therefore some form of limited interconnection network must be used.

23 œ Mesh (Torus) In a mesh network, the nodes are arranged in a k dimensional lattice of width w, giving a total of w k nodes. Fig...(a) -D mesh network with width Fig. (b) -D mesh network with width

24 Fig.. (c) -D mesh network Communication is allowed only between neighboring nodes. All interior nodes are connected to k other nodes. œ Ring Fig.(a) Simple Ring network A simple ring is just a linear array with the end nodes linked.

25 It is equivalent to a 1D mesh with wraparound connections. A chordal ring is a simple ring with cross or chordal links between nodes on opposite sides. Fig.(b) Chordal Ring network œ Hypercube Connection ( Binary n-cube ) Hypercube networks consist of N = ^k nodes arranged in a k dimensional hypercube. The nodes are numbered 0, 1,...^k -1 and two nodes are connected if their binary labels differ by exactly one bit.

26 Fig. Hypercubes of dimension zero through four

27 K dimensional hypercube is formed by combining two k-1 dimensional hypercubes and connecting corresponding nodes i.e. hypercubes are recursive. each node is connected to k other nodes i.e. each is of degree k. The departmental NCUBE is based on this topology i.e. a dimensional hypercube ( nodes). K dimensional hypercube is formed by combining two k-1 dimensional hypercubes and connecting corresponding nodes i.e. hypercubes are recursive. Each node is connected to k other nodes i.e. each is of degree k. The departmental NCUBE is based on this topology i.e. a dimensional hypercube ( nodes).

28 CHAPTER Multistage Interconnection Networks.1 Introduction Multistage Interconnection networks (MINs) consist of more than one stages of small interconnection elements called switching elements and links interconnecting them. Multistage networks are described by three characteristic features, the switching elements, and network topology and control structures. A multistage interconnection network is actually a compromise between crossbar and shared bus networks. Multistage interconnection networks: œ Attempt to reduce cost œ Attempt to decrease diameter, diameter is the longest path any two nodes In a multistage interconnection network[], as in a crossbar, switching elements are distinct from processors. However, fewer than O(P ) switches are used to connect P processors.instead, messages pass through a series of switches stages. Figure.1. illustrates two MINs, which are representatives of a general class of networks characterized by parameters dimension n and radix k. Shaded circles represent processors and unshaded circles represent crossbar switches.the network on the left has k= and n=. On the right, k= and n=.the network can be constructed from unidirectional switches and links. In which case it is folded so that the processors on the left and right are the same. Alternatively, it can be constructed from bi-directional switches and links, in which case processors on the left and right are distinct. 8

29 Fig.1 A multistage interconnection network These networks are sometimes referred to as radix k, dimension n butterflies, or k-ay n- flies. Either n stages of k (n-1)k*k unidirectional crossbar switches connect p=k n processors or n stages of k (n-1)k*k bi-directional crossbar switches connect p=k n processors. In the latter case, each link comprises two channels that carry data in opposite directions, and each crossbar switch can route data arriving on any of k inputs to any of k outputs. Each stage of these networks connects p inputs with p outputs, although not every input is directly connected to every output in each stage. In a unidirectional MIN, all messages must traverse the same number of wires, and so the cost of sending a message is independent of processor location. In effect, all processors are equidistant. In a bi-directional MIN, the number of wires traversed depends to some extent on processor location, although to a lesser extent than in a mesh or hypercube. 9

30 (a) (b) Fig.. Communication in a bi-directional MIN. The communication indicated at (a) involves processors connected to the same crossbar; it takes just two hops and passes through a single switch. The communication at (b) takes three hops and passes through two switches. 0

31 The fact that messages destined for different destinations may need to pass over the same wire means that MINs are not immune to competition for bandwidth. Nevertheless, a MIN connecting P processors typically provides P wires at each stage, so in principle we should be able to organize communications so that little competition occurs. Switching elements The switching elements[11] may be viewed as a very small network. These switches are the devices having multiple input and outputs.the number of inputs/outputs and the input-to-output connections supported within a switch vary among the various designs. A two-function switch can assume either the straight or the exchange states i.e. straight, exchange, upper broadcast and lower broadcast. Switching Element Straight Exchange Lower Broadcast Upper broadcast 1

32 . Classification of Multistage interconnection networks Multistage interconnection networks can be classified according to different categories. The main classification categories are path, switches and control...1 Classification according to Path..1.1 Unique path networks: These networks provide unique path between every source and destination. The failure of any switching elements along the path disconnects some source-destination pairs. So adversely affecting the capabilities of the existing network. These are not reliable for a large multiprocessor system, as they cannot tolerate even a single fault. In case of multiple requests, a source destination connection any be blocked by a previously established connection. Thereby providing a poor performance...1. Multipath networks: These provide more than one paths between source and destination.in case, there is a failure of one switching element in the path, the request is routed through some other alternative path. Unique path multistage interconnection networks can be made multipath by adding redundancy in the form of extra switching elements, links, stages, sub networks, by increasing the size of switching elements or using multipath networks. Multipath multistage interconnection networks[8] can be either static or dynamic. For static networks, if a fault is encountered, then data has to backtrack, to the source or some fixed point to select an alternative path in the network. The implementation of backtracking is expensive in terms of the hardware. In dynamic networks, if a fault is encountered in a particular stage, a switching element in proceeding stage will re-route data through an alternative available path.

33 .. Classification according to Switches...1 Regular networks: Regular multistage interconnection networks have got an equal number of switching elements per stage; as a result they may impose equal time delay to all requests passing through them.... Irregular networks: Irregular multistage interconnection networks have unequal number of switching elements per stage and thus they are inherently multipaths in nature. For a given source-destination pair, there are different path lengths available... Classification according to Control...1 Flip controlled networks: Flip controlled multistage interconnection networks have a common control signal for switching in various switching elements at a given stage. This network is less complicated due to lesser number of control signals but has lesser bandwidth.... Distributed control networks: Distributed control multistage interconnection networks have a separate signal for every switching element. These have higher bandwidth due to selection of source destination pair at a given time and are quite complex... Other classification...1 Blocking networks: In blocking network, simultaneous connections of more than one terminal pair may result in conflict in use of network communication links. For example Omega networks.... Non blocking networks: A network is called non blocking if it is possible to route from any source to any destination, in presence of other established sourcedestination routes, provided no two sources have same destination. In other words, a

34 network is called rearrangeble if it can perform all possible connections between inputs and outputs by rearranging its existing connections so that a connection path for a new input output pair can always be established. For example Benes network.. Type of connections in MINs There are four types of connections[9], which are commonly used, in multistage interconnection networks. These are: œ One to one connections: A one to one connection passes information from a source to a destination. The exact route, taken by the information, is determined by path itself. œ Multipath connection: Multipath means many one to one connections are active simultaneously. œ Permutation connection: A set of one to one connections such that no two connections have the same sources and destinations. œ Broadcast connection: Information flow from source to various destinations either some or all. Thus a number of destinations simultaneously receive the information.. Routing in MINs No decision regarding the routing in a network is a perfect one. To acquire nearly complete knowledge for routing would require so many overheads that traffic throughout would be simultaneously reduced. For example, if there is minimal traffic, the network path with minimum number of links will normally be the best. If a node or switching elements fails, then the path with minimum number of links, which bypass the failures, will be the best. As traffic builds up, however this simple routing strategy can give poor results at times because the shortest path may happen to be congested. So the network as a whole should employ a routing strategy that would by pass areas of congestion.

35 There are several objectives of routing strategy: œ Minimize the transmit times œ Minimize the costs œ Maximize the network through put capability. To minimize the transmit times under conditions changing load, many control signals or overheads would be sent so that network throughput would be reduced. On the other hand, maximizing the throughput could be done at the expense of packet transmit times...1 Routing tags Routing tag is a way of describing the path though the network. For multistage interconnection networks, these tags are generally expressed as a multi-digit integer expressed by the destination. Each successive digit in this integer encodes the settings for the switch in the next stage along a desired path. The control is called distributed if the devices, using the network switches can be set their own based on the tag information... Type of routing in MINs The routing in multistage interconnection networks take place through the generation of routing tags, which specify a fault free path. There is basically three type of routing that is commonly used in multistage interconnection networks....1 Non adaptive routing: In this method a source leans a fault when a path it is attempting to establish reaches the faulty network component. A notice of fault is sent to the source, which tries next alternative path. This method has poor performance though it requires little hardware.

36 ... Adaptive routing: The adaptive routing can be of the following types: Notification on demand: with notification on demand, a source maintains a table of faults it encountered in attempting to establish paths and uses this information to guide the future routing. Broadcast routing: With broadcast notification of a fault, all the sources are notified of the fault components as they diagnosed.... Dynamic Routing: A fault free path need not be specified by a source if the routing tags are modified in response to the faults as a path is followed or established. The dynamic routing can be accomplished in multistage interconnection networks constructed of switches, which are capable of performing the necessary tag revision.. Fault tolerance A fault tolerance[10] multistage interconnection network provides service routing even under the faults. Fault can be permanent or transient in nature. Fault tolerance is a criteria that must be met for the network which has tolerated a given fault or faults. A network is a single fault tolerant if it can function as specified by its fault-tolerance criteria despite any single fault conforming to its faults models. In general, if any set of I- faults can be tolerated by a network, then network is I-fault tolerant. A network that can tolerate some instances of I-faults is robust although not I-fault tolerant.

37 CHAPTER A survey of MINs.1 Introduction To solve the problem of providing fast, reliable and efficient communication at a reasonable cost in large parallel processing systems, many different networks between the extremes of single bus and the cross bar have been proposed. Such interconnection networks can be constructed from single or multiple stages of switches. In a single stage network, data may have to be passed through the switches several times before reaching the final destination. In multistage network, one pass of multiple stages of switches is usually sufficient. Sources Destination 0 i u 0 O u i u 0 O u N-1 I u N O u N N-1 Fig..1 Conceptual view of a single stage interconnection network

38 A conceptual model of a single stage network to interconnect an N component parallel processing system is shown in fig.1, which indicates that the single stage network can be viewed as an intra-connected set of N input and N output units. The way input units are connected with the output units, determine the functional characteristics of the network i.e. the allowable interconnections. The single stage network is also called a recirculating network. Data items may have to recirculate through the single stage several times before reaching their final destination. Number of recirculations needed depends upon connectivity in a single stage network. In general, the higher is the hardware connectivity, the lesser is the number of recirculations. Multistage interconnection networks are built from the stages of the basic from stages of the basic single stage networks. Communication through MINs varies in multiprocessor systems and therefore a number of MINs have been proposed, analyzed and notified by various researchers. MINs have different design depending upon the number of stages, number of SEs per stage and number of links etc. The design also determines the control strategy and routing algorithms. Therefore, different MINs offer varying degrees of reliability, efficiency, cost and fault-tolerant. 8

39 MINS UNIQUE PATH MULTI PATH REGULAR MINS IRREGULAR MINS STATIC DYNAMIC STATIC DYNAMIC Fig.. Classification of MINs 9

40 . Unique- path MINs Unique path MINs is characterized by the presence of a single path between any sourcedestination pair. They are not even single fault tolerant and failure of even one of the switches disconnects some of the source-destination pairs. Further, distinct sourcedestination pairs may have common link, therefore, blocking of link due to preoccupation may occur. Hence, they are unreliable, as they are non-fault tolerant. Some of the examples of these MINs are described below:..1 Crossbar Network The crossbar[1] MIN is shown in Fig..It is the simplest and cost intensive method for connecting N sources to N destinations. Total No. of Stages =N Main features: For a N network No. of stages = N No. of Switches/ Stage = N Total No. of stages =N Limitations: Cost intensive way of connection, which becomes highly prohibitive for a large network. 0

41 Fig.. Crossbar Network.. Omega Network The Omega[] network is shown in Fig... In Omega network the interconnection pattern is often called as Perfect Shuffle. The routing in this network takes place based on the destination tag. If tag bit is 0 signal goes to the upper destination and if it is 1 then the request is routed to the lower destination. Unlike Crossbar it is a Blocking network, because not all set of requests are processed simultaneously. Conflicts can occur over the use of an interconnection or the switch as well as between the requests and replies. Main Features: For a N network: No. of stages=log N No.of switches per stage = N/ Total No. of switches= N/ log N 1

42 Fig..Omega Network

43 Fig..Generalized Cube Network

44 .. Generalized Cube Network The generalized cube network is shown Fig... It is very much similar to the Omega network explained above and is also an example of the Unique path MINs. Main Features: For an N*N cube No. of stages= log N No.of switches per stage = N/ Total No. of switches = N/ log N.. Shuffle Exchange network Shuffle Exchange network is based on routing functions that are Shuffle and Exchange. A perfect shuffle of N=8 is shown in Fig. Perfect shuffle[1] cuts the deck into two halves from the center and intermixes them evenly. Inverse perfect shuffle does the opposite to restore the original ordering as shown in Fig (0) (1) () 011 () 100 () 101 () 110 () 111 () Fig. A perfect shuffle 000 (0) (1) () 011 () 100 () 101 () 110 () 111 () Fig. A Inverse shuffle

45 The unique paths MINs have many important properties 1) The hardware cost is of O (N log N), providing N simultaneous paths having pathlengths O (log N). ) They provide simple and distributed routing algorithms making the central routing unnecessary and thus result in low communication latency times. ) A unique path exists between any source to any destination, and distinct source/ destination paths may have common links. There are few problems with this kind of configuration. They are 1) A source/destination connection may be blocked by a previously established connection thereby providing a poor performance in a random access environment. ) The failures of even a single link or switch will cause disconnection of several source/destination paths. Such a MIN with 1 source and 1 destinations, built from * switching elements is the shuffle-exchange MIN that, can be easily depicted in the Fig.. Multi-path Static Regular MINs..1 Benes Network The Benes network is shown in Fig..8. It is also similar to the Omega Network but is no blocking problem in the Benes network as it has more number of stages compared to the Omega network. Unlike the Omega network, in which there is exactly one path from any source to the destination, in Benes network there are many alternatives. For example source 0 can be connected to the destination to the destination 0 via 1A, A, C, A, A, but another route is through 1A, C, C, C, A.If the complete list of source-destination pairs is available, it is possible to find a set of routes beforehand provided n o two sources want to use the same destination simultaneously. However, if the requests come in sequential order, it is not always possible to satisfy al of them due to the sequential order,

46 it is not always possible to satisfy all of them due to the choices already made. The routing in this network is much more complex compared to the Omega Network as the choice for the selection of a route is made at every step.. Multipath Regular Dynamic MINs In these MINs, a fork at every SE re-routes the data to an alternate available path without resorting to the backtracking. It avoids the unnecessary time delay and the fault-tolerance is generally achieved by providing extra links in the network.. Multipath Regular Dynamic MINs..1 Augmented Shuffle Exchange MINs The Augmented Shuffle Exchange[] MINs provide the fault-tolerance using links between the Conjugate pairs of switches. At a stage I, two switches k and 1 belong to the same conjugate subset if k =1 mod I. In each conjugate subset of switches there are several pairs of switches called Conjugate pair of switches. For example in Fig.9 the switches (1,0) and (,0) form conjugate pair since both are connected to the switches (,1) and (,1). Conjugate subsets and Conjugate pairs of switches play a fundamental role in the augmentation scheme. The scheme for creating multiple paths is based on connecting the switches to a conjugate subset by using additional links to form loops for this purpose the * switches by 8 switches. The vertical links that are used to connect switches in the same stage are called auxiliary links. The network of Fig.9 shows this augmentation. By using these auxiliary links fault-tolerant routing can be accomplished. If a switch is not able to process a request because o a faulty switch in the next stage or because of a busy link, it can re-route that request via its auxiliary destination link to the conjugate switch in the loop. The next switch in turn will make connection to a different (non-faulty) switch in the following stage. For example, suppose a connection is made from source link 8 to destination link. Under the normal conditions, the path will be (,0), (0,1), (1,) and (,). Now suppose that switch (1,) and (,). Now, suppose that switch (1,) is faulty,

47 Fig.8.Benes Network

48 using an auxiliary link whenever a fault is encountered allows any source to be connected to any destination while tolerating any single faulty switch in any stage other than the initial stage and the final stage. If a switch failure occurs at the initial stage then it disconnects those sources from rest of the network. Similarly, a switch failure in the final stage disconnects the destinations attached to that switch. To attain fault tolerance in these stages (Initial and final), each source and destination must be provided with at least switches. Schemes for connecting sources and destination must be provided with at least one additional input/output link so that they can be connected to two switches. Schemes for connecting sources and destinations equipped with two ports each are shown in Fig..9 A *1 multiplexer is placed at each source link of stage 0, and each source is connected to two distinct multiplexers. To provide additional connections to the destinations, N 1* demultiplexers replace the N/ switches in the final stage of MIN. Each destination is directly connected to two demultiplexers. In this Fig..9 various loops are so formed subject to the condition that no two switches in a given loop form the conjugate pair, in order to achieve the property of on-line repair and maintenance in addition to single fault-tolerance. Such a network is called an augmented shuffle exchange network or ASEN. The ASEN-Max with maximum number of switches connected in a loop is shown in fig. Similarly ASEN- and other networks can be formed. In general, an ASEN with number of switches in a loop in stage I is equal to min ( n-i-, K) is called ASEN-K. 8

49 Fig.9 ASEN 9

50 . Irregular MINs..1 Four-Tree Network (FT) FT[] network is represented in Fig.10 FT is an irregular Dynamic MIN that supports multiple paths of different lengths. Two subgroups of identical sub networks are used in its formation each having the size ^n-1 * ^n-1 are used. In this network * switches are used instead of * switches. Ever * switch in first subnetwork forms a loop with the corresponding switch in the other subnetwork. Connecting both the subgroups by means of the Multiplexers and Demultiplexers provides the Fault Tolerance in the first and the last stages. Every request is first tried to be routed through the primary path, if unavailable due fault or if it is busy, the request is routed through the path, if unavailable due fault or if it is busy, the request is routed through the other subnetwork. Thus a fork is available at every stage except the last sage which makes alternate routing possible. FT is a single-fault tolerant in nature. For a N*N FT network Main Features: No. of stages= log N/-1 No. of to 1 Multiplexers= N No. of 1 to Demultiplexers= N No. of SEs in stage i and log N/-1= n-i-1 0

51 Fig.10 FT 1

52 .. Modified Four tree network MFT represented in Fig.11.which uses one stage less, compared to the FT and uses two switches less compared to the FT. It connects all sources to the destinations and provides fault-tolerance and reliability features well as FT. Here the maximum path length is, which is one less compared to FT. Thus there is benefit in terms of cost and path-length. Also, as it uses lesser number of paths and switches, therefore, more fault tolerant. More the number of links and switches more are the number of faults. For a N*N MFT network Main Features: No. of stages = log N/- No. of to 1 Multiplexers = N No. of 1 to Demultiplexers = N No. of SEs in stage i and log N/-= n-i-1 If the number of switches at different stages in an network are not the same then such networks are called Irregular networks. Irregular networks are inherently multi-path in nature but, they may or may not be fault tolerant i nature. We will discuss both the Unique and Multi-path Irregular MINs.

53 Fig..11 Modified FT

54 Chapter Permutation Passabiltiy in MINs.1 Introduction In unique path multistage interconnection networks there is a unique path between a source and a destination. While multipath multistage interconnection networks provide more than one paths from a source to a destination. In multipath multistage interconnection networks, the request is routed through an alternative path, if the most favorable path is not amiable due to the reasons: œ Some switch(es) in that path may be faulty œ Some other request is occupying that path at that instant of time In the multipath MINs a very important performance parameter is the Permutation passability (which means that if a number of requests simultaneously occur at source at a particular moment of time then how many of them successfully mature after being routed through the network). The network tries to send the request firstly through the most favorable path if such path is not available then the request is routed through the alternative path. If there is no alternative path available, the request is dropped. The desirable character of any network is that the network should be such that it allows maximum requests through it with minimum path length. A minimum path length means a request will: œ Take less time to reach destination œ Have less probability of intermediate link failures So problem can be defined as to find permutation passability of regular and irregular networks under fault is calculated. This will show that at a particular moment of time, if a number of requests simultaneously occur at source, how many of them successfully mature will i.e. will reach their destination.

55 . Simulation Analysis The simulation of permutation passability behavior of a network will generate randomly the number of requests that will appear at source side at a particular instant of time. The same numbers of source/destination pairs are formulated. Each request is tried routed through its most favorable path, others have to be routed through an alternative path. In case the former is already busy in serving to some other request, the remaining will have to be simply dropped, due to unavailability of an alternative path between the source and destination. This simulation analysis of permutation passability behavior is checked for 0 times, for each network, taking different number of inputs appearing at source side. Then total number of request matured and average path length is calculated. The regular networks which are simulated are: œ ASEN And the irregular networks are: œ œ Four-Tree Networks (FT) Modified-Four Tree networks The following regular and irregular multistage interconnection networks to be analyzed on the basis of two parameters i.e. number of requests reaching the destination and average path length.. Simulation of Permutation Passability in Regular Networks No. of Requests = N Request Matured = RM Average Path Length = APL

56 N Source/Destination Pairs [,][,][10,1][1,11][,1][,] [,1][1,10][1,1][11,][,] [1,0][11,][0,][1,1][10,0][9,] [,][8,0][1,] [,8][1,1][,11][11,][1,1] [1,1][8,10][10,1] [11,9][,][1,][10,] [0,9] [10,][,1][1,][1,][,1][1,0] [0,0][,][,][8,][1,1] [1,][10,][1,1][1,1][,1][11,9][1,][8,8] [9,11][1,1][,][10,1][11,1][1,11] [1,11][,9][1,1] [,1][1,][11,][0,][10,][,][, 1][9,][1,9][1,1][,] [1,][1,1][0,][,][9,1][,][1, 0][1,1][,][,10] [1,][9,][1,][1,1][,8][,9] [,][1,1][8,1] [10,][8,][,9][,0][,][1,1] [,1][,1][,1][1,1][1,] [,1][1,][10,1][,1][11,] [9,][,8][1,][,10][,8] [9,1][,1][,8][1,][,][8,11] [,8][8,8][11,1][1,][1,1] [1,0][1,][1,] [8,8] [1,9][,9][,1][,9][9,1][,1] [1,0][,0][8,10][11,] [,1][11,][8,][1,1][1,8][,1] [,8][1,] RM APL N Source/Destination Pairs [,][,][10,1][1,11][,1][,] [,1][1,10][1,1][11,][,] [1,0][11,][0,][1,1][10,0][9,] [,][8,0][1,] [,8][1,1][,11][11,][1,1] [1,1][8,10][10,1] [11,9][,][1,][10,] [0,9] [10,][,1][1,][1,][,1][1,0] [0,0][,][,][8,][1,1] [1,][10,][1,1][1,1][,1] [11,9][1,][8,8] [9,11][1,1][,][10,1][11,1][1,11] [1,11][,9][1,1] [,1][1,][11,][0,][10,][,] [,1][9,][1,9][1,1][,] [1,][1,1][0,][,][9,1][,] [1,0][1,1][,][,10] [1,][9,][1,][1,1][,8][,9] [,][1,1][8,1] [10,][8,][,9][,0][,][1,1] [,1][,1][,1][1,1][1,] [,1][1,][10,1][,1][11,] [9,][,8][1,][,10][,8] [9,1][,1][,8][1,][,][8,11] [,8][8,8][11,1][1,][1,1] [1,0][1,][1,] [8,8] [1,9][,9][,1][,9][9,1][,1] [1,0][,0][8,10][11,] [,1][11,][8,][1,1][1,8][,1] [,8][1,] RM APL ASEN network When no switch is failed When switch is failed