VOSync: An Implementation of Synchronization System for The Virtual Orchestra

Transcription

1 VOSync: An Implementation of Synchronization System for The Virtual Orchestra Chung-Ping Young, Yen-Bor Lin and Ting-Ying Wei Department of Computer Science and Information Engineering National Cheng-Kung University No.1, University Road, Tainan City 701, Taiwan (R.O.C.) yen Abstract The proposed system integrates the IEEE 1588 standard with the Pulse Per Second (PPS) mechanism to improve the accuracy of timing synchronization of the multiple nodes. A reference implementation for the virtual orchestra was given and introduced to evaluate the performance. It operates in the form of a character device driver and the application interface (API) was built for a programmer to use this proposed system. The experimental results show that the accuracy achieves the degree of several microseconds and the proposed system is acceptable for the application. Index Terms IEEE 1588, Clock Synchronization, Pulse Per Second System, Precise Time Protocol I. INTRODUCTION Virtual orchestra is a distributed multitrack music replaying system, where several wired/wireless networked speakers are spread over the field and controlled by a music streaming server. The replaying timing is critical since each speaker is programmed to receive, decode, signal-process and play an individual track at specific time, so the whole work will be broadcast with special sound effect or in concord. Unfortunately, the oscillator of each connected device node drifts all the time [1], and the timing problem will occur because of manufacturing and the change of ambient temperature. If the frequency deviation of a low-cost quartz oscillator is about ±100 ppm, the time error would be 100 μs at a one-second synchronization interval. Thus, the synchronization becomes an unavoidable issue among all the device nodes of a virtual orchestra. To solve this problem, we propose the way to correct the clock skew in software. The IEEE 1588 standard [2], [3] just describes how to calculate the clock skew but there is no more information about how to control the clock offset. Thus, we proposed a system to ease off the effect of the clock offset. This consists of two components including the Pulse Per Second (PPS) component [4], which arises the pulse at the beginning of a second, and the IEEE 1588 component. The front one is response for gathering the UTC time from an NTP server and the compensation for the clock of the grand master. The latter is used to synchronize the slaves to the grand master. The RFC 2783 specification [5] is also hired to bridge PPS and IEEE Beside, the idea of a native feedback controller with the stability characteristic is also integrated with the two components. The problem of IEEE 1588 to overcome is the failure of the microsecond accuracy without hardware support. [6] It Fig. 1. The precise time protocol. even decreases the accuracy from the order of microseconds to milliseconds in those cases. The further explanation will be given in section II-B with a short description about the Precise Time Protocol (PTP) which handles the exchange of timestamps from the PPS subsystem to achieve the synchronization. Each round of the message transaction defined by the PTP had been described in Fig.1 [7]. The instants to send the timestamps in the nodes A and B are t 1 and t 3 respectively. The instants to receive the timestamps are t 2 and t 4 with respect to t 1 and t 3. Then, the network delay is expressed by: T AB =(t 2 T 0 ) t 1 (1) T BA = t 4 (t 3 T 0 ) (2) where T 0 represents the clock offset, T AB is the network delay from t 1 to t 2, and T BA is the network delay from t 3 to t 4. The frequency offset within these two nodes is negligible and the clocks are assumed to be perfect clocks. Then, the clock offset is obtained by: T 0 = t 2 t 1 (t 4 t 3 ) T AB T BA (3) 2 2 which T AB T BA means the noise caused by the asymmetric network delay. However, PTP assumes the network delay is symmetric and therefore the following formula is obtained: T 0 = t 2 t 1 (t 4 t 3 ) (4) 2 The clock offset computed by the algorithm of PTP is the source of the noise that affects the accuracy of the system seriously /16/$31.00 copyright 2016 IEEE ICIS 2016, June 26-29, 2016, Okayama, Japan

2 The solution is classified into two categories. One is to enable the hardware support which measures the network delay [8] in each node and provides an interface to transfer the measured value into IEEE 1588 components.[7] Another is to use a filter, such as Kalman filter[9], to filter the the clock offset and the network delay or to use the clock servo mechanism and adjust the clock with the feedback result. II. THE PROPOSED MECHANISM Under the distributed network environment, there are several reasons to produce the jitter including the instability of the clock offset, the scheduling latency, the interrupt latency and the resolution of the system clock. [10] To achieve the synchronization, in this proposed design, the PPS system is hired and integrated with the state machine of IEEE 1588 protocol.[10] The synchronization of the start point is handled with a synchronization protocol. In this paper, the PPS subsystem and PTP subsystem cooperate to perform the synchronization for the virtual orchestra. The PPS system receives the PPS signal from certain device, such as a GPS receiver[11], and PTP system performs the actions defined in IEEE Besides, a solution to synchronize the clock to a GPS receiver is provided. Therefore, the accuracy of the proposed system was shown achieving the sub-millisecond in the experimental result section. They will be introduced in advance in the follows. A. The synchronization of the starting point There are four main factors for a slave to output the signal at the skewed time. First, the asymmetric network delay comes from the server s issuing the transmission of a message at different instant. Secondly, the time error may make the slaves capture the different time stamp even the slaves actually output the signal at the same time. Thirdly, the rate error may make the slaves wait with the drifted system clock and incur the slaves waiting with a wrong time scale. Finally, the last one factor is the schedule latency which is ignorable when this synchronization protocol is applied on a non Operating System (non-os) platform. There is a master device which acts to issue the message carrying the timing information and to build a multicast communication requesting the slaves to output the signal at a specific instant. In Fig.2, S1 and S2 represent the two slaves for example, the M node stands for the master device. When a slave receives the message, it will wait for a while according to the received message from the master device and then output the signal. S1 and S2 will issue the request to the master when the synchronization has been stable. After M has received the requests from the slaves, it will perform a period of block waiting and then issue a message to inform the slaves output the signal. In the synchronization period, the PPS system unifies the clock speed of the slaves, and IEEE 1588 system correct and control the time error and the rate error among the slaves. Thus, the system maintains the accuracy in the degree of microsecond. Fig. 2. The synchronization protocol for the starting point. Fig. 3. The IEEE 1588 protocol. B. The IEEE 1588 protocol and the PTP As shown in Fig.3, there are four main units including the protocol engine unit, the protocol computation unit, the clock correction computation unit and the message computation unit. The clock correction computation unit is responsible for executing the Best Master Algorithm(MBA) to divide the subsystem of time synchronization in order to construct the system in the form of a spanning tree and to make each child have only one parent. The message computation unit is responsible for handling every kind of receiving messages as well as capturing timestamps. IEEE 1588 had defined two ports, which are event port and general port respectively, and four message types. Sync and Delay Req messages send out from the event port. Follow up and Delay response messages are received from the general port. In Fig.4, the timestamps of t1 and t4 are captured in the network interface card (NIC) driver, these are gotten with loop back from switch, recorded in Follow up message, and then are sent to the slave. A Slave captures the timestamp of the receiving message at the time t2 and t3 through the modified NIC driver. To the every kind of a message header, we implemented the message handler with the definition of IEEE 1588 and used these handlers to collect the foreign messages and to filter other messages which are

3 Fig. 4. The synchronization protocol for the starting point. not relevant to the local clock. After we have obtained the timestamps of t1, t2, t3 and t4, we commit them to the protocol computation unit in order to get the clock offset estimation and the network delay estimation through the PTP calculation. However, the correctness of the timestamps is still not enough because of the definition of outbound latency and inbound latency in IEEE Therefore we adopt the way of clock servo presented in [12] to compensate the timestamp and the network delay. The PTP is one of the most important algorithms of IEEE 1588 to calculate the clock offset and the network delay. It can be expressed by the following equations to obtain the times [13]: Delay + Offset = t 2 t 1 (5) Delay Offset = t 4 t 3 (6) Delay =((t 2 t 1 )+(t 4 t 3 ))/2 (7) Offset =((t 2 t 1 ) (t 4 t 3 ))/2 (8) where the term Delay represents the field of one way delay which is the network delay estimation derived from IEEE 1588 and the term Offset represents the estimated clock offset. The meaning and relationship among them are illustrated in Fig.4. C. The Pulse Per Second (PPS) subsystem With time passes by, the skew between the general clock of the grand master increases gradually and drifts far away finally. In general, the clock speed could not be corrected immediately and the pulse offset still comes after the clock speed is corrected and no frequency offset exists. Here, the goal of the PPS subsystem is to minimize the frequency offset and the time offset. The architecture of the PPS subsystem is illustrated in Fig.5. It generates a pulse per second with a 100 milliseconds duration of a phase. The GPIO 64 on the Creator PXA270 platform is used to receive the PPS signals used only for the master clock from the GPS module. The PPS management unit performs the PPS clock servo algorithm and is consist of two parts these are the top halve and the bottom halve to decrease the interrupt latency. The job items of the two parts are listed in the diagram. In this implemented sample system, the source of the timestamp is selectable by the implemented function named time pps kc bind() and will be adopted to compute the clock frequency offset. The PI controller is the default method to control the clock and is used to minimize the clock offset. The adjustment in microseconds is obtained from the PI controller and is fed into the kernel frequency locked loop (FLL) unit to adjust the system clock. The interface named do adjtime() in the kernel is exported to make the PPS driver possible to use this subroutine. The frequency based adjustment method is chosen to correct the clock because of the larger adjustment range compared to the tick based adjustment method. The clock rate adjustment of the PPS clock servo algorithm is formulated by Correction ClockRate =(offset time /P + offset freq /I)/N (9) where P presents the proportional term to correct the time offset, I presents the integral term to track the frequency offset, and N presents the scale of adjustment. The goal is to remove the original pulse offset at the beginning in Fig.6. The implemented PPS system divides the pulse offset into the time offset and the frequency offset, and they are corrected gradually. D. The RFC2783 The interfaces defined in RFC2783 are adopted to integrate the subsystems with the IEEE 1588 protocol and to make the programmer get easy to use the proposed system. The whole system is modelled as a character device driver and is named a PPS driver. III. THE EXPERIMENTAL RESULTS In this section, the three types of the errors as shown in Fig.7 including the wall time error, the frequency/rate error and the time error will be evaluated with a sample implementation to show the performance. The results will show the proposed system had converged not only the rate error and time error but also the wall time error within several microseconds. A. The experimental setup Fig.7 shows the experimental environment and the three types of the errors are labelled on where they are extracted. Without the lack of generality, this sample implementation includes one master node and two slave nodes. We used PXA270 platform to receive PPS signal with GPIO pins. In this section, the values of P term, I term and N term of the implemented PPS subsystem described in section II-C were set to be 2500, 1000 and 1 respectively. The PPS debug printer and the IEEE 1588 debug printer were implemented to record the information, the timestamps as an example, from the modified char device driver as the measured results related

4 Fig. 5. The architecture of Pulse Per Second subsystem. Fig. 6. The timing diagram to demonstrate the PPS clock servo algorithm. to the mentioned errors into the files because the implemented driver cannot operate on any file in kernel mode. The results were obtained as shown in Fig B. The grand master The grand master got the rough wall time at the beginning and the wall time was refined to be accurate in several microseconds. The record information of the correction processes are shown in Fig.8 and Fig.9. The horizontal axis indicates the time passes by and the unit is second. The vertical axis indicates the offset and the unit is microsecond. It had been found that the system clock of the grand master was faster for 50 microseconds and the PPS subsystem performed the correction jobs over and over. Finally, the frequency offset oscillated within +2 to -4 microseconds and the wall time offset oscillated within +7.5 to -3.5 microseconds. Note that the wall time offset was measured as the time offset between the considering clock and the UTC time from NTP server. The results mean the system provides a good qualified clock to the IEEE 1588 protocol. C. The salve In this section, the GPS clock was treated as the reference clock to measure the errors of the slave node. As shown in Fig.10, the rate error achieved 59 microseconds and oscillated within 51 to 54 microseconds. Obviously, the system operated in the wrong frequency and it caused the linear increasing in wall time error as shown in Fig.11. With the proposed PPS subsystem, though the time error was large at the beginning, for 687 microseconds as an example shown in the Fig.13, the IEEE 1588 protocol decreased the time error quickly and the curve becomes gentle after the 22th second in Fig.12. Note that the time error is different with the wall time error. Finally, the rate error oscillated within -4 to -1 microseconds and the time error oscillated within +10 to -20 microseconds. To observe the effect of the accuracy of the master, the GPS clock was treated as the reference clock again to measure the wall time error. The measured curve in Fig.14 is similar to that in Fig.13. This shows that the time produced on the regulated master is very closed to the UTC time and the proposed system is a good choice to track the master clock and to remove the time error. D. The case study - a distributed media player system To demonstrate the effectiveness of the proposed synchronization system, we also implemented a distributed multichannel media player operating on Linux based on the Creator Xscale PXA270 platform. The preliminary result focusing on the sound output will be given in this section. The implementation includes the start point synchronization and decoding as well as playing the music. For convenience, we assume the music data had already been received and the MPlayer was used to decode the music file in PCM format. The multimedia player system performed the start point synchronization, as described in section II-A. The media player system was programmed with Open Sound Source (OSS) architecture to output the sound of the music. To take the whole picture of the implemented player here, we briefly describe the applied procedures of a part of the

5 Fig. 7. The experimental environment and the three types of the errors to measure. Fig. 8. The frequency offset on the grand master. Fig. 10. The rare error on the slave without the proposed design. Fig. 9. The wall time offset on the grand master. designed and implemented API. First at all, the function configure multicast() was called to configure the multicasting for IEEE 1588 and the start point synchronization protocol. Next, The function config IEEE1588() was executed to configure IEEE 1588 system consisting of the function configure PPS DRIV ER() to add the PPS system into the kernel for the configuration of the interrupt routine and handling the PPS interrupt. The measurements including the time offset and frequency offset were also obtained by the activated PPS debugger printer with the function configure PPS PRINTER(). Then, the sampling rate and the channel to play the music were configured by the function music configuration(). During the time interval in the running state, the function run Startpoint protocal() was performed to obtain the play time and the wait() function was called to wait until the play time comes. Finally, the music was played using the function output music(). Therefore, the PPS system regulated the master s clock, and the IEEE 1588 system synchronized the slaves such that the speakers played the audio data at the same time. This makes the electrical band Fig. 11. The wall time error on the slave without the proposed design. Fig. 12. The rare error on the slave with the proposed design. of multi-instrument become realizable. In this case, the song named Jingle Bells was divided into the soprano&tenor part and the alto&bass part. In Fig.15, the vertical axis indicates the offsets between the start points to play the music and the horizontal axis indicates the times of the request. In this experiment, we commanded the slaves

6 clock offset are well-controlled. This system is a good solution and satisfies the application requirement in the accuracy of several microseconds. In the future, the Kalman filter, as described in [9] to offer the better estimation of clock offset and clock skew in software implementation, will be considered to cooperate for compensating the network delay asymmetric and timestamps asymmetric in more accurate way to increase the accuracy of this proposed system. REFERENCES Fig. 13. The time error on the slave with the proposed design. Fig. 14. The wall time error on the slave with the proposed design. to play the music one second later after the sending time. It can be observed that the variance of the start point offset converged on a stable state. Though the jitter of the clock offset is in microsecond level, the difference of the scheduling speed between the slaves is in the scale of milliseconds. So we could see the start point offset still close to 1 millisecond even if we improved the clock offset by the proposed the clock synchronization and the system entered the stable state. The result shows that our system could improve all slaves to play the sound at the specific time. [1] W. Ye, Ieee1588 clock servo algorithm, in Electronic Measurement Instruments, ICEMI 09. 9th International Conference on, Aug 2009, pp [2] Ieee standard for a precision clock synchronization protocol for networked measurement and control systems, IEEE Std , pp. i 144, [3] Ieee standard for a precision clock synchronization protocol for networked measurement and control systems, IEEE Std (Revision of IEEE Std ), pp , July [4] P. Vyskoc?il and J. Sebesta, Relative timing characteristics of gps timing modules for time synchronization application, in Satellite and Space Communications, IWSSC International Workshop on, Sept 2009, pp [5] J. Mogul, D. Mills, J. Brittenson, J. Stone, and U. Windl, Pulse-persecond api for unix-like operating systems, version 1.0, United States, [6] J. C. Eidson, Measurement, control, and communication using IEEE Springer Science & Business Media, [7] H. Weibel and D. Béchaz, Implementation and performance of time stamping techniques, in Proceedings of the 2004 Conference on IEEE, vol. 1588, [8] N. Simanic, R. Exel, P. Loschmidt, T. Bigler, and N. Kero, Compensation of asymmetrical latency for ethernet clock synchronization, in Precision Clock Synchronization for Measurement Control and Communication (ISPCS), 2011 International IEEE Symposium on, Sept 2011, pp [9] G. Giorgi and C. Narduzzi, Performance analysis of kalman-filterbased clock synchronization in ieee 1588 networks, Instrumentation and Measurement, IEEE Transactions on, vol. 60, no. 8, pp , Aug [10] Y. Bang, J. Han, K. Lee, J. Yoon, J. Joung, S. Yang, and J.-K. Rhee, Wireless network synchronization for multichannel multimedia services, in Advanced Communication Technology, ICACT th International Conference on, vol. 02, Feb 2009, pp [11] A. Carta, N. Locci, C. Muscas, F. Pinna, and S. Sulis, Gps and ieee 1588 synchronization for the measurement of synchrophasors in electric power systems, Comput. Stand. Interfaces, vol. 33, no. 2, pp , Feb [Online]. Available: [12] K. Correll, N. Barendt, and M. Branicky, Design considerations for software only implementations of the ieee 1588 precision time protocol, in Conference on IEEE, vol. 1588, 2005, pp [13] K. Lee, J. C. Eidson, H. Weibel, and D. Mohl, Ieee 1588-standard for a precision clock synchronization protocol for networked measurement and control systems, in Conference on IEEE, vol. 1588, 2005, p. 2. Fig. 15. The offset of start point between the slaves for the distributed media player system with the proposed synchronization design. IV. CONCLUSION AND FUTURE WORK The proposed synchronization system is introduced and was implemented on Creator Xscale PXA2770 platform to obtain the experimental results showing that the clock speed and the