IEEE 1588, Standard for a Precision Clock Synchronization Protocol

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1 IEEE 1588, Standard for a Precision Clock Synchronization Protocol What is it? Where is it used? How does it work? How to implement it? Prof. Hans Weibel, Zurich University of Applied Sciences hans.weibel@zhwin.ch 2005 ZHW

2 What is it all about? Master Packet Network Distribution of frequency and time over a packet network Slaves ZHW / H. Weibel, Emedded World / 2

3 IEEE 1588 and other Time Dissemination Networks Why a new standard? NTP does a good job since many years runs on legacy data networks but some applications demand for much higher accuracy Specialized sync networks can do this job more accurate but at much higher cost e.g. IRIG-B, a specialized dedicated sync network e.g. GPS, allows for global synchronization, requires outdoor antenna IEEE 1588 offers high accuracy over a data network but requires hardware assistance applicability restricted to a closed environment ZHW / H. Weibel, Emedded World / 3

4 Nature and Importance of System Time System time can exist in different ways implicitly: the system does not have a real clock, but a timing behaviour given by operational sequences in HW and/or SW; typical in small closed systems explicitly: time is represented by a clock; in complex systems most often a necessity System time is important to coordinate measurement instant (sampling, triggering) to measure time intervals (and to calculate derived quantities) as a reference to determine the order of events to determine the age of data items (data correlation; data base replication) as a basis for the execution of coordinated actions (time based behaviour) scheduled execution of scripts scheduled execution of mutual exclusion to decouple communication from execution ZHW / H. Weibel, Emedded World / 4

5 Some important Definitions Accuracy and Stability Deviation from the Reference inaccurate and not stable inaccurate and stable accurate and stable accurate and not stable inaccurate and stable t ZHW / H. Weibel, Emedded World / 5

6 Application of synchronized Clocks Where is sub-µs Accuracy required? Automation and control systems Synchronize multi axis drive systems Synchronize subsystems with cyclic operation Measurement and automatic test systems Correlation of decentrally acquired values Time stamping of logged data Power generation, transmission and distribution systems Control of switching operations Reconstruction of network activities and events Isolation of problems (distinguish cause and impact) Ranging, Telemetry and Navigation Triangulation Telecommunications Emulation of TDM circuits through packet networks Backup for other time sources Loss of GPS signal ZHW / H. Weibel, Emedded World / 6

7 Application of synchronized Clocks Automation and Control Systems Application of IEEE 1588 is announced by different organizations proposing Real-time Ethernet concepts, such as ETHERNET Powerlink EtherCAT CIPSync ProfiNet System wide clock does not guarantee but enable real-time behaviour with mechanisms such as cyclic operation time stamping of data scheduled actions and communication communication decoupled from execution ZHW / H. Weibel, Emedded World / 7

8 Application of synchronized Clocks Automation and Control Systems Example: Multi axis motion control, e.g. in a printing machine Many drives have to be synchronized Paper speed is 25m/s ( corresponds to 40µs/mm) ZHW / H. Weibel, Emedded World / 8

9 Application of synchronized Clocks Automation and Control Systems Example: Multi axis motion control, e.g. in coordinated robots Picture: KUKA Roboter GmbH ZHW / H. Weibel, Emedded World / 9

10 Application of synchronized Clocks Measurement and Data Acquisition Systems Capture / acquire data within a distributed environment simultaneously at different places deliver data with a time stamp Processing Correlate the data Report the order of events to enable diagnosis Reconstruct complex, fast and distributed activities Straight forward installation Sync and data over the same standard packet network no special sync lines required ZHW / H. Weibel, Emedded World / 10

11 Application of synchronized Clocks Automatic Test Systems Example: Automatic Test Systems based on Synthetic Instruments What is a Synthetic Instrument? A collection of hardware and software modules that can be concatenated together and configured to emulate a standard instrument. Advantages: re-configurable, re-usable, less rack space! What is a Synthetic Instrument module? An elementary building block of a larger measurement system. Synthetic Instrument modules can be used in reconfigurable applications Simpler the building block, the easier to upgrade Standard interfaces Application software is external to the Synthetic Instrument module ZHW / H. Weibel, Emedded World / 11

12 Application of synchronized Clocks Power Generation, Transmission and Distribution Syst. Components of the power grid have to be protected from critical load situations and turned off Protection switching guarantees high service availability U/I is measured at all critical points within the grid at precise time points and in a high rate to monitor the network to predict critical load situations to measure delivered/consumed power between providers The traditional solution for synchronization is based on a dedicated and costly cabling (e.g. IRIG-B) Using the same network for data and synchronization has big economic and operational advantages ZHW / H. Weibel, Emedded World / 12

13 Application of synchronized Clocks Power Generation, Transmission and Distribution Syst. Example: Substation Automation according to IEC ZHW / H. Weibel, Emedded World / 13

14 Application of synchronized Clocks Telemetry / Navigation t 1 t 2 t 3 Example: Positioning System for Divers (Submarine Navigation) Principle is similar with GPS, but sonar instead of radio bojes insted of satellites ZHW / H. Weibel, Emedded World / 14

15 Application of synchronized Clocks Telecommunications Frequency distribution over packet networks Circuit Emulation Service in packet networks (TDM over Packet) becomes more and more attractive in IP-centric infrastructure compelling solution in pure Ethernet configurations such as Metro Ethernet or Eternet in the First Mile Base station synchronization for handover (GSM, DECT, ) Single Frequency Networks (SFN) such as Trunk Radio systems or DVB, where all transmitters are synchronously modulated with the same signal and operate on the same frequency Benefits for Operations Support Systems (OSS) Billing mechanisms SLA-compliance checking ZHW / H. Weibel, Emedded World / 15

16 Application of synchronized Clocks Telecommunications Example: Emulation of a TDM Circuit over a Packet Network Packet Network may be Metro Ethernet, IP, ATM or MPLS Sync Network may be separate or - if IEEE 1588 is applied - the same as for the payload Goal is f s = f d Bit Stream (TDM) Edge Packet Flow Packet Network Switch Edge Bit Stream (TDM) Packetization De-Packetization Clocking Data In f s f d Clocking Data Out Synchronization Network ZHW / H. Weibel, Emedded World / 16

17 IEEE 1588 Specification Contents of the Standard descriptors to characterize system clocks states and behaviour of system clocks data type definitions time representation Precision Time Protocol (PTP) operation Determination of a loop-free topology Selection of the master clock (Master Clock Selection Algorithm) Syncronization of system clocks details of application in Ethernet networks conformance requirements ZHW / H. Weibel, Emedded World / 17

18 IEEE 1588 Specification Goals synchronization of distributed system clocks with high precision (< Gs ) applicable in any multicast capable network the focus here is Ethernet easy configuration fast convergence support of a heterogeneous mix of different clocks with different characteristics (accuracy, resolution, drift, stability) moderate demand for bandwidth and computing ressources ZHW / H. Weibel, Emedded World / 18

19 Principal Operation of Clock Adjustment Master Clock PTP UDP IP MAC Phy The Master Clock sends its time to the Slave Clock. The remaining error corresponds to the transfer delay of the time message. PTP UDP IP MAC Phy Slave Clock Network PTP UDP IP MAC Phy Precision Time Protocol (Application Layer) User Datagram Protocol (Transport Layer) Internet Protocol (Network Layer) Media Access Control Physical Layer ZHW / H. Weibel, Emedded World / 19

20 Main Problems are Delay and Jitter Master Clock Delay and Jitter Protocol Stack PTP UDP IP MAC Phy MII The Transfer Delay can be measured and eliminated. It remains an error caused by fluctuations of the transfer delay, called Jitter. MII PTP UDP IP MAC Phy Slave Clock Delay and Jitter Protocol Stack Network PTP UDP IP MAC Phy Precision Time Protocol (Application Layer) User Datagram Protocol (Transport Layer) Internet Protocol (Network Layer) Media Access Control Physical Layer Delay and Jitter Network ZHW / H. Weibel, Emedded World / 20

21 Delay and Offset Determination Master Clock t estim t t pretended concurrency Sync(t estim ) Follow_up(t 0 ) Delay_Req Delay_Resp(t 3 ) Slave Clock 40 O = Offset = Clocks Slave Clocks Master A D = Delay t 1 = t 0 +D+O B O t 2 t 3 = t 2 -O+D measured values t 1, t 2, t 3, t 4 A = t 1 -t 0 = D+O B = t 3 -t 2 = D-O Delay D = Offset O = A + B 2 A - B 2 ZHW / H. Weibel, Emedded World / 21

22 Frequency and Time Transfer Drift Compensation Frequency Transfer When free running, the slave s oscillator has not exactly the same frequency as the master Consecutive time stamped SYN messages allow to determine and compensate the deviation (accelerate or slow down the oscillator) The frequency varies over time (due to environmental conditions, e.g. temperature, acceleration, vibration, etc.) This compensation is repeated regularly (frequency depending on oscillator stability and desired accuracy) Remember: 1 ppm results in 1 us / s Offset Correction Time Transfer Set the slave s time to the master s time Correction is based on the round trip time measurement (carried out by time stamped SYN and Delay_Req messages) ZHW / H. Weibel, Emedded World / 22

23 Sync Interval and Network Load Dimensions 1 ppm of deviation corresponds to 1 µs per second (1 µs/s results in 1s/12 days) a cheap quartz has a temperature dependance of 1 ppm/ 0 C or more In order to achieve high accuracy, frequent adjustments are required the standard allows for Sync intervals of 1, 2, 8, 16 and 64 seconds it is proposed to extend this choice to O, ¼ and ½ seconds Sync and Follow_up messages are sent as multicasts the master can serve all slaves of a segment with one single message this enables each slave to calculate its offset individually (provided that the delay is known) Delay_Req and Delay_Resp messages are point-to-point, but sent with multicast addreses anyway (no address administration required) this enables the slave to calculate the delay (assumed that transmission is symmetric, i.e. same transit delay for both directions) because delay is assumed not to change quickly, it is not measured as frequent as the offset is -> resulting network load is fairly low ZHW / H. Weibel, Emedded World / 23

24 PTP over UDP / IP / Ethernet UDP Port 319: event port for Sync und Delay_Req messages Port 320: general port for Follow_up, Delay_Resp and Mgmt messages IP Time To Live = 0, i.e. will not be forwarded by routers multicast addresses for PTP-primary (default Domain) for PTP-alternate1 (alternate Domain) for PTP-alternate2 (alternate Domain) for PTP-alternate3 (alternate Domain) Ethernet Ethernet Frame Preamble SFD Src Dst L/T Data CRC IP H UDP H PTP Message Time Stamp Point ZHW / H. Weibel, Emedded World / 24

25 Hardware assisted Time Stamping Master Clock Slave Clock PTP Applic. MII MII PTP Applic. estimated send time t 0 Sync(estimated send time) t 1 precise send time Follow_up(precise send time) precise receive time t 2 t 3 Delay_Req Offset Computation precise send time precise receive time Delay_Resp(precise receive time) Time Stamping t t Delay Computation = (t 1 -t 0 )+(t 3 -t 2 )/2 ZHW / H. Weibel, Emedded World / 25

26 Concept of Boundary Clock Eliminate the Network s Fluctuation! Master Clock PTP UDP IP MAC MII Switch with Boundary Clock Slave PTP UDP IP Master PTP UDP IP MAC MAC Slave Clock PTP UDP IP MAC Phy Phy Phy Phy Time Stamp Unit Switching Function ZHW / H. Weibel, Emedded World / 26

27 Topology and Best Master Clock M Ordinary Clock, Grandmaster: clock selected as best Master (selection based on comparison of clock descriptors) M S M M Boundary Clock, e.g. Ethernet switch S S S S S S: Port in Slave State M: Port in Master State M M M S Ordinary Clock ZHW / H. Weibel, Emedded World / 27

28 Implementation How to achieve high Accuracy? Time stamps have to be taken as near as possible to the physical layer, in order to eliminate the impact of protocol stack and operating system software Implementiation with HW assistance: Install a PTP message detector and time stamp unit at the MII (Media Independent Interface, connecting MAC and PHY). Exact time stamp has to be taken for every emission and reception of relevant PTP messages (i.e. Sync and Delay_Req). Implementiation without HW support: Time stamps taken by SW, at the entry/exit point of the interrupt service routine serving the MAC controller or at the application layer Provide Boundary Clocks in switches (and routers) switch has its own clock which is synchronized with the master plays the slave role at one port and the master role on all remaining ports Use statistical mehtods to reduce jitter filtering, averaging,... such methods slower the convergence ZHW / H. Weibel, Emedded World / 28

29 Implementation Statistical Methods Even with HW assistance, some fluctuations can still be observed quantization effects due to time stamp resolution jitter in the data path (PHY chips, eventually hubs) oscillator instabilities Stochastic fluctuations may be removed by statistical methods filtering and averaging algorithms long-term averaging requires a reasonable oscillator stability If a topology change occurs (e.g. fast reconfiguration in ring configuration) filtering and averaging slower the convergence if reconfiguration can reliably detected, filtering and and averaging should be bypassed to accelerat convergence Systematic effects remain e.g. imperfect symmetry ZHW / H. Weibel, Emedded World / 29

30 Implementation ZHW s Eval Kit as an Example Application PTP Protocol Engine Port Interface TCP UDP Packets TSU Interface Time Stamps CLK Interface Drift Offset Time IP MAC TSU Clock PPS PHY PHY PHY OSC Network Interface PC/104 Board RX TX ZHW / H. Weibel, Emedded World / 30

31 Implementation A typical IEEE 1588 enabled Network Interface Application Port Interface PTP Protocol Engine TSU Interface CLK Interface TCP UDP IP Packets Driver MAC MDIO Time Stamps Drift Offset Time OSC MII Clock PPS TSU PHY timed I/O Data ZHW / H. Weibel, Emedded World / 31

32 Implementation Hardware Assistance - Overview Clock Time t n+1 + t n Increment 1 MII PTP Event Frame Detector Time Stamp Snapshot Time stampers for PTP frames - one for TX - one for RX 2 Input Time Stamp Time stampers for ext. events k Output X Compare Time triggered outputs m Registers ZHW / H. Weibel, Emedded World / 32

33 Implementation Hardware Assistance Clock Design Details k 0 s ns fractions of ns t n Overflow ns fractions of ns Increment A s ns fractions of ns t n+1 The nominal increment is choosen according to the nominal oscillator frequency The drift is compensated by slightly increasing od decreasing the increment ZHW / H. Weibel, Emedded World / 33

34 Synchronization via Hub Start-up Period ZHW / H. Weibel, Emedded World / 34

Synchronization via Hub Accuracy under stable Conditions Values: 1 000

35 Synchronization via Hub Accuracy under stable Conditions Values: Max: Min: Mean: 80ns -120ns 4ns ZHW / H. Weibel, Emedded World / 35

36 Performance Deviation of two synchronized Clocks Offset between Master and Slave + / - 60 ns Std deviation: 15ns Hirschmann Electronics ZHW / H. Weibel, Emedded World / 36

37 IEEE 1588 Standard Status and Future Standard was approved 12 th of September 2002 and published in Nov 2002 IEC has adopted the standard under the label IEC in 2004 Application of IEEE 1588 was announced by different standards organizations and interest groups First commercial IEEE 1588 enabled products are on the market On a plug fest, several implementations have proved interoperability Components with integrated HW assistance were anounced or are available ERTEC from Siemens netx from Hilscher XScale network processor from Intel hynet32xs from Hyperstone Increasing interest in new application areas A standard revision working group has been established to elaborate enhancements and improvements to meet new requirements ZHW / H. Weibel, Emedded World / 37

38 Next Version of the IEEE 1588 Standard Proposed Enhancements Resolution of known errors Conformance enhancements Enhancements for increased resolution and accuracy, i.e. shorter sync interval; higher time stamp resolution Increased system management capability, i.e. SNMP support Mapping to DeviceNet Annex D modifications for variable Ethernet headers Prevention of error accumulation in cascaded topologies, i.e. transparent clock Ethernet layer 2 mapping and short sync message format Extensions to enable implementation of redundant systems Extension mechanism, i.e. uniform way of extending fields/messages ZHW / H. Weibel, Emedded World / 38

39 Many thanks for your attention! Prof. H. Weibel Zurich University of Applied Sciences Institute of Embedded Systems ZHW / H. Weibel, Emedded World / 39

Technology Update on IEEE 1588: The Second Edition of the High Precision Clock Synchronization Protocol

Technology Update on IEEE 1588: The Second Edition of the High Precision Clock Synchronization Protocol Prof. Hans Weibel Zurich University of Applied Sciences Institute of Embedded Systems (InES) Technikumstrasse