Raggedstone5 User Manual. Issue 1.1. Enterpoint Ltd. Raggedstone5 Manual Issue

Transcription

1 1 Raggedstone5 User Manual Issue 1.1

2 2 Kit Contents You should receive the following items with your Raggedstone 5 development kit: 1 - Raggedstone5 Board 2-4 Digit, 7 Segment LED display (fitted) 3 PCI mounting bracket You will also need a programming cable e.g. Enterpoint's PROG3 USB Programming cable.

3 3 Contents Kit Contents 2 Foreword 4 Trademarks 4 INTRODUCTION 5 RAGGEDSTONE5 BOARD 6 GETTING STARTED 7 SELECTING THE FPGA BANK VOLTAGES. 8 PROGRAMMING RAGGEDSTONE5 9 RAGGEDSTONE FEATURES 11 POWER INPUTS AND PICKUPS 11 POWER REGULATORS 12 DIL HEADERS 13 SIL HEADERS 15 CLOCK MODULE HEADER 15 7-SEGMENT DISPLAY HEADER 15 FPGA 17 OSCILLATOR 17 LEDS 18 ANALOG INPUTS AND INTERNAL TEMPERATURE SENSOR 19 USB 21 PUSH BUTTON SWITCHES 22 BATTERY BACKUP 23 DDR3 MEMORY 24 SATA 26 PCIE 27 SERIAL EEPROM 28 SPI FLASH 28 THERMAL CONSIDERATIONS 29 MECHANICAL 30 Medical and Safety Critical Use 31 Warranty 31 Support 31

4 4 Foreword PLEASE READ THIS ENTIRE MANUAL BEFORE PLUGGING IN OR POWERING UP YOUR RAGGEDSTONE5 BOARD. PLEASE TAKE SPECIAL NOTE OF THE WARNINGS WITHIN THIS MANUAL. Trademarks Artix, ISE, EDK, Webpack, Xilinx are the registered trademarks of Xilinx Inc, San Jose, California, US. Raggedstone5 is a trademark of Enterpoint Ltd. Figure 1 Raggedstone5 Board

5 5 INTRODUCTION Welcome to your Raggedstone5 board. Raggedstone5 is Enterpoint s Artix-7 PCIE FPGA development board, a member of the very popular Raggedstone series of FPGA development boards. The aim of this manual is to assist in using the main features of Raggedstone5. There are features that are beyond the scope of the manual. Should you need to use these features then please support@enterpoint.co.uk for detailed instructions. Raggedstone5 comes in a single variant based on an XC7A200T-2FBG676C Artix- 7. Should you need a more powerful or industrial or automotive grade FPGA fitted please contact Enterpoint sales for a quote. Artix-7 200T is supported by the free Webpack edition of the Xilinx ISE/Vivado tools. Raggedstone5 is supported by a wide range of add-on modules. Some examples of these include: ADC 7927 MODULE LED DOT MATRIX MODULE BUTTONS/SWITCHES/SATA/MEMORY MODULE RS232 AND RS485 HEADER MODULES DP83816 ETHERNET MODULE SD CARD MODULE DDR2 MODULE IDE/5V TOLERANT CPLD MODULE USB MODULE D/A CONVERTER MODULE ADV70202 MODULE LTC2248 ADC MODULE MICTOR CONNECTOR MODULE IDT5V19EE901 CLOCK MODULE OPTOISOLATOR MODULE NAND FLASH MODULE OVM 7690 CAMERA MODULE KSZ9021RLGIGABIT PHY MODULE We can also offer custom DIL Header modules should you require a function not covered by our current range of modules. Typical turn around for this service is 6-8 weeks depending upon quantity ordered and availability of components.

6 6 RAGGEDSTONE5 BOARD Figure 2 Raggedstone5 MAIN FEATURES

7 7 GETTING STARTED Your Raggedstone5 will be supplied with a default setting of jumpers fitted. (1) Fit the LED 7 segment display into its connector (may already be fitted), (2) Either connect the Raggedstone5 board to a powered PCIe connector, or provide 12v via the disk drive connector (top right) or plug in a 12v power supply using the 2.1mm Jack socket. (3) Fit an oscillator into the oscillator socket if required (may already be fitted). (4) Switch on your power source.

8 8 SELECTING THE FPGA BANK VOLTAGES. The Bank Voltage for the user I/O pins of the Artix-7 on Raggedstone5 can be set to either 3.3V or 2.5V using a 2mm jumper on the 8-pin header J13. When choosing the Bank voltage be aware that the Artix-7 has a maximum IO input voltage of 0.5V above the selected Bank VCCO Voltage. Alternatively a user-generated Bank IO voltage could be introduced on pin B2 of J13. There is a 0V reference on pins A4 and B4 of J13 for this purpose. If you choose to use this option please refer to the Artix-7 user guide from to check the allowed IO voltage range for the FPGA. Also be aware that there is no fuse protecting the Raggedstone5 circuitry from your power source. Raggedstone5 IO Bank Voltage Header Figure 3 Place a jumper to link pins B1 and B2 if you require an IO voltage of 3.3V, or between B2 and A2 if you require 2.5V. Figure 4 Detail of J13

9 9 PROGRAMMING RAGGEDSTONE5 The programming of the FPGA and SPI Flash on Raggedstone5 is achieved using the JTAG connection. Principally it is anticipated that a JTAG connection will be used in conjunction with Xilinx ISE software although other alternatives do exist. You will need to use ISE version 14.1 or later, or Vivado to configure Artix-7. You will need ISE 14.3 or later to build and implement a design in Artix-7. There is a single JTAG chain on Raggedstone5. The JTAG chain allows the programming of the Artix-7 and the SPI Flash device. Raggedstone5 JTAG connector Figure 5 The JTAG connector J3 has a layout as follows: Top edge of board 3V3 TMS TCK TDO TDI NC NC GND GND GND GND GND GND GND Using impact Boundary Scan the JTAG chain appears like this: Figure 6 Artix-7 detected by impact

10 10 1. Programming the FPGA JTAG programming of the Artix-7 FPGA is volatile and the FPGA will lose its configuration every time the board power is cycled. For sustained use of an FPGA design programming the design into the Flash memory is recommended (see 2 and 3 below). Direct JTAG programming using.bit files is useful for fast, temporary programming during development of FPGA programs. Right click the icon representing the Artix-7 FPGA and choose Assign New Configuration File. Navigate to your.bit file and choose OPEN. The next dialogue box will offer to add a flash memory and you should decline. Right click the icon representing the Artix-7 FPGA and choose Program. Click OK. The Artix-7 will program. This process is very quick (typically a few seconds) 2. Programming the SPI flash memory. Once the SPI Flash memory has been programmed, the Artix-7 device will automatically load from the Flash memory at power up. Generation of suitable Flash memory files (.mcs) can be achieved using ISE impact s Prom File Formatter. Right click on the icon representing the Artix-7 and choose Add SPI/BPI Flash Navigate to your programming file (.mcs) and click OPEN. Use the next dialogue box to select SPI flash and W28Q128BV. Data width should be set to 4. The flash memory should appear as shown below. Figure 7 Artix-7 with SPI flash added Right click on the icon representing the flash memory and choose Program to load your program into the device. It is recommended that options to Verify and Erase before programming are chosen. Otherwise all defaults can be accepted. The programming operation will take some time (at least 3 or 4 minutes). 3. Configuration over USB. In theory it should be possible to reconfigure the Raggdstone5 FPGA using the USB connection. However Enterpoint Ltd do not yet support this system. The 2mm Jumper header J1 has been provided for this option. Four 2mm jumpers are required to route the JTAG signals to the USB device. The jumpers should link A1 to B1, A2 to B2 and so on. Figure 8 Detail of J1

11 11 POWER INPUTS AND PICK-UPS RAGGEDSTONE FEATURES Raggedstone5 is powered either from the PCIe edge connector, from a 12V power supply via the 2.5mm DC jack socket J7, or from the Disk Drive connector J14. The 12V input to Raggedstone5 is regulated by 7 regulators for the supplies to the FPGA and Peripherals. These regulators produce 0.675V, 1V, 1.2V, 1.35V, 1.8V, 2.5V and 3.3V and can be tested on header pins as shown in fig.3 below. On Raggedstone5 there are 34 header pins with 3.3V and 0V available on each side of the board for users to access power for their own add-on circuitry. These pins are arranged on a 0.1inch grid to enable users to plug in their own stripboard designs. Figure 9 Raggedstone5 Power Supply Features WARNING THE REGULATORS MAY BECOME HOT IN NORMAL OPERATION ALONG WITH THE BOARDS THERMAL RELIEF. PLEASE DO NOT TOUCH OR PLACE HIGHLY FLAMABLE MATERIALS NEAR THESE DEVICES WHILST THE RAGGEDSTONE5 BOARD IS IN OPERATION.

12 12 POWER REGULATORS Raggedstone5 has 7 power regulators which are arranged to comply with the power sequencing requirements for Artix-7: 1.A Micrel MIC26950 (U4) provides 3.3V at a maximum of 12A for the FPGA IO and to supply other regulators. 2.A Micrel (U19) provides a maximum of 7A at 2.5V for the FPGA IO. 3. A Texas Instruments TPS54240 (U17) provides a maximum of 2A at 1.8V for the FPGA VCCAUX. 4. A Micrel (U1) provides a maximum of 7A at 1.35V for the DDR3 and associated FPGA IO. 5. A Texas Instruments TPS54240 (U18) provides a maximum of 2A at 1.2V for the FPGA MGAVTT. 6. A Texas Instruments TPS53355 (U2) provides a maximum of 30A at 1V for the FPGA core. 7.A Texas Instruments TPS52100 (U3) push-pull regulator sources/sinks a maximum of 3A at 0.675V for the DDR3 and associated FPGA IO. The maximum current that can be delivered into Raggedstone5 from the PCIE connector has been limited by a resettable fuse to a maximum current of 2.6A at 12V. This limit should be considered when adding user circuitry onto the header pins. If more current is drawn the resettable fuse will cut the supply to the board, if this happens the power supply must be switched off and time given for the fuse to reset, which occurs when the fuse has cooled and reconnected its internal contacts. This typically takes 1-2 seconds. A 7A fast blow fuse (replacement fuse Littlefuse R154007) limits the current from the Jack socket or the Disk drive socket to 7A. Do not connect these two options simultaneously. Figure 10 Raggedstone5 Power Regulators

13 13 DIL HEADERS The DIL Headers provide a simple mechanical and electrical interface for add-on modules. The connectors on this header are on a 0.1inch, 2.54mm, pitch and allow either custom modules or strip board to be fitted (mating connector Precidip (eg ) or Mill-max 410 series or Samtec or TOBY HTS series with mm diameter pins). The headers have a row of permanent positive power sockets (3.3V) to the left of JL2 and JR2 and a row of permanent GND (0V) sockets to the right of the JL1 and JR1. Voltages outside the range 0V to 3.3V must not be applied to the DIL headers. The Artix-7 has an absolute maximum IO input voltage of (VCCO +0.5V). The connections between the DIL the headers and the FPGA are shown below: LEFT DIL HEADER RIGHT DIL HEADER JL1 JL2 PIN JR1 JR2 J25 0V 3.3V K22 1 Y8 0V 3.3V AB6 J26 0V 3.3V K23 2 AA8 0V 3.3V AC6 J23 0V 3.3V G20 3 Y7 0V 3.3V W3 H23 0V 3.3V G21 4 AA7 0V 3.3V Y3 G25 0V 3.3V H26 5 AD5 0V 3.3V AD1 F25 0V 3.3V G26 6 AE5 0V 3.3V AE1 K20 0V 3.3V J19 7 AE3 0V 3.3V Y6 J20 0V 3.3V H19 8 AF3 0V 3.3V Y5 G24 0V 3.3V K16 9 W5 0V 3.3V AC3 F24 0V 3.3V K17 10 W4 0V 3.3V AD3 F23 0V 3.3V M14 11 AC4 0V 3.3V AA5 E23 0V 3.3V L14 12 AD4 0V 3.3V AB5 E25 0V 3.3V H21 13 AB2 0V 3.3V V6 D25 0V 3.3V H22 14 AC2 0V 3.3V W6 K15 0V 3.3V M15 15 Y2 0V 3.3V V8 J16 0V 3.3V L15 16 Y1 0V 3.3V W8 J18 0V 3.3V K21 17 AB1 0V 3.3V V3 H18 0V 3.3V J21 18 AC1 0V 3.3V V2 J14 0V 3.3V J24 19 V1 0V 3.3V U7 J15 0V 3.3V H24 20 W1 0V 3.3V V7 G22 0V 3.3V M16 21 G17 0V 3.3V E17 F22 0V 3.3V M17 22 F17 0V 3.3V E18 E26 0V 3.3V L17 23 F18 0V 3.3V G15 D26 0V 3.3V L18 24 F19 0V 3.3V F15 C22 0V 3.3V D23 25 E16 0V 3.3V D18 C23 0V 3.3V D24 26 D16 0V 3.3V C18 C24 0V 3.3V C26 27 H14 0V 3.3V A17 B24 0V 3.3V B26 28 H15 0V 3.3V A18 A23 0V 3.3V B25 29 H16 0V 3.3V D19 A24 0V 3.3V A25 30 G16 0V 3.3V C19 E21 0V 3.3V B22 31 C17 0V 3.3V E20 D21 0V 3.3V A22 32 B17 0V 3.3V D20 C21 0V 3.3V B20 33 B19 0V 3.3V G19 B21 0V 3.3V A20 34 A19 0V 3.3V F20

14 14 The signals on the DIL headers are arranged in LVDS pairs and routed such that the trace lengths approximately match and skew is minimised within pair. Adjacent LVDS_P and LVDS_N form the matched pair at the DIL Header and the Artix-7 FPGA. For example FPGA pins J25 and J26 form one pair (JL1 pins 1 and 2). All LVDS pairs can be used as general inputs/outputs from the Artix-7. Figure 11 Raggedstone5 DIL Headers

15 15 SIL HEADERS There are 4 SIL headers on Raggedstone5. They are arranged as 2 pairs. J9 and J11 form the Clock Module header and have 5 pins each. The two 8-pin SIL headers are usually used to support the LTC-4627JR 4-digit 7-segment display (U9), however the 7 segment display can be removed to make these pins available to the user. The FPGA Bank IO voltage for these headers is fixed at 3.3V. Voltages outside the range 0V to 3.3V must not be applied to the SIL headers. The Artix-7 has an absolute maximum IO input voltage of 0.5V above the Bank IO Voltage. 1. CLOCK MODULE HEADER These header pins are designed to allow the Enterpoint Clock module to be fitted. This module is fitted with an ICS MHZ, Crystal Oscillator-To-Differential LVDS Frequency Synthesizer device. If this module is not fitted the header pins are available to the user. J11 has a permanent positive power pin (3.3V) at the top position. J9 has a GND (0V) connection at the top position. The connections to the FPGA (BANK1) are shown below: J9 J11 PIN1 0V PIN1 3.3V PIN2 N21 PIN2 L22 PIN3 N22 PIN3 M20 PIN4 P21 PIN4 L20 PIN5 P20 PIN5 M19 The connections to J9 are LVDS pairs connecting to Global Clock inputs on the FPGA. On J11 connections to M20 and L20 are an LVDS pair. The Connections to L22 and M19 are to general purpose IO pins. The horizontal distance between J9 and J11 is 0.6inch (15.25mm) SEGMENT DISPLAY HEADER The two 8-pin headers which form the 7-segment display holder U9 have 14 connections to the FPGA. Of these 14 connections 8 have series 470ohm resistors, which are normally used as currentlimiting resistors for the 7 segment display. This should be taken into account if this header is used for other purposes. The connections between U9 and the FPGA are shown below: PIN16 R23* PIN15 R25* PIN 14 P23* PIN13 N26* PIN12 M25 PIN11 N17* PIN10 N/C PIN9 N/C PIN1 R18 PIN2 R17 PIN3 N18* PIN4 R16 PIN5 N19* PIN6 M24 PIN7 N16* PIN8 M22 *These pins connect to the FPGA via a series 470 ohm resistor. The vertical distance between the upper and lower pins of U9 is 0.4inch (10.2mm).

16 16 Figure 12 Raggedstone5 SIL Headers

17 17 FPGA Raggedstone5 supports Artix-7 devices in the FB676 package. Raggedstone5 is normally available with the XC7A200T-2FB676C fitted, which features: 215,360 logic cells 740 DSP slices 13,140Kb Block RAM 8 High Speed Transceivers PCI Express support up to x4 Gen 2 4 Hard IP memory controllers Should you have an application that needs bigger devices, industrial or faster speed grades please contact sales for a quote at boardsales@enterpoint.co.uk OSCILLATORS The oscillator socket U16 on Raggedstone5 supports 3.3V, 8-pin DIL outline, crystal oscillators. This clock signal (USER_CLK)is routed to pin M21 of the FPGA which is a Global Clock input. The Raggedstone5 board can alternatively be fitted with a fixed frequency 50MHz ASEM oscillator X1, which connects to the same pin of the FPGA. Please contact Enterpoint Sales for this option on boardsales@enterpoint.co.uk. There are also two other 50MHz ASEM oscillators connected to the FPGA. X4 connects to pin AA3, which is a Global Clock pin. X2 connects to pin P16 (EMCCMK) and is used to determine the configuration rate. The frequency of X2 is chosen so that in conjunction with the Quad SPI Flash the Raggedstone5 board will configure within the time required for the PCIe interface to be recognised by a host system. X3 is a 150MHz low jitter oscillator dedicated to the SATA interface. The Artix-7 200T has 10 Clock Management Tiles including Digital Clock Multipliers (DCMs) to produce multiples, divisions and phases of clock signals. Please consult the Artix-7 datasheet available from the Xilinx website at if multiple clock signals are required. Figure 13 Raggedstone5 FPGA and Oscillators

18 18 LEDs On Raggedstone5 there are 5 LEDS. LED1 (Green) is situated on the top left corner of the board and indicates the presence of the 3.3v power rail. It is not available for other uses. User LEDs 2 to 5 are situated the top of the board immediately above JR1, and are connected to the FPGA as indicated below: LED COLOUR FPGA PIN LED2 RED AF5 LED3 YELLOW AF4 LED4 GREEN AF2 LED5 BLUE AE2 The Cathode of each LED is connected to 0V. The FPGA signal must be asserted HIGH for an LED to be lit. Figure 14 Raggedstone5 LEDs

19 19 ANALOG INPUTS AND INTERNAL TEMPERATURE SENSOR Figure 15 Raggedstone5 Analog inputs The Artix-7 device on Raggedstone5 has a single dedicated analog input pair, VP (pin N12) and VN (pin P11), which are routed to a 3-pin 2mm pitch header J15. The Artix-7 has two internal 12 bit Analog to digital converters which can be configured to measure the voltage on thevp/vn pins or to monitor its own internal supply voltages (VCCINT, VCCAUX and VCCBRAM). It can also monitor the temperature of the FPGA die via its internal temperature sensor. Information on the Artix-7 XADC and details concerning its configuration can be found in UG480 from Figure 16 Raggedstone5 Detail of J15 The maximum input range to the ADCs is 0V to 1V in unipolar mode. In bipolar mode the input range is +0.5 to -0.5V. The analog inputs of the ADC use a differential sampling scheme to reduce the effects of common-mode noise signals. This common-mode rejection improves the ADC performance in noisy digital environments. The XC7A200T-2FB676C device has 16 other analog input pairs, 8 of which are available on the left hand side DIL header pins of Raggedstone5. These FPGA inputs pins are normal digital IOs unless they are specifically configured as analog inputs. Information about how this is achieved can be found in UG480 from These optional analog inputs have the same input voltage restrictions as the dedicated analog pair VN/VP.

20 20 The pin connections for these 8 optional analog input pairs are shown below: DIL HEADER PIN ADC FUNCTION FPGA PIN JL1_15 AD0_P K15 JL1_16 AD0_N J16 JL1_19 AD8_P J14 JL1_20 AD8_N J15 JL2_9 AD1_P K16 JL2_10 AD1_N K17 JL2_15 AD9_P M15 JL2_16 AD9_N L15 JL2_7 AD2_P J19 JL2_8 AD2_N H19 JL2_23 AD10_P L17 JL2_24 AD10_N L18 JL1_7 AD3_P K20 JL1_8 AD3_N J20 JL1_17 AD11_P J18 JL1_18 AD11_N H18

21 21 USB Figure 17 Raggedstone5 USB The USB interface on the Raggedstone5 is achieved using an FT232R USB to serial UART interface. The datasheet and drivers for this device are available from When appropriate drivers are installed the Raggedstone5 USB port should be detected as a serial port. Alternative data optimised drivers are also available from FTDI. The FT232R is connected to the Artix-7 and provided a simple UART, or other converter, is implemented then the data sent over the USB serial port can be used either as control and/or data information. This allows a host computer to act in a number of ways including system control and data storage functions. The connections between the USB device and the FPGA are shown below: FT232R FPGA PIN CTS# R22 DCD# R21 DSR# R20 R# R26 RTS# T22 DTR# T24 TXD T25 RXD T23

22 22 PUSH BUTTON SWITCHES Raggedstone5 has two tactile push-button switches. To use these switches it is necessary to set the IO pins connected to the switches to have a pull up resistor setting in the constraints file. Any switch pressed, or made, will then give a LOW signal at the FPGA, otherwise a HIGH is seen. The two push button switches are connected to the following IO pins. These switches are connected to IO on Bank 34, which is also connected to one of the DDR3 devices and has an IO Voltage of 1.35V. The IO Standard in the constraints file needs to reflect this. SWITCH SIGNAL FPGA PIN DESIGNATOR NAME SW1 PB2 U2 SW2 PB1 U1 Figure 18 Raggedstone5 Push Button Switches

23 23 BATTERY BACKUP The Raggedstone5 has a battery holder which is available to provide battery backup to the FPGA. It is connected to the Artix-7 on pin G14. The battery holder accepts a 1.5V Lithium battery size LR44 or equivalent. The battery holder is situated on the front right of the PCB. Figure 19 Raggedstone5 Battery Holder

24 24 DDR3 Raggedstone5 has four 4GBIT DDR3 Micron MT41K256M16HA-125:E devices as standard. These devices are organised as two 32 bit wide memory interfaces with a common address busses and are supported by the hard core memory controllers that are in the Artix-7 FPGA. To add this core to your design the COREGEN tool, part of the ISE (or Vivado) suite, will generate implementation templates in VHDL or Verilog for the configuration that you want to use. More details on the memory controller can be found in the user guide For OEM applications we can fit bigger DDR3 parts subject to limitations of the memory controller. Each pair of DDR3 devices has 16 address lines and 32 data lines to address all the available memory, which can be accessed at speeds of 1.25ns. More details of the DDR3 can be found in The first DDR3 pair (U14 and U15) has the following connections to the FPGA: DDR3 DDR3 DDR3 FPGA PIN FPGA PIN FUNCTION FUNCTION FUNCTION FPGA PIN DDR3_A0 N1 DDR3_RST_N F5 DDR3_DQ20 F7 DDR3_A1 K2 DDR3_CKE R1 DDR3_DQ21 H6 DDR3_A2 L3 DDR3_CLK_N L4 DDR3_DQ22 D6 DDR3_A3 J1 DDR3_CLK_P M4 DDR3_DQ23 H9 DDR3_A4 K1 DDR3_DQ0 D5 DDR3_DQ24 K7 DDR3_A5 N8 DDR3_DQ1 D4 DDR3_DQ25 F4 DDR3_A6 M6 DDR3_DQ2 B4 DDR3_DQ26 K8 DDR3_A7 N6 DDR3_DQ3 F3 DDR3_DQ27 J5 DDR3_A8 N7 DDR3_DQ4 C3 DDR3_DQ28 K6 DDR3_A9 K5 DDR3_DQ5 E5 DDR3_DQ29 G4 DDR3_A10 L5 DDR3_DQ6 A4 DDR3_DQ30 L8 DDR3_A11 L7 DDR3_DQ7 D3 DDR3_DQ31 G5 DDR3_A12 M7 DDR3_DQ8 E1 DDR3_DM0 C4 DDR3_A13 J3 DDR3_DQ9 D1 DDR3_DM1 C2 DDR3_A14 K3 DDR3_DQ10 F2 DDR3_DM2 E6 DDR3_A15 P4 DDR3_DQ11 A3 DDR3_DM3 J6 DDR3_BA0 H1 DDR3_DQ12 G1 DDR3_DQS0_P B5 DDR3_BA1 H2 DDR3_DQ13 A2 DDR3_DQS0_N A5 DDR3_BA2 M1 DDR3_DQ14 G2 DDR3_DQS1_P C1 DDR3_ODT P1 DDR3_DQ15 E2 DDR3_DQS1_N B1 DDR3_CS_N N2 DDR3_DQ16 G6 DDR3_DQS2_P H7 DDR3_RAS_N M2 DDR3_DQ17 H8 DDR3_DQS2_N G7 DDR3_WE_N N3 DDR3_DQ18 F8 DDR3_DQS3_P J4 DDR3_CAS_N L2 DDR3_DQ19 G8 DDR3_DQS3_N H4 FPGA Pins R3 and P3 are reserved for DDR_SYS_CLK. The signals shown shaded in yellow are terminated using suitable arrangements of resistors.

25 25 The second DDR3 pair (U6 and U7) has the following connections to the FPGA: DDR3 DDR3 DDR3 FPGA PIN FPGA PIN FUNCTION FUNCTION FUNCTION FPGA PIN DDR3_A0 AE22 DDR3_RST_N V22 DDR3_DQ20 W20 DDR3_A1 AF20 DDR3_CKE AC18 DDR3_DQ21 T19 DDR3_A2 AF19 DDR3_CLK_N AF25 DDR3_DQ22 W21 DDR3_A3 AE21 DDR3_CLK_P AF24 DDR3_DQ23 V19 DDR3_A4 AD21 DDR3_DQ0 U25 DDR3_DQ24 T14 DDR3_A5 W16 DDR3_DQ1 V26 DDR3_DQ25 V16 DDR3_A6 AD23 DDR3_DQ2 W26 DDR3_DQ26 U15 DDR3_A7 AF23 DDR3_DQ3 W25 DDR3_DQ27 U16 DDR3_A8 AE23 DDR3_DQ4 Y26 DDR3_DQ28 T15 DDR3_A9 AD26 DDR3_DQ5 U26 DDR3_DQ29 V14 DDR3_A10 AD25 DDR3_DQ6 AA25 DDR3_DQ30 U14 DDR3_A11 AC23 DDR3_DQ7 V24 DDR3_DQ31 V17 DDR3_A12 AC22 DDR3_DQ8 U22 DDR3_DM0 U25 DDR3_A13 AE26 DDR3_DQ9 AA23 DDR3_DM1 AA24 DDR3_A14 AE25 DDR3_DQ10 V23 DDR3_DM2 U21 DDR3_A15 AE18 DDR3_DQ11 AA22 DDR3_DM3 V18 DDR3_BA0 AE20 DDR3_DQ12 W23 DDR3_DQS0_P AB26 DDR3_BA1 AD20 DDR3_DQ13 Y22 DDR3_DQS0_N AC26 DDR3_BA2 AF22 DDR3_DQ14 Y23 DDR3_DQS1_P AB24 DDR3_ODT AD18 DDR3_DQ15 AB25 DDR3_DQS1_N AC24 DDR3_CS_N AB20 DDR3_DQ16 Y20 DDR3_DQS2_P T20 DDR3_RAS_N AB21 DDR3_DQ17 U19 DDR3_DQS2_N U20 DDR3_WE_N AA20 DDR3_DQ18 Y21 DDR3_DQS3_P T17 DDR3_CAS_N AC21 DDR3_DQ19 V21 DDR3_DQS3_N T18 FPGA PinsAA19 and AB19 are reserved for DDR_SYS_CLK. The signals shown shaded in yellow are terminated using suitable arrangements of resistors. Figure 20 Raggedstone5 DDR3

26 26 SATA Raggedstone5 has 3 SATA connectors which are connected to the MGT interface of the Artix-7. The SATA clock is provided by an Abracom DSC MHz low jitter oscillator. The connections between the SATA Clock, the SATA connectors and the FPGA are shown below (omitting series capacitors): Sata1 Connector J8 pin FPGA PIN Sata2 Connector J10 Pin FPGA PIN Sata3 Connector J12 Pin FPGA PIN J8 PIN 2 AE9 J10 PIN 2 AC10 J12 PIN 2 AC8 J8 PIN 3 AF9 J10 PIN 3 AD10 J12 PIN 3 AD8 J8 PIN 5 AF13 J10PIN 5 AC12 J12 PIN 5 AC14 J8 PIN 6 AE13 J10 PIN 6 AD12 J12 PIN 6 AD14 CLOCK+ AA13 CLOCK- AB13 Figure 21 Raggedstone5 SATA

27 27 PCIe Edge Connector The Raggedstone5 has a x4 PCIe Interface. The pin out of the Artix-7 FPGA has been chosen such that the PCI interface follows the pinout for the Xilinx Artix-7 hard core for PCIe which can be generated automatically by the Xilinx Core Generator. The connections between the PCIe connector and the FPGA are shown below. SIGNAL PCIE CONNECTOR FPGA PIN NAME PIN PCIE_CLK_P A13 F11 PCIE_CLK_N A14 E11 PCIE_TX0_P A16 D10 PCIE_TX0_N A17 C10 PCIE_RX0_P B14 D12 PCIE_RX0_N B15 C12 PCIE_TX1_P A21 B9 PCIE_TX1_N A22 A9 PCIE_RX1_P B19 B13 PCIE_RX1_N B20 A13 PCIE_TX2_P A25 D8 PCIE_TX2_N A26 C8 PCIE_RX2_P B23 D14 PCIE_RX2_N B24 C14 PCIE_TX3_P A29 B7 PCIE_TX3_N A30 A7 PCIE_RX3_P B27 B11 PCIE_RX3_N B28 A11 PCIE_PRESENT#1 A1 J5 PIN 3 PCIE_PRESENT#2 B17 J5 PIN2 PCIE_PRESENT#4 B31 J5 PIN 1 PCIE presence signals 1, 2 and 4 are routed to the 2mm pitch 3 pin jumper header J5. If the Raggedstone5 board is plugged into an open-ended x1 PCIe socket a jumper should be fitted to J5 to link pins 2 and 3. If the board is plugged into a x4 PCIe socket a jumper should be fitted to J5 to link pins 1 and 2. PIN 1 PIN 3 Figure 22 Detail of J5

28 28 Serial EEPROM Raggedstone5 has a 16K Two-Wire Atmel AT24C16BY6 EEPROM device (U10) which uses a simple parallel address and single serial data line and clock. There is also a write protect line which can be used to electronically safeguard the information contained in the device The 3 address lines are permanently connected to 0V. It can run at speeds up to 400 khz. This serial memory has 2048 words of 8 bits and employs a byte or page programming system. The connections between the EEPROM and the FPGA are shown below: SPI Flash Memory EEPROM SIGNAL SDA SCL WP FPGA PIN K25 K26 M26 The Winbond W28Q128BV Quad SPI flash memory device (U8) configures the FPGA when it is powered providing a suitable bitstream is programmed into the device. The W28Q128BV has a capacity of 128Mbits with a single configuration bitstream for Raggedstone5 taking 77.9Mbits. Any remaining space can be used for an alternative configuration or code and data storage. After configuration the SPI Flash can be accessed via the following pins of the FPGA: W28Q128BV FUNCTION FPGA PIN W28Q128BV PIN CCLK H13 6 D/MISO0 R14 5 Q/MISO1 R15 2 WP#/MISO2 P14 3 HOLD/MISO3 N14 7 CS# P18 1 Figure 23 Raggedstone5 EEPROM and SPI Flash

29 29 Thermal considerations Depending upon the design implemented in the FPGA, it may dissipate a significant amount of heat. There are two resources on Raggedstone5 to aid heat dissipation: 1. Two holes have been provided so that a standard heatsink can be fitted over the FPGA. They are designed to accept a 37.5mm square Northbridge heatsink with push fit pegs (a typical fan to fit this type of heatsink is Enzotech SLF-1). The diagonal distance between these 3mm diameter holes is 59.1mm. A 23mm high heatsink to fit Raggedstone5 is available from the Enterpoint online shop. 2. A standard 3 pin motherboard fan connector (J6) with 12V power has been provided so that a fan can be placed near the board. The centre pin of J6 is positive 12V, Pin 1 is 0V (to the right of pin2) and Pin 3 can be used for fan speed monitoring by the Artix-7. The fan speed output pulses are routed through an optocoupler Q1 to pin AF18 of the FPGA. Figure 24 Raggedstone5 Thermal Management Resources

30 30 Mechanical information Figure 25 Raggedstone5 Mechanical Information (CAD Image) Figure26 Raggedstone5 Edge View (3d model) The maximum height of the components on Raggedstone5 is determined by the tallest component (Jack socket J7) which is approximately 11mm. This is less than the width of the single slot PC mounting bracket supplied with Raggedstone5. This does not include the height of any heatsink or fan. The PCB is 1.6mm thick. All dimensions are shown in millimetres. If you need any further mechanical information please contact us. Contact information is shown on the last page of this manual.

31 31 Medical and Safety Critical Use Raggedstone5 boards are not authorised for the use in, or use in the design of, medical or other safety critical systems without the express written person of the Board of Enterpoint. If such use is allowed the said use will be entirely the responsibility of the user. Enterpoint Ltd will accept no liability for any failure or defect of the Raggedstone5 board, or its design, when it is used in any medical or safety critical application. Warranty Raggedstone5 comes with a 90 day return to base warranty. Do not attempt to solder connections to the Raggedstone5. Enterpoint reserves the right not to honour a warranty if the failure is due to soldering or other maltreatment of the Raggedstone5 board. Outside warranty Enterpoint offers a fixed price repair or replacement service. We reserve the right not to offer this service where a Raggedstone5 has been maltreated or otherwise deliberately damaged. Please contact support if you need to use this service. Other specialised warranty programs can be offered to users of multiple Enterpoint products. Please contact sales on boardsales@enterpoint.co.uk if you are interested in these types of warranty, Support Enterpoint offers support during normal United Kingdom working hours 9.00am to 5.00pm. Please examine our Raggedstone5 FAQ web page and the contents of this manual before raising a support query. We can be contacted as follows: Telephone (0) support@enterpoint.co.uk