Demo Carrier Board for Industrial Micromodule

Transcription

1 Demo Carrier Board for ndustrial Micromodule Rev 1.0 as of Overview Features The Trenz Electronic TE00 Demo Carrier Board provides lowcost connection and extension to the Trenz Electronic TE000 SpartanE ndustrial Micromodule series. FPGA signals available on header J The TE000 micromodule signals are available on highdensity, surface mount connectors and are routed to the standard headers of the Demo Carrier Board with a differential impedance of 100 ohm. The following ports are available for application demonstration: one Dsub 1 VGA output, two Dsub RS ports, two PS/ ports. A 1 JTAG connector for Xilinx parallel cable, V and USB cable HWUSB is made available for easy attachment Flexible power supply is possible through screw terminals (J7), dedicated DC jack (J8) or optionally USB bus (J1). Figure 1: demo carrier board: top view without TE00 module. and J, each with x 0. mm (100 mil) pitch differential pairs (for highspeed signals) 10 singleended lines (for low / mediumspeed signals) 1 x 1 Pmod or, alternatively, up to x 6 Pmods header connector J with x mm (0 mil) pitch for the direct connection with an Optomotive Cameleon camera head Board power supply via screw terminals, DC jack or optionally industrial USB connector JTAG header compatible with Xilinx parallel cable, V and USB cable HWUSB Small form factor: 11 x 7 mm Figure : demo carrier board: top view with TE00 module. 1

2 Demo Carrier Board for ndustrial Micromodule Figure : assembly diagram. Set the Jumper J6 [TE00] to EXT, and Details connect a V DC supply to either the. To locate jumper and connectors, see mm DCjack J8 [TE00] (center positfigure : assembly diagram. ive) or the DC screw terminals J7 [TE00] (upper positive as hinted by Warning: make sure to install the modthe "+V"). ule only in the way shown in Figure! A quick way to check this is to make sure that the mounting holes on the TE000 micromodule are in line with those on the TE00 Demo Carrier Board. Power Supply There are three ways to supply power to the board: V DC power supply USB bus power supply (optional). V DC power supply Both inputs are protected against polarity inversion by a cross bar diode D1. Screw terminals J7 [TE00] are not populated by default. USB bus power supply (optional) Set the Jumper J6 [TE00] to USB and connect a USB hostpowered cable to the industrial USB receptacle J1 [TE00]. Receptacle J1 [TE00] is not populated by default. For further information, please consult paragraph "USB Port".

3 Demo Carrier Board for ndustrial Micromodule Header Power Pins Power s on the /O mating headers can provide power to external circuits. The following voltages are generated on the micromodule: 1. V (J [TE00]:, ). V (J [TE00]: 1, 1) (J [TE00]:,,, ). For more information on available power ratings, please see "Trenz Electronic TE000 ndustrial Micromodule User Manual". SpartanE/A FPGAs at Speeds Up to 666 Mbps", xapp8.pdf). Application Ports The TE00 Demo Carrier Board provides the following ports ready for FPGAdriven applications or demonstrations: 1 x microsd (socket) 1 x Optomotive camera (male) 1 x 1 Pmod or, alternatively, up to x 6 Pmods x PS/ (female) /O Banks Power Supply Power supply input Vcc for FPGA bank 0 can be connected externally through connector J, s 1 (Vcc0). f bank 0 is not needed, Vcc can be left open. Warning! f the Vcc line is supplied internally by one of the powersupply lines present on the TE000 module, do NOT apply any external voltage. Warning! Spartan /Os are not V tolerant. Applying more than the recommended operating voltages at any, results in a damaged FPGA (see Xilinx Answer AR#116). Singleended lines The demo carrier board has a total of 10 single ended lines routed to header connectors J [TE00] and J [TE00]. These lines can be used for lowspeed and mediumspeed signals. Differential Pairs The demo carrier board has a total of differential signal pairs routed with a differential impedance of 100 ohm to header connectors J [TE00] and J [TE00]. These lines can be used for high speed signaling up to 666 Mbit/s per differential pair (see Xilinx application note XAPP8 "1:7 Deserialization in 1 x RS DCE (female) 1 x RS DTE (male) 1 x VGA (female) Each application port is composed of a hardware interface and the corresponding FPGA core. microsd The FPGA can read and write at bank a microsd card through the microsd socket J1 [TE0] as detailed in Table 1. The microsd socket is provided with a card detection switch (c.d.s.). FPGA DAT _L0N_ R1 CD/DAT _L18P_ P11 CMD _L18N_ N11 VDD CLK GCLK1 V VSS DAT0 _L10P_ R8 DAT1 _L10N_ T8 c.d.s. P_LP_ V1 Table 1: microsd signal details (bank ). Optomotive camera An Optomotive Cameleon camera head

4 Demo Carrier Board for ndustrial Micromodule can be connected to the TE00 Demo Carrier Board through a 0wire ribbon cable inserted on header connector J [TE00] with 1.7 mm (0 mil) pitch as shown in Figure. Figure : Optomotive camera connected to the demo board. Please make sure that the ribbon cable connector is inserted on header connector J [TE00] such that wire 1 (usually the only colormarked wire) is near the bottom part of the board (VGA and RS ports side). For further information about Optomotive technology, please read Trenz Electronic application note "TE000 XPS Reference Designs" (ANTE00001.pdf) Pmod (peripheral module) port(s) One 1 Pmod device or, alternatively, up to two 6 Pmod devices can be connected to a section of header connector J[TE00] as shown in Figure. J [TE00] Pmod odd Pmod even J [TE00] 1 /O /O 1 11 /O /O 1 /O /O 10 7 /O /O 8 6 Figure : Pmod port(s). Table : Pmod out (J [TE00]). Pmod signals are available at bank 0 of the FPGA as detailed in Table. FPGA Pmod 1 odd _L0P_0 B6 Pmod odd _LN_0 D Pmod odd _LN_0 B Pmod odd _LP_0 C Pmod odd Pmod 6 odd Pmod 1 even _L0N_0 A6 Pmod even _LP_0 C Pmod even _LP_0 A Pmod even C Pmod even Pmod 6 even Table : Pmod out (bank 0). Pmod out at connector J [TE00]) is detailed in Table. PS/ Ports The TE00 Demo Carrier Board is equipped with two minidn6 female connectors (J10 and J11) for the connection of serial input devices with PS/ connectors (typically keyboard and

5 Demo Carrier Board for ndustrial Micromodule mouse). PS/ signals are available at bank of the FPGA as detailed in Table. FPGA PS_C1 (port 1 clock) _L1N_ M PS_D1 (port 1 data) _L07P_ N7 PS_C (port clock) _L0P_ R PS_D (port data) _L0N_ T Table : PS/ out (bank ). The TE00 Demo Carrier Board is equipped with an RS DTE (data terminal equipment) serial port implemented with a Dsub male connector J [TE00]. Pin Dir. 1,, 6 internally connected RxDDTE O TxDDTE 7, 8 internally connected not connected Table 7: out of connector [TE00]. RS DCE Port The TE00 Demo Carrier Board is equipped with an RS DCE (data communication equipment) serial port implemented with a Dsub female connector J1 [TE00] as detailed in Table. Pin Dir. 1,, 6 internally connected O TxDDCE RxDDCE 7, 8 internally connected not connected Table : out of connector [TE00]. J1 FPGA TxDDCE _L0N_ P6 RxDDCE _L0P_ R6 RS DTE Port The RS DTE signals are available at bank of the FPGA as detailed in Table 8. FPGA TxDDTE (bank ) V7 RxDDTE _L07N_ P7 Table 8: RS DTE signal details (bank ). VGA Port The RS DCE signals are available at bank of the FPGA as detailed intable 6. Table 6: RS DCE signal details (bank ). J The FPGA can drive a VGA output port through a Dsub 1 male connector. Each RGB channel has a resolution of bits, for an overall color depth of,768 colors per pixel. The VGA signals are available at bank and of the FPGA as detailed in Table. FPGA R0 _LP_ R R1 _LN_ R R _L1P_ P R _L1N_ P1 R _LP_ T G0 _L06N_ V6

6 Demo Carrier Board for ndustrial Micromodule FPGA Pin G1 _L06P_ V 1 G (bank ) U Vref () G _L0P_ U G _L18N_ M TMS B0 _L1N_ M6 B1 _L1P_ M 6 TCK B _L17P_ L6 7 B _L17N_ L 8 TDO B (bank ) U6 /HSYNC _L0P_ N 10 TD /VSYNC _L0N_ N 11 VGA_SCL _LP_ P 1 n.c. VGA_SDA _LN_ P 1 1 n.c. Table : VGA port out (bank and ). Table 10: 1 JTAG connector J. Other Ports USB Port JTAG Port Connector J is a 1 JTAG connector for Xilinx parallel cable, V and USB cable HWUSB. USB data lines of header connector J1[TE00] are connected (through boardtoboard connectors J[TE000] and J[TE000]) to the USB microcontroller on the TE000 micromodule. Pin Dir. 1 power Vcc /O Data /O Data+ BRAD Table 11: connector J1 out. Header connector J1[TE00] is a. mm (100 mil) pitch connector compatible with the following industrial USB connectors: Bulgin Mini USB Buccaneer PX0 (P68 B type Mini USB, front panel mounted, way crimp connector at rear) 6

7 Demo Carrier Board for ndustrial Micromodule Figure : Bulgin PX06 (rear connector). f connector J1[TE00] is populated with a Bulgin adapter connector, it appears as shown in Figure 10. Figure 6: Bulgin PX0 (front connector). Figure 7: Bulgin PX0 (rear connector). Bulgin Mini USB Buccaneer PX06 (P68 B type Mini USB, rear panel mounted, way header connector at rear) Figure 10: connector J1 [TE00] when populated. Figure 8: Bulgin PX06 (front connector). f connector J1[TE00] is not populated (default assembly), it can be connected to a host USB socket through the J1toUSB adapter cable (Figure 11) delivered with the TE00 Demo Carrier Board. 7

8 Demo Carrier Board for ndustrial Micromodule Figure 11: J1toUSB adapter cable. When plugging the header connector of the adapter cable into the unpopulated connector J1[TE00], please make sure to pull slightly apart the s in such a way that headerpitch matches connector J1 pitch; plug the corresponding to the red wire in the outermost contact hole (1 VCC); leave the innermost braid) unconnected. contact ( When the adapter cable is inserted into the unpopulated connector J1[TE00], it should look like shown in Figure 1. The mechanical strain between the two connectors make soldering them unnecessary for most applications. Figure 1: adapter connector in place (board side). For the USB power line, please see paragraph USB bus power supply. Pushbutton The pushbutton S1 [TE00] is connected to the master reset line of the module. By pressing the button, both the EZUSB FX USB microcontroller and the FPGA are reset. The value of the master reset is overridden by switch S [TE000] on the TE000 micromodule when it is set to Reset. Reference Designs Genode Labs included some TE00 reference designs for a range of TE000 modules to Genode FX project official source tree, and with the next release of Genode FX, the TE000 support will become a regular part of the official Gen 8

9 Demo Carrier Board for ndustrial Micromodule ode FX distribution. For furhter information, please consult the following references: Genode FX FPGA graphics Genode FX project page Genode FX project tree Rev Date Who FDR created FDR dimensions vised FDR added differential pairs and singleended lines details FDR added labels on J1 picture; added J1toUSB adapter cable FDR improved TE00 tote000 description Genode FX reference UCF files Ordering nformation Demo Carrier Board The Demo Carrier Board is available at Trenz Eectronic Shop with ordering number TE00. For other kind of headers J[TE00] and J[TE00], or for other header mounting options, please contact Trenz Electronic. Description re Table 1: document change history Optomotive Parts Optomotive ( is a Slovenian mechatronic company. The Cameleon Sensor Head is available at Trenz Eectronic Shop with ordering number 67. Bulgin Parts Bulgin (Elektron Components Ltd) is a UKbased company designing and manufacturing electromechanical components. For a comprehensive list of distributors, please visit Trenz Electronic Shop To reach Trenz Eectronic Shop, please visit Document Change History

10 Demo Carrier Board for ndustrial Micromodule Appendix The following tables reports out information of the multi connectors J[TE00], J[TE00] and J[TE00]. BB name FPGA dir dir FPGA BB name 1 Vcc power power Vcc 6 7 B0 C C C B0 C 8 B0_L_N B A B0_L_P B0_L_N D C B0_L_P 1 1 B0_L0_P B6 A6 B0_L0_N 1 1 GCLK_L1_N B B8 GCLK_L1_P B_L0_N D D1 B_L0_P 18 1 B_L01_P C1 C B_L01_N 0 1 B_L07_P G6 G B_L07_N B_L0_N E1 E B_L0_P 6 7 B0_L1_P F7 E7 B0_L1_N 8 B0_L1_N E6 D6 B0_L1_P 0 1 B0_L18_N D7 C7 B0_L18_P B0_L17_N F8 E8 B0_L17_P 6 7 B0 A8 A8 A7 B0 A7 8 GCLK_L1_N D C GCLK_L1_P 0 Table 1: out of header J [TE00]. 10

11 Demo Carrier Board for ndustrial Micromodule Pin BB name FPGA Dir Dir FPGA BB name Pin 1 GCLK_L11_P D10 E10 GCLK_L11_N B0_L0_P C11 D11 B0_L0_N 6 7 B0 A11 A11 G B0 G 8 GCLK_L1_N A10 B10 GCLK_L1_P B0_L1_N F E B0_L1_P 1 1. V. V 1 1 B0 A1 A1 B11 B0 B B0_L06_N E1 F1 B0_L06_P 18 1 B0 E1 E1 D1 B0 D1 0 1 B0_L08_N F11 E11 B0_L08_P B0_L0_N B1 A1 B0_L0_P 6 7 B0_L01_N A16 B16 B0_L01_P 8 B0_L0_N C1 D1 B0_L0_P 0 1 B0_L0_N A1 B1 B0_L0_P 1. V 1. V Vcon power 6 7 Vcon power.0 V 8 0 Table 1: out of header J [TE00]. 11

12 Demo Carrier Board for ndustrial Micromodule BB name FPGA dir dir FPGA BB name 1 DOUT DOUT6 DOUT7 6 7 DOUT8 8 DOUT LNE_VALD 1 1 FRAME_VALD 1 1 DOUT /O STLN_OUT 18 1 O EXPOSURE 0 1 O SCLK /O STFRM_OUT /O SDATA 6 7 O SYSCLK 8 PXCLK 0 1 DOUT1 DOUT DOUT 6 7 DOUT 8.0 V 0 Table 1: out of header J [TE00]. 1