Digilab 2E FPGA Development Board

Transcription

1 Digilab 2E FPGA Development Board Design Resources for Digital Engineers digilent, inc. The Digilab 2E (D2E) FPGA-based development board makes an excellent prototyping platform for moderate to complex digital circuits and systems. The D2E board features a 200K-gate Xilinx Spartan 2E XC2S200E FPGA in a PQ208 package that provides 143 user I/Os. All available I/O signals are routed either to the expansion connectors, or to the ports and other on-board devices. A single on-board pushbutton and LED allow for quick circuit and device programming checks, as well as basic I/O (e.g., for reset and status). The D2E board mates with several existing peripheral boards so that entire digital systems can be quickly and easily constructed. The D2E board works seamlessly with the free WebPack CAD tools, and it ships with a programming cable and power supply, so projects can be implemented immediately, without the need for any other components or expenses. Digilab 2E (D2E) Development Board D2E board features include: A Xilinx XC2S200E FPGA in a PQ208 package offering 143 user I/O signals; Dual on-board 1.5A power regulators (3.3V and 1.8V); A socketed 50MHz oscillator; A socket for a Xilinx SPROM; EPP-capable parallel port for JTAG-based FPGA programming and user data transfers; A separate JTAG header for use with Xilinx parallel 3 or parallel 4 programming cables; 5-wire RS-232 serial port; Status LED and pushbutton for basic I/O; mil spaced, right angle DIP socket 40- pin expansion connectors. Power jack 5-9VDC Serial Port Parallel Port 2.5VDC regulator 3.3VDC regulator RS-232 converter EPP or SPP parallel port Buffer Port/prog control switch Serial Port JTAG Port 50MHz CLK Status LED Xilinx Spartan2E XC2S200E-PQ208 Expansion A Push button Expansion E SPROM Expansion B Expansion F Expansion C Expansion D For more information, please see the Digilab 2E reference documents available at the Digilent website. D2E Block Diagram

2 Digilent 2E System Board Reference Manual Revision: March 24, East Main Pullman, WA (509) Voice and Fax PRELIMINARY Digilab 2E Reference Manual Overview The Digilab 2E (D2E) development board featuring the Xilinx Spartan 2E XC2S200E FPGA provides an inexpensive and expandable platform on which to design and implement digital circuits of all kinds. D2E board features include: A Xilinx XC2S200E FPGA; Dual on-board 1.5A power regulators (2.5V and 3.3V); A socketed 50MHz oscillator; An EPP-capable parallel port for JTAGbased FPGA programming and user data transfers; A 5-wire Rs-232 serial port; A status LED and pushbutton for basic I/O; Six 100-mil spaced, right-angle DIP socket 40-pin expansion connectors. The D2E board has been designed specifically to work with the Xilinx ISE CAD tools, including the free WebPack tools available from the Xilinx website. Like other Spartan 2 boards in the Digilab family, the D2E board has been partitioned so that only the hardware required by a particular project need be purchased. Several existing peripheral boards Power jack 5-9VDC Serial Port Parallel Port 2.5VDC regulator 3.3VDC regulator RS-232 converter EPP or SPP parallel port Buffer Port/prog control switch Serial Port JTAG Port 50MHz CLK Push button Status LED Xilinx Spartan2E XC2S200E-PQ208 Expansion A Expansion E SPROM Expansion B Expansion F D2E circuit board block diagram that mate with the expansion connectors are currently available (see and new boards are frequently added. The lowcost, standard expansion connectors allow new peripheral boards, including wire-wrap or manually soldered boards, to be quickly designed and used. The D2E board ships with a power supply and programming cable, so designs can be implemented immediately without the need for any additional hardware. Expansion C Expansion D Copyright All rights reserved Document:

3 Digilent 2E Reference Manual Functional description The Digilab D2E board has been designed to offer a low-cost and minimal system for designers who need a flexible platform to gain exposure to the Spartan 2E device, or for those who need to prototype FPGA-based designs rapidly. The D2E board provides only the essential supporting devices for the Spartan 2E, and routes all available FPGA signals to standard expansion connectors. Included on the board are 2.5VDC and 3.3VDC regulators, a JTAG configuration circuit that uses a standard parallel cable, basic communication ports including an enhanced parallel port and 5-wire serial port, a 50MHz oscillator, and a pushbutton and LED for rudimentary I/O. The D2E board has been designed to serve as a host for various peripheral boards. The expansion connectors on the D2E board mate with standard 40-pin, 100 mil spaced DIP headers available from any catalog distributor. Expansion connectors provide the unregulated supply voltage (VU), 3.3V, GND, and 37 FPGA signals to peripheral boards, so system designers can quickly develop application- specific peripheral boards. Digilent also produces a collection of expansion boards with commonly used devices. See the Digilent website ( for a listing of currently available boards. Table 1 shows all signals routed on the D2E board. These signals, and the circuits that they connect to, are described in the following sections. Power Supplies VU VDD33 Unregulated power supply voltage depends on power supply used. Must be between 5VDC and 10VDC. Routed to regulators and expansion connectors only. FPGA VCCO and VCC for all other devices, routed on PCB plane. 1.5A can be drawn with less than 20mV ripple (typical) FPGA VCCINT routed on PCB plane System ground routed to all devices on PCB ground plane VDD25 GND Programming and parallel port PWE EPP mode write enable signal (in to FPGA) PD0-PD7 Bi-directional data signals PINT Interrupt signal (out from FPGA) PWT EPP mode wait signal (out from FPGA) PDS EPP mode data strobe (in to FPGA) PRS Reset signal (in to FPGA) PAS EPP mode address strobe (in to FPGA) Serial port RXD Serial port receive data (in to FPGA) TXD Serial port send data (out from FPGA) DSR Serial port data set ready (out from FPGA) CTS Serial port clear to send (out from FPGA) RST Serial port request to send (in to FPGA) On board devices BTN1 User-controllable pushbutton input LED1 User-controllable status LED CLK1 CMOS oscillator connected to GCLK0 Expansion Connectors A4-A40 A bus signals connecting the A & E connectors to the FPGA B4-B14 B bus signals connecting the B & F connectors to the FPGA C4-C40 C bus signals connecting the C connector to the FPGA D4-D40 D bus signals connecting the D connector to the FPGA Table 1. D2E board signal definitions Parallel port and FPGA configuration circuit The Digilab 2E board uses a DB-25 parallel port connector to route JTAG programming signals from a host computer to the FPGA. This same connector also routes the computer s parallel port pins to the FPGA following the EPP port definition contained in the IEEE 1284 standard. A three-state buffer, controlled by a switch, determines whether the JTAG port or EPP port is enabled. With this circuit, the Rev: Apr 14, Page 2 of 10

4 Digilent 2E Reference Manual FPGA can be configured using the JTAG protocol over the parallel cable. The same cable can then be used (after the switch is repositioned) to move data between the board and the host computer using the high-speed EPP protocol. A separate JTAG header is also provided so that a dedicated programming cable (like the Xilinx Parallel III cable) can be used. The JTAG programming circuit follows the JTAG schematic available from Xilinx, so that the Digilab 2E board is fully compatible with all Xilinx programming tools. The EPP parallel port circuit follows the guidelines in the IEEE 1284 specification, and data rates approaching 2Mbytes/second can be achieved. JTAG and EPP connections are shown in the diagrams below. Pin 13 Pin 1 Pin 25 Pin 25 DB25 parallel port connector Front view Pin 1 Top view of hole pattern, with cable attaching from this side Pin 14 Pin EPP signal EPP Function 1 Write Enable (O) Low for read, High for write 2-9 Data bus (B) Bidirectional data lines 10 Interrupt (I) Interrupt/acknowledge input 11 Wait (I) Bus handshake; low to ack 12 Spare NOT CONNECTED 13 Spare NOT CONNECTED 14 Data Strobe (O) Low when data valid 15 Spare NOT CONNECTED 16 Reset (O) Low to reset 17 Address strobe (O) Low when address valid GND System ground Figure 1. Parallel port connectors and signals The D2E board directly supports JTAG and SPROM configuration. Hardware debugger configuration is supported indirectly. To configure the board from a computer using the JTAG mode, set switch 1 (SW1) in the JTAG position, and attach a power supply and programming cable. The power supply must be connected before the parallel cable, or the board may hang in a non-communicating state. The board will be auto-detected by the Xilinx JTAG programming software, and all normal JTAG operations will be available. To configure the FPGA from an SPROM, load the programmed SPROM into the 8-pin ROM socket (labeled IC6), place SW1 in the PORT position, add jumpers to all mode pins, and apply power. To configure the board using the hardware debugger protocol, a slight board modification is required a jumper wire must be soldered to the non-vcc side of R45. Insert wire-wrap posts into the SPROM socket, attach the hardware debugger signals to the appropriate posts, and attach the PROG signal to the jumper wire attached to R45. The hardware debugger programming software will now automatically recognize the board, and hardware debugger programming can proceed as normal. Programming circuit detail is shown below. Note that all parallel port signals are routed to the test header J12 for easy connection of test and measurement equipment. Rev: Apr 14, Page 3 of 10

5 Digilent 2E Reference Manual Pull-up resistors are used on all parallel port signals. They are not shown here. Write Enable (PWE) Data Strobe (PDS) Data 0 (PD0) Data 1 (PD1) Reset (PRST) Data 2 (PD2) Address Strobe (PAS) Data 3 (PD3) Data 4 (PD4) Data 5 (PD5) Data 6 (PD6) P206 P205 P15 P11 P203 P10 P204 P9 P8 P7 P6 P107 P155 P153 P104 Xilinx Spartan 2E PQ208 INIT CCLK DATA IN DONE M0 M1 M2 Pull-ups on INIT and DONE not shown Jumper block SPROM 8-DIP Data 7 (PD7) Interrupt (PINT) Wait (PWT) P5 P4 P3 P157 P207 P159 P2 TDO TCLK TDI TMS DB25 connector GND VDD SENSE CABLE DET1 CABLE DET2 PORT Vdd Decouping three-state buffer Enable GND Program enable switch (SW1) JTAG Figure 2. Parallel port and programming circuit schematic Serial Port The D2E serial port uses a Maxim MAX3386E RS-232 voltage converter to generate the required RS- 232 voltages. Five signals are connected through the RS-232 converter, allowing for partial hardware handshaking. The serial port pin definitions and circuit are shown below. The serial port is provided in part to support the Xilinx MicroBlaze embedded RSIC processor core available from the Xilinx website. The two devices connected to either end of a serial cable are known as the Data Terminal Equipment (DTE) and the Data Communications Equipment (DCE). The DCE was originally conceived to be a modem, but now many devices connect to a computer as a DCE. A DTE device uses a male DB-9 connector, and a DCE device uses a female DB-9 connector. The DTE is considered the source of data, and the DCE the peripheral device. Two DTE devices can be connected via a serial cable only if lines Rev: Apr 14, Page 4 of 10

6 Digilent 2E Reference Manual two and three are crossed this is known as a null modem cable. A DTE and DCE device can be connected with a straight-through cable. The Digilab 2E board is configured as a DCE device. Serial Port Pin Definitions Pin 9 Pin 1 DB9 top-down hole pattern; cable attaches from this side Pin 5 Pin 9 DB9 serial port connector Front view Pin 1 Pin 6 Pin # Name Function Direction Connected 1 DCD Data carrier detect DCE DTE N 2 RXD Received data DCE DTE Y 3 TXD Transmitted data DCE DTE Y 4 DTR Data terminal ready DCE DTE N 5 SG Signal ground Y 6 DSR Data set ready DCE DTE Y 7 RTS Request to send DCE DTE Y 8 CTS Clear to send DCE DTE Y 9 RI Ring Indicator DCE DTE N DSR RXD RTS TXD CTS Maxim MAX3386E RS232 Voltage Converter P200 P201 P198 P202 P199 Xilinx Spartan 2E PQ208 DB9 Connector GND Figure 3. Serial port circuit schematic Oscillator The Digilab 2E uses a socketed half-size 8-pin DIP oscillator. The board ships with a 50MHz oscillator, allowing for system clocks from virtually DC to 200MHz (using the Spartan 2E DLL circuit and/or clock counter-dividers). Oscillators from 32KHz to 100MHz can easily be substituted, allowing for a wide range of clock frequencies. The oscillator, which is connected to the FPGA GCK0 input (P80), is bypassed with a 0.1uF capacitor and it is located as physically close to the FPGA as possible (trace length is about 10mm). Power Supplies The Digilab 2E board uses two LM A voltage regulators to produce 2.5VDC and 3.3VDC supplies. The regulator inputs are driven from an external DC power supply connected to the on-board 2.1mm center-positive power jack. The regulators have 10uF of input capacitance, 20uF of local output capacitance, and 10uF of regulation bypass capacitance. This allows the regulators to produce stable, low noise supplies using inexpensive power supplies, regardless of load (up to 1.5A). The regulator Rev: Apr 14, Page 5 of 10

7 Digilent 2E Reference Manual bodies are soldered to the board for improved thermal dissipation. DC supplies in the range of 5VDC to 10VDC may be used. The Digilab 2E board uses a four layer PCB, with the inner layers dedicated to VCC and GND planes. Most of the VCC plane is at 3.3V, with an island under the FPGA at 2.5V. The FPGA and the other ICs on the board all have 0.1uF bypass capacitors placed as close as possible to the VCC pins. Total board current is dependant on FPGA configuration, clock frequency, and external connections. In test circuits with roughly 50K gates routed, a 50MHz clock source, and a single expansion board attached (the DIO2 board), approximately 200mA +/- 30% of supply current is drawn from the 2.5V supply, and approximately 150mA +/- 50% is drawn from the 3.3V supply. These currents are strongly dependent on FPGA and peripheral board configurations. All FPGA VCCO pins are connected to the 3.3V supply. If other VCCO voltages are required, please contact Digilent for information regarding various options (Digilent can be contacted through Expansion connectors Pin 39 Pin 3: 3.3V Pin 1: GND Pin 39 Pin 40 Pin 4 Pin 2: VU Pin 40 The six expansion connectors labeled A-F use 100 mil spaced DIP headers. All six connectors have GND routed to pin 1, VU routed to pin 2, and 3.3V routed to pin 3. Pins 4-40 all route directly to the FPGA. The connectors are organized in pairs, with the A & B, C& D, and E & F pairs placed on the same board edge. Connectors A & B and E & F are routed in parallel, with pairs A & E and B & F sharing identical pin connections to the FPGA. Connectors C & D have all pins routed to separate FPGA pins. All connector pairs are separated by 400 mils, so any peripheral board can be placed in any connector (or pair of connectors). The PQ208 package used on the D2E board allows 122 signals to be routed to the expansion connectors (the remaining 21 available signals are routed to the parallel and serial connectors). Connectors C and D F E are closest to the FPGA, and all C and D pins are connected to the closest available FPGA pins with Figure 4. Expansion connector detail the shortest possible route. Thus, the 74 FPGA signals routed to the C & D connectors will exhibit the least amount of signal delay, and data rates of up to 100MHz are attainable. The A & E connectors also DB-25 DB-9 A 37 B 11 Spartan 2E PQ C D Rev: Apr 14, Page 6 of 10

8 Digilent 2E Reference Manual route 37 FPGA signals, but with less favorable routes. Only 11 FPGA signals were left to route to the B & F connectors, so 26 pins on those connectors are not connected. Connector pin definitions follow. Rev: Apr 14, Page 7 of 10

9 Digilent 2E Reference Manual Table 2. Digilab 2E Expansion Connector pinouts A&E connector B&F connector C connector D connector Pin Signal S-II pin Pin Signal S-II pin Pin Signal S-II pin Pin Signal S-II pin 1 GND - 1 GND - 1 GND - 1 GND - 2 VU - 2 VU - 2 VU - 2 VU - 3 VDD33-3 VDD33-3 VDD33-3 VDD33-4 A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B11 185* 11 C D A B12 182* 12 C D A B C D A B C D A B15-15 C D A B16-16 C D A B17-17 C D A NC - 18 C D A NC - 19 C D A NC - 20 C D A NC - 21 C D A NC - 22 C D A NC - 23 C D A NC - 24 C D A NC - 25 C D A NC - 26 C D A NC - 27 C D A NC - 28 C D A NC - 29 C D A NC - 30 C D A NC - 31 C D A NC - 32 C D A NC - 33 C D A NC - 34 C D A NC - 35 C D A NC - 36 C D A NC - 37 C D A NC - 38 C D A NC - 39 C D A NC - 40 C D40 71 * uses GCLK pin Rev: Apr 14, Page 8 of 10

10 Digilent 2E Reference Manual Pushbutton and LED A single pushbutton and LED are provided on the board allowing basic status and control functions to be implemented without a peripheral board. As examples, the LED can be illuminated from a signal in the FPGA to verify that configuration has been successful, and the pushbutton can be used to provide a basic reset function independent of other inputs. The circuits are shown below. Vdd Push button 4.7K 4.7K 80 Ohm P77 Xilinx Spartan 2E PQ208 P69 Figure 5. Pushbutton and LED detail Spartan 2E FPGA The block diagram of the Digilab 2E board shows all connections between the FPGA and the devices on the board. All FPGA pin connections are shown in the following table. DB-25 parallel port JTAG 4 13 DB-9 serial port SPROM 5 4 Clock LED Push button The Spartan device can be configured using the Xilinx JTAG tools and a parallel cable connecting the D2E board and the host computer. Note that a separate JTAG header that connects directly to the JTAG pins is also provided. Spartan 2E PQ Expansion A Expansion B Expansion C Expansion E Expansion F 37 Expansion D For further information on the Spartan FPGA, please see the Xilinx data sheets available at the Xilinx website ( Figure 6. Spartan 2E connection detail Rev: Apr 14, Page 9 of 10

11 Digilent 2E Reference Manual Table 3. Digilab 2E board Spartan 2E FPGA pinout Pin # Function Pin # Function Pin # Function Pin # Function 1 GND 53 VCCO 105 VCCO 157 TDO 2 TMS 54 M2 106 PROG 158 GND 3 PWT 55 A INIT 159 TDI 4 PINT 56 A D C19 5 PD7 57 A D C18 6 PD6 58 A D C17 7 PD5 59 A D C16 8 PD4 60 A9 112 D C15 9 PD3 61 A8 113 D C14 10 PD2 62 A7 114 D C13 11 PD1 63 A6 115 D9 167 C12 12 GND 64 A5 116 D C11 13 VCCO 65 GND 117 GND 169 C10 14 VCCINT 66 VCCO 118 VCCO 170 GND 15 PD0 67 VCCINT 119 VCCINT 171 VCCO 16 A40 68 A4 120 D7 172 VCCINT 17 A39 69 LED1 121 D8 173 C9 18 A38 70 D D5 174 C8 19 GND 71 D D6 175 C7 20 A37 72 GND 124 GND 176 C6 21 A36 73 D D4 177 GND 22 A35 74 D C C5 23 A34 75 D C C4 24 A33 76 VCCINT 128 VCCINT 180 B14 25 GND 77 BTN1* 129 C B13 26 VCCO 78 VCCO 130 VCCO 182 B12* 27 A32 79 GND 131 GND 183 GND 28 VCCINT 80 CLK1* 132 C VCCO 29 A31 81 D C B11* 30 A30 82 D C VCCINT 31 A29 83 D C B10 32 GND 84 D C B9 33 A28 85 GND 137 GND 189 B8 34 A27 86 D C GND 35 A26 87 D C B7 36 A25 88 D C B6 37 VCCINT 89 D C B5 38 VCCO 90 VCCINT 142 VCCINT 194 B4 39 GND 91 VCCO 143 VCCO 195 VCCINT 40 A24 92 GND 144 GND 196 VCCO 41 A23 93 D C GND 42 A22 94 D C RTS 43 A21 95 D C CTS 44 A20 96 D C DSR 45 A19 97 D C TXD 46 A18 98 D C RXD 47 A17 99 D C PRS 48 A D C PAS 49 A D DIN 205 PDS 50 M1 102 D C PWE 51 GND 103 GND 155 CCLK 207 TCK 52 MO 104 DONE 156 VCCO 208 VCCO * uses GCLK pin Rev: Apr 14, Page 10 of 10

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17 Digilab Digital I/O 1 Peripheral Board Design Resources for Digital Engineers digilent, inc. The Digilab Digital I/O Board 1 (DIO1) provides a ready-made source for I/O devices and ports commonly used in digital systems. The DIO1 board can be used with any Digilab system board to create a platform that can host a wide range of projects. Many projects can be implemented immediately without the need for any other components; if further custom circuits are needed, a Digilab breadboard or wirewrap board can be inserted between a system board and DIO1 board. All devices on the DIO1 board are driven directly from an attached system board, keeping system designs as simple as possible. DIO1 board features include: A 4 digit, seven-segment LED display; 8 individual LEDs; 4 momentary pushbuttons; 8 slide switches; 3-bit VGA port; PS2 mouse/keyboard port. For more information, please see the Digilab DIO1 reference documents available at our website. VGA Port PS2 port Digilab DIO1 Peripheral Board Connector A 5 2 Connector B 12 4 displays 4 buttons 8 switches DIO1 Block Diagram HC373 Latch 8 LEDs

18 Digilent DIO1 Manual Revision: May 10, East Main Pullman, WA (509) Voice and Fax TM Overview The Digital I/O board 1 (DIO1) is one of several expansion boards designed to mate with Digilent system boards. The DIO1 is an inexpensive board that contains an assortment of basic digital I/O devices, including buttons, switches, and several LED displays. The DIO1 board can be combined with Digilab system boards to provide a source of ready-made I/O devices, allowing a wide range of projects to be implemented without the need for any other components. DIO1 board features include: A four digit seven-segment LED display; 8 individual LEDs; A 3-bit VGA port; 5 momentary pushbuttons; 8 slide switches; A PS2 mouse/keyboard port. Functional description The DIO1 board has been designed to provide a basic, inexpensive platform that contains many of the I/O devices commonly found in digital systems. Unlike the more advanced DIO2 board, the DIO1 board has been designed so that all signals pass directly to an attached system board, so no intermediate logic is required. When mated with a Digilab system board, the DIO1 board can provide a flexible prototyping system that can be operational immediately. LEDs Eight LEDs are provided for circuit outputs. The LED cathodes are tied to ground via 270- ohm resistors, and the anodes are driven from the 74HC373 (so the LED drive signals are active high). VGA Port Connector A 5 2 Connector B HC373 Latch LD signals LD1- LD8 RP1 270 Ohm PS2 port 4 displays 5 buttons 8 switches 8 LEDs GND Figure 2. LED Circuit Figure 1. DIO1 schematic Signals All named signals used on the DIO1 board are defined in the Table 1. Voltage levels for all 10 pages Doc:

19 DIO1 Reference Manual signals arriving from an attached Digilab system board are determined by the system board, but all signals arising on the I/O board derive from the on-board 5VDC regulator (so they are all 5V CMOS signals). The DIO1 board uses a two-layer process, so all signals are available on the top and bottom layers. Many signals are brought to a test point header for easy test and measurement equipment attachment. Power Supply The DIO1 board receives system power from pins 39 and 37 of connectors A and B (which mate to pins 1 and 3 of an attached system boards). Pin 37 provides Vdd from the attached system board (assumed to be 3.3VDC), and pin 39 is connected to ground. Up to 5VDC can be safely applied to the Vdd input pin (pin 37). The DIO1 board typically consumes less than 10mA with no LED s illuminated, and up to 130mA with all LEDs illuminated (including all segments of the seven-segment display). Seven-segment LED display The DIO1 board contains a modular 4-digit, common anode, seven-segment LED display. In a common anode display, the seven anodes of the LEDs forming each digit are connected to four common circuit nodes (labeled AN1 through AN4 on the DIO1 board). Each anode, and therefore each digit, can be independently turned on and off by driving these signals to a 1 or a 0. The cathodes of similar segments on all four displays are also connected together into seven common circuit nodes labeled CA through CG. Thus, each cathode for all four displays can be turned on and off independently. Power Supplies VU VDD33 Unregulated power supply voltage from attached system board typically 5-9VDC. Although connected to the board, this supply is not used on the DIO1 board. Regulated power supply voltage (3.3VDC) from attached system board. All devices on DIO1 board use this supply. GND System ground VGA signals HS VGA Horizontal Sync signal VS VGA Vertical Sync signal R VGA 1-bit red data G VGA 1-bit green data B VGA 1-bit blue data PS2 signals KCLK PS2 (Keyboard or Mouse) clock signal KDAT PS2 (Keyboard or Mouse) data signal Input devices BTN1-4 Pushbuttons 1 through 4 SW1- Slide switches 1 through 8 SW8 Output devices LD0-LD8 Discreet LEDs 1 through 8 CA-CF Seven-segment display cathodes AN1- Seven-segment display anodes AN3 Table 1. DIO1 board signal definitions This connection scheme creates a multiplexed display, where driving the anode signals and corresponding cathode patterns of each digit in a repeating, continuous succession can create a 4-digit display. In order for each of the four digits to appear bright and continuously illuminated, all four digits should be driven once every 1 to 16ms (for a refresh frequency of 60Hz to 1KHz). For example, in a 60Hz refresh scheme, each digit would be illuminated for ¼ of the refresh cycle, or 4ms. The controller must assure that the correct cathode pattern is present when the corresponding anode signal is driven. To illustrate the process, if AN1 is driven high while CB and CC are driven low, then a 1 will be displayed in digit position 2. Then, if AN2 is driven high while CA, CB and CC are driven low, then a 7 will be displayed in digit position 2. If AN1/CB, CC are driven for 4ms, and then AN2/CA, CB, CC Copyright Page 2

20 DIO1 Reference Manual are driven for 4ms in an endless succession, the display will show 17 in the first two digits. An example timing diagram is provided to the right. Anodes -- connected to CPLD via transistors for greater current Vdd a4 a3 a2 a1 AN1 AN2 AN3 AN4 Refresh period = 1ms to 16ms Digit period = Refresh / 4 Cathodes Digit 1 Digit 2 Digit 3 Digit 4 Seven segment display refresh signals and timings a b c d e f g dp Cathodes -- connected to CPLD pins via 100Ω resistor f e. a g d b c (a) Common anode a f g e d c b (b) Figure 3. (a) Seven segment display detail. (b) common anode display configuration. (c) segement illumination patterns for decimal digits. (d) segment illumination truth table. (c) Digit Illuminated Segment Show a b c d e f g n (d) Vdd Push Buttons Vdd RP8&9 4.7KOhm GND To Connector Outputs from the 4 momentary-contact push buttons are normally low, and are driven high only while the button is actively pressed. The buttons exhibit a worst-case bounce time of about 1ms. A 74HC14 Hex Schmidt Trigger inverter provides the debounce filtering and ESD protection. The button outputs are brought out directly to pins on interface connector B. Copyright Page 3

21 DIO1 Reference Manual Switches The eight slide switches can be used to connect either Vdd or GND to eight pins on interface connecter B. The switches exhibit about 2ms of bounce, and no active debouncing circuit is employed. A 4.7K-ohm series resistor is used for nominal input protection. Vdd GND RP6 & KOhm To Connector PS2 port The DIO1 board includes a 6-pin mini-din connector that can accommodate a PS2 mouse or PS2 2 keyboard connection. Both the 4 6 mouse and keyboard use a twowire serial bus (including clock and data) to communicate with a host device, and both drive the bus with identical signal timings. Both use 11-bit words that include a start, stop and odd parity bit, but the data packets are organized differently, and the keyboard interface allows bi-directional data transfers (so the host device can illuminate state LEDs on the keyboard). Bus timings are shown below. The clock and data signals are only driven when data transfers occur, and otherwise they are held in the idle PS2 Connector front view Pin 6 Pin 1 Pin 5 Bottom-up hole pattern PS2 Pin Definitions Pin Function 1 Data 2 Reserved 3 GND 4 Vdd 5 Clock 6 Reserved state at logic 1. The timings define signal requirements for mouse-to-host communications and bi-directional keyboard communications. Edge 0 T CK T CK Edge 10 Symbol Parameter Min Max CLK T CK T SU Clock time 30us 50us Data-to-clock setup time 5us 25us T HLD Clock-to-data hold time 5us 25us DATA T SU T HLD '0' start bit '1' stop bit Copyright Page 4

22 DIO1 Reference Manual Keyboard The keyboard uses open collector drivers so that either the keyboard or an attached host device can drive the two-wire bus (if the host device will not send data to the keyboard, then the host can use simple input-only ports). The clock and data signals (PS2C and PS2D) are connected directly to pins on the B connector. A PS2-style keyboard uses scan codes to communicate key press data (nearly all keyboards in use today are PS2 style). Each key has a single, unique scan code that is sent whenever the corresponding key is pressed. If the key is pressed and held, the scan code will be sent repeatedly once every 100ms or so. When a key is released, a F0 key-up code is sent, followed by the scan code of the released key. If a key has a shift character that is A host device can also send data to the keyboard. Below is a short list of some oftenused commands. ED Turn on/off Num Lock, Caps Lock, and Scroll Lock LEDs. The keyboard acknowledges receipt of an ED by returning an FA, after which the host send another byte to set LED status: Bit 0 sets Scroll Lock; bit 1 sets the Num Lock; and Bit 2 sets Caps lock. Bits 3 to 7 are ignored. EE Echo. Upon receiving an echo command, the keyboard replies with the same scan code ( EE ). F3 Set scan code repeat rate. The keyboard acknowledges receipt of an F3 by returning an FA, after which the host sends a second byte to set the repeat rate. FE Resend. Upon receiving a resend ESC 76 F1 05 F2 06 F3 04 F4 0C F5 03 F6 0B F7 83 F8 0A F9 01 F10 09 F11 78 F12 07 E0 75 ` ~ 0E TAB 0D 1! 16 Caps Lock 58 Shift 12 Ctrl 14 Q 15 1E W 1D A 1C Z 1Z 3 # 26 S 1B Alt 11 4 $ 25 E 24 D 23 X 22 R 2D C 21 5 % 2E F 2B T 2C G 34 V 2A 6 ^ 36 B 32 Y 35 7 & 3D H 33 8 * 3E U 3C J 3B N 31 Space 29 I 43 M 3A 9 ( 46 O 44 K 42, < 41 0 ) 45 L 4B P 4D > _ 4E ; : 4C /? 4A Alt E0 11 = + 55 [ { 54 ' " 52 ] } 5B BackSpace 66 \ 5D Enter 5A Shift 59 Ctrl E0 14 E0 74 E0 6B E0 72 different than the non-shift character, the same scan code is sent whether the shift key is pressed or not, and the host device must determine which character to use. Some keys, called extended keys, send an E0 ahead of the scan code (and they may send more than one scan code). When an extended key is released, a E0 F0 key-up code is sent, followed by the scan code. Scan codes for most keys are shown in the figure below. FF command, the keyboard will re-send the last scan code sent. Reset. Resets the keyboard. The keyboard should send data to the host only when both the data and clock lines are high (or idle). Since the host is the bus master, the keyboard should check to see whether the host is sending data before driving the bus. To facilitate this, the clock line can be used as a clear to send signal. If the host pulls the clock line low, the keyboard must not send any data until the clock is released (host-to- Copyright Page 5

23 DIO1 Reference Manual keyboard data transmission will not be dealt with further here). The keyboard sends data to the host in 11-bit words that contain a 0 start bit, followed by 8- bits of scan code (LSB first), followed by an odd parity bit and terminated with a 1 stop bit. The keyboard generates 11 clock transitions (at around 20-30KHz) when the data is sent, and data is valid on the falling edge of the clock. 1 indicates a negative number). The magnitude of the X and Y numbers represent the rate of mouse movement the larger the number, the faster the mouse is moving (the XV and YV bits in the status byte are movement overflow indicators a 1 means overflow has occurred). If the mouse moves continuously, the 33-bit transmissions are repeated every 50ms or so. The L and R fields in the status byte indicate Left and Right button presses (a 1 indicates the button is being pressed). Mouse The mouse outputs a clock and data signal when it is moved; otherwise, these signals remain at logic 1. Each time the mouse is moved, three 11-bit words are sent from the mouse to the host device. Each of the 11-bit words contains a 0 start bit, followed by 8 bits of data (LSB first), followed by an odd parity bit, and terminated with a 1 stop bit. Thus, each data transmission contains 33 bits, where bits 0, 11, and 22 are 0 start bits, and bits 10, 21, and 32 are 1 stop bits. The three 8-bit data fields contain movement data as shown below. Mouse status byte X direction byte Y direction byte 1 0 L R 0 1 XS YS XY YY P 1 0 X0 X1 X2 X3 X4 X5 X6 X7 P 1 0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 P 1 Idle state Start bit Stop bit Start bit Stop bit Start bit Stop bit Idle state Data is valid at the falling edge of the clock, and the clock period is 20 to 30KHz. The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a positive number in the X field, and moving to the left generates a negative number. Likewise, moving the mouse up generates a positive number in the Y field, and moving down represents a negative number (the XS and YS bits in the status byte are the sign bits a 1 Copyright Page 6

24 DIO1 Reference Manual VGA port The five standard VGA signals Red (R), Green (G), Blue (B), Horizontal Sync (HS), and Vertical Sync (VS) are routed directly from the A connector to the VGA connector. A series resistor is used on each color line to provide 3- bit color, with 1 bit each for Red, Green, and Blue. The series resistor uses the 75 ohm VGA cable termination to ensure that the color signals remain in the VGA-specified 0V 0.7V range. The HS and VS signals are TTL level. VGA signal timings are specified, published, copyrighted and sold by the VESA organization ( The following VGA system and timing information is provided as an example of how a VGA monitor might be driven in 640 by 480 mode. For more precise information, or for information on higher VGA frequencies, refer to document available at the VESA website (or experiment!). Pin 5 Pin 10 Pin 1 Pin 6 Pin 1 Pin 15 Pin 11 Pin 15 DB15 VGA connector Front view DB15 through-hole pattern as seen from the top DB15 Connector Red Green Blue Horizontal Sync To R on Connector B To G on Connector B To B on Connector B To HS on Connector B Vertical Sync To VS on Connector B GND VGA systems and signal timings for a 60Hz, 640x480 display Copyright Page 7

25 DIO1 Reference Manual CRT-based VGA displays use amplitude modulated, moving electron beams (or cathode rays) to display information on a phosphorcoated screen. LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal, thereby changing light permitivity through the crystal on a pixel-by-pixel basis. Although the following description is limited to CRT displays, LCD displays have evolved to use the same signal timings as CRT displays (so the signals discussion below pertains to both CRTs and LCDs). CRT displays use electron beams (one for red, one for blue and one for green) to illuminate phosphor that coats the inner side of the display end of a cathode ray tube (see drawing below). Electron beams emanate from electron guns, which are a finely pointed, heated cathodes placed in close proximity to a positively charged annular plate called a grid. The electrostatic force imposed by the grid pulls away rays of energized electrons as current flows into the cathodes. These particle rays are initially accelerated towards the grid, but they soon fall under the influence of the much larger electrostatic force that results from the entire phosphor coated display surface of the CRT being charged to 20kV (or more). The rays are focused to a fine beam as they pass through the center of the grids, and then they accelerate to impact on the phosphor coated display surface. The phosphor surface glows brightly at the impact point, and the phosphor continues to glow for several hundred microseconds after the beam is removed. The larger the current fed into the cathode, the brighter the phosphor will glow. Between the grid and the display surface, the beam passes through the neck of the CRT Cathode ray where two coils of wire produce orthogonal electromagnetic fields. Because cathode rays are composed of charged particles (electrons), they can be bent by these magnetic fields. Current waveforms are passed through the coils to produce magnetic fields that cause the electron beams to transverse the display surface in a raster pattern, horizontally from left to right and vertically from top to bottom. Information is only displayed when the beam is moving in the forward direction (left to right and top to bottom), and not during the time the beam is reset back to the left or top edge of the display. Much of the potential display time is therefore lost in blanking periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass. The size of the beams, the frequency at which the beam can be traced across the display, and the frequency at which the electron beam can be modulated determine the display resolution. Modern VGA displays can accommodate different resolutions, and a VGA controller circuit dictates the resolution by producing timing signals to control the raster patterns. The controller must produce TTL-level synchronizing pulses to set the frequency at Anode (entire screen) High voltage supply (>20kV) Cathode ray tube deflection control Deflection coils Grid grid control gun control Control board Cathode ray tube display system Electron guns (Red, Blue, Green) Sync signals (to deflection control) which current flows through the deflection coils, and it must ensure that pixel (or video) data is applied to the electron guns at the Copyright Page 8 R,G,B signals (to guns) VGA cable

26 DIO1 Reference Manual Symbol T S T disp T pw T fp T bp Parameter Sync pulse time Display time VS pulse width VS front porch VS back porch Vertical Sync Time Clocks Lines 16.7ms 15.36ms 64 us 320 us 928 us 416, ,000 1,600 8,000 23, Horizontal Sync Time Clocks 32 us 25.6 us 3.84 us 640 ns 1.92 us T pw T S T disp T fp T bp correct time. Video data typically comes from a video refresh memory, with one or more bytes assigned to each pixel location (the DIO1 board uses 3-bits per pixel). The controller must index into video memory as the beams move across the display, and retrieve and apply video data to the display at precisely the time the electron beam is moving across a given pixel. Current through horizontal defletion coil pixel 0,0 640 pixels are displayed each time the beam travels across the screen VGA display surface pixel 0,639 pixel 479,0 pixel 479,639 Stable current ramp - information displayed during this time Retrace - no information displayed during this time The VGA controller circuit must generate the HS and VS timings signals and coordinate the delivery of video data based on the time pixel clock. The pixel clock defines the time available HS to display 1 pixel of information. The VS signal defines the refresh frequency of the display, or the frequency at which all information on the display is redrawn. The minimum refresh frequency is a function of the display s phosphor and electron beam intensity, with practical refresh frequencies falling in the 60Hz to 120Hz range. The number of lines to be displayed at a given refresh frequency defines the horizontal retrace VGA Signal Timing "front porch" Total horizontal time Horizontal display time Horizontal sync signal sets retrace frequency retrace time "back porch" A VGA controller circuit decodes the output of a horizontal-sync counter driven by the pixel clock to generate HS signal timings. This counter can be used to locate any pixel location on a given row. Likewise, the output of a vertical-sync counter that increments with each HS pulse can be used to generate VS signal timings, and this counter can be used to locate any given row. These two continually running counters can be used to form an address into Copyright Page 9

27 DIO1 Reference Manual video RAM. No time relationship between the onset of the HS pulse and the onset of the VS pulse is specified, so the designer can arrange the counters to easily form video RAM addresses, or to minimize decoding logic for sync pulse generation. The connector pinouts are shown below. Separately available tables show pass-through connections for the devices on the DIO1 board when the board is attached to various system boards i.e., one table is available showing the FPGA connections to the DIO1 devices for a D2 system board, another table is available showing the FPGA connections for a D2E board, a third for the D2XL board, etc. Connector pinouts J2 (B) connector J1 (A) Connector Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal 1 CA 11 CF 21 A1 31 n/c 30 BLU 2 SW1 12 SW6 22 LD1 32 LD6 32 PS2D 3 CB 13 CG 23 A2 33 n/c 33 GRN 4 SW2 14 SW7 24 LD2 34 LD7 34 PS2C 5 CC 15 DP 25 A3 35 n/c 35 RED 6 SW3 16 SW8 26 LD3 36 LD8 36 HS 7 CD 17 BTN2 27 A4 37 VDD33 37 VDD 8 SW4 18 BTN1 28 LD4 38 LDG 38 VS 9 CE 19 BTN4 29 n/c 39 GND 39 GND 10 SW5 20 BTN3 30 LD5 40 VU 40 VU Copyright Page 10

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30 Digilent Board Interconnect Table D2E to DIO1 Interconnect Tables Dio1 Pinout D2E Pinout Connector P2 Connector E and A Connector C Pin Signal Pin Signal Pin Signal 1 CA 39 A C SW1 40 A C CB 37 A C SW2 38 A C CC 35 A C SW3 36 A C CD 33 A C SW4 34 A C C 31 A C SW5 32 A C CF 29 A C SW6 30 A C CG 27 A C SW7 28 A C DP 25 A C SW8 26 A C BTN2 23 A C BTN1 24 A C BTN4 21 A C BTN3 22 A C A1 19 A C LD1 20 A C A2 17 A C LD2 18 A C A3 15 A C LD3 16 A C A4 13 A C LD4 14 A C A C LD5 12 A C A C LD6 10 A C A C LD7 8 A C BTN5 5 A C LD8 6 A C VCC 3 VCC VCC 3 VCC VCC 38 4 A C GND 1 GND GND 1 GND GND 40 2 VU VU 2 VU VU

31 Digilent Board Interconnect Table Dio1 Pinout D2E Pinout Connector P1 Connector F and B Connector D Pin Signal Pin Signal Pin Signal D D D D D D D D D D D D D D D D D D D D D D D D D D D D B D B D BLU 9 B D PS2D 10 B D GRN 7 B D PS2C 8 B D RED 5 B D HS 6 B D VCC 3 VCC VCC 3 VCC VCC 38 VS 4 B D GND 1 GND GND 1 GND GND 40 2 VU VU 2 VU VU