DS1220AB/AD 16k Nonvolatile SRAM

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Bertina Williamson
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1 DS122AB/AD 16k Nonvolatile SRAM FEATURES years minimum data retention in the absence of external power Data is automatically protected during power loss Directly replaces 2k x 8 volatile static RAM or EEPROM Unlimited write cycles Low-power CMOS JEDEC standard 24-pin DIP package Read and write access times as fast as Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time Full ±% V CC operating range (DS122AD) Optional ±5% V CC operating range (DS122AB) Optional industrial temperature range of -4 C to +85 C, designated IND PIN ASSIGNMENT 24-Pin ENCAPSULATED PACKAGE 72-mil EXTENDED PIN DESCRIPTION A-A DQ-DQ7 CE WE OE V CC GND A7 A6 A5 A4 A3 A2 A1 A DQ DQ1 DQ2 GND VCC A8 A9 WE OE A CE DQ7 DQ6 DQ5 DQ4 DQ3 - Address Inputs - Data In/Data Out - Chip Enable - Write Enable - Output Enable - Power (+5V) - Ground DESCRIPTION The DS122AB and DS122AD 16k Nonvolatile SRAMs are 16,384-bit, fully static, nonvolatile SRAMs organized as 248 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which cotantly monitors V CC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. The NV SRAMs can be used in place of existing 2k x 8 SRAMs directly conforming to the popular bytewide 24-pin DIP standard. The devices also match the pinout of the 2716 EPROM and the 2816 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. 1 of

2 DS122AB/AD READ MODE The DS122AB and DS122AD execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 11 address inputs (A-A) defines which of the 248 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within t ACC (Access Time) after the last address input signal is stable, providing that the CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is either t CO for CE or t OE for OE rather than address access. WRITE MODE The DS122AB and DS122AD execute a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t WR ) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in t ODW from its falling edge. DATA RETENTION MODE The DS122AB provides full functional capability for V CC greater than 4.75 volts and write protects by 4.5V. The DS122AD provides full functional capability for V CC greater than 4.5 volts and write protects by 4.25V. Data is maintained in the absence of V CC without any additional support circuitry. The nonvolatile static RAMs cotantly monitor V CC. Should the supply voltage decay, the NV SRAMs automatically write protect themselves, all inputs become don t care, and all outputs become high impedance. As V CC falls below approximately 3. volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when V CC rises above approximately 3. volts, the power switching circuit connects external V CC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after V CC exceeds 4.75 volts for the DS122AB and 4.5 volts for the DS122AD. FRESHNESS SEAL Each DS122 device is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When V CC is first applied at a level of greater than V TP, the lithium energy source is enabled for battery backup operation. 2 of 9

3 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature DS122AB/AD -.3V to +7.V C to 7 C; -4 C to +85 C for IND parts -4 C to +7 C; -4 C to +85 C for IND parts 26 C for seconds This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operation sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods of time may affect reliability. RECOENDED DC OPERATING CONDITIONS (T A : See Note ) DS 122AB Power Supply Voltage V CC V DS 122AD Power Supply Voltage V CC V Logic 1 V IH 2.2 V CC V Logic V IL. +.8 V DC ELECTRICAL CHARACTERISTICS (V CC =5V ± 5% for DS122AB) (T A : See Note ) (V CC =5V ± % for DS122AD) Input Leakage Current I IL µa I/O Leakage Current -1. I IO CE V IH V CC +1. µa Output 2.4V I OH -1. ma Output I OL 2. ma Standby Current CE = 2.2V I CCS1 5.. ma Standby Current CE = V CC -.5V I CCS ma Operating Current t CYC =2 (Commercial) I CC1 75 ma Operating Current t CYC =2 (Industrial) I CCO1 85 ma Write Protection Voltage 4.5 V (DS122AB) TP V Write Protection Voltage 4.25 V (DS122AD) TP V CAPACITANCE (T A =25 C) Input Capacitance C IN 5 pf Input/Output Capacitance C I/O 5 12 pf 3 of 9

4 AC ELECTRICAL CHARACTERISTICS DS122AB/AD (V CC =5.V ± 5% for DS122AB) (T A : See Note ) (V CC =5.V ± % for DS122AD) PARAMETER SYMBOL DS122AB- DS122AD- DS122AB-12 DS122AD-12 MIN MAX MIN MAX Read Cycle Time t RC 12 Access Time t ACC 12 OE to Output Valid t OE 5 6 UNITS CE to Output Valid t CO 12 NOTES OE or CE to Output Active t COE Output High Z from 35 t Deselection OD 35 5 Output Hold from Address 5 t Change OH 5 Write Cycle Time t WC 12 Write Pulse Width t WP Address Setup Time t AW Write Recovery Time t WR1 t WR Output High from WE t ODW Output Active from WE t OEW Data Setup Time t DS Data Hold Time t DH1 t DH of 9

5 AC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL DS122AB-15 DS122AD-15 DS122AB-2 DS122AD-2 UNITS MIN MAX MIN MAX Read Cycle Time t RC 15 2 Access Time t ACC 15 2 OE to Output Valid t OE 7 CE to Output Valid t CO 15 2 DS122AB/AD (cont d) NOTES OE or CE to Output Active t COE Output High Z from 35 t Deselection OD 35 5 Output Hold from Address 5 t Change OH 5 Write Cycle Time t WC 15 2 Write Pulse Width t WP 15 3 Address Setup Time t AW Write Recovery Time t WR1 t WR Output High Z from WE t ODW Output Active from WE t OEW Data Setup Time t DS Data Hold Time t DH1 t DH of 9

6 READ CYCLE DS122AB/AD SEE NOTE 1 WRITE CYCLE 1 SEE NOTES 2, 3, 4, 6, 7, 8 AND 12 WRITE CYCLE 2 SEE NOTES 2, 3, 4, 6, 7, 8 AND 13 6 of 9

7 POWER-DOWN/POWER-UP CONDITION DS122AB/AD SEE NOTE 11 POWER-DOWN/POWER-UP TIMING (t A : See Note ) CE at V IH before Power-Down t PD µs 11 V CC slew from V TP to v t F 3 µs V CC slew from V to V TP t R 3 µs CE at V IH after Power-Up t REC ms (T A =25 C) Expected Data Retention Time t DR years 9 WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in the battery backup mode. NOTES: 1. WE is high for a read cycle. 2. OE = V IH or V IL. If OE = V IH during write cycle, the output buffers remain in a high-impedance state. 3. t WP is specified as the logical AND of CE and WE. t WP is measured from the latter of CE or CE going low to the earlier of CE or WE going high. 4. t DS is measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5 pf load and are not % tested. 6. If the CE low traition occurs simultaneously with or later than the WE low traition, the output buffers remain in a high-impedance state during this period. 7 of 9

8 DS122AB/AD 7. If the CE high traition occurs prior to or simultaneously with the WE high traition, the output buffers remain in a high-impedance state during this period. 8. If WE is low or the WE low traition occurs prior to or simultaneously with the CE low traition, the output buffers remain in a high-impedance state during this period. 9. Each DS122AB and each DS122AD has a built-in switch that disconnects the lithium source until V CC is first applied by the user. The expected t DR is defined as accumulative time in the absence of V CC starting from the time power is first applied by the user.. All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial products, this range is C to 7 C. For industrial products (IND), this range is -4 C to +85 C. 11. In a power down condition the voltage on any pin may not exceed the voltage on V CC. 12. t WR1, t DH1 are measured from WE going high. 13. t WR2, t DH2 are measured from CE going high. 14. DS122AB and DS122AD modules are recognized by Underwriters Laboratory (U.L. ) under file E DC TEST CONDITIONS Outputs Open All Voltages Are Referenced to Ground AC TEST CONDITIONS Output Load: pf + 1TTL Gate Input Pulse Levels: - 3.V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5 ORDERING INFORMATION 8 of 9

9 DS122AB/AD DS122AB/AD NONVOLATILE SRAM, 24-PIN 72-MIL EXTENDED MODULE PKG 24-PIN DIM MIN MAX A IN B IN C IN D IN E IN F IN G IN H IN J IN K IN of 9

DS1225Y 64k Nonvolatile SRAM

DS1225Y 64k Nonvolatile SRAM 19-5603; Rev 10/10 NOT RECOMMENDED FOR NEW DESIGNS 64k Nonvolatile SRAM www.maxim-ic.com FEATURES 10 years minimum data retention in the absence of external power Data is automatically protected during