Maximizing Endurance of MSC1210 Flash Memory

Transcription

1 Application Report SBAA91 April 23 Maximizing Endurance of MSC121 Flash Memory Ramesh Saripalli ABSTRACT Data Acquisition Products Microsystems The MSC121 embeds an 851 CPU, a high-performance, delta-sigma, 24-bit analog-todigital converter (ADC), 4/8/16/32K bytes flash memory (Flash) and other peripherals to give a system on-chip solution for high-precision data acquisition systems [1]. The endurance the number of times Flash can be erased and reprogrammed without failure is an important feature of Flash. This application report presents how to maximize the endurance of MSC121 Flash and also discusses the data retention specifications of the MSC121. Contents Introduction... 2 MSC121 Flash Technology and System... 2 Endurance... 2 Endurance Mechanism... 3 System Setup... 3 Measurement Procedure... 3 Erase/Program Operations... 3 Pattern... 3 Parameters... 4 Sample Size... 4 Firmware... 4 Endurance Results... 5 Temperature... 5 Voltage... 6 Erase Time... 7 Maximizing the Endurance... 7 Data Retention... 8 Appendix A: Table of Endurance Results for Different Test Conditions... 9 Appendix B: Graphs for Different Test Conditions... 1 Appendix C: Data Retention at Different Junction Temperatures References

2 Introduction Flash microcontrollers and Flash are popular these days. These devices can be programmed and erased in system. Flash can be programmed the same way as the EEPROM, however, Flash can be erased electrically, whereas, EPROM must be erased using a UV eraser. The memory is called flash because part or all of these devices can be erased in a flash. When compared to EEPROM, Flash offers higher performance, lower power consumption, and significant cost savings. The MSC121 family uses Flash for both data and code memory. MSC121 Flash Technology and System The MSC121 family uses NOR-type Flash. NOR Flash has large sector size and cell size, highspeed rewrite, and high-speed random data access. NOR devices use hot electron injection for data writing and tunnel release for erasing. Figure 1 shows the Flash system of the MSC121 from the user s perspective. You can write to the FTCON register [1] to modify the erase and write time of Flash. The Flash commands call the Flash subroutines in the internal boot ROM, which sends the signals to the Flash Controller. The controller executes commands like Flash Write, Flash Read, Flash Erase and Page Erase on the flash memory. Flash Commands Boot ROM Flash Controller 32K Bytes Flash Data and Program Memory FTCON 128 Bytes Flash HCR Figure 1. User s View of a Flash Memory System Main Flash Storage: 32K bytes (Y5), 16K bytes (Y4), 8K bytes (Y3), and 4K bytes (Y2) Configuration Flash Storage: 128 bytes Erase/Write Storage Value: Erase to all 1s; valid write value ; write 1 has no effect. Flash Structure: NOR-type Flash Page Size: 128 bytes Read Time: Minimum of 3ns (~33MHz CPU clock) Write Time: 3µs ~4µs Page/Mass Erase Time: 4ms Power Supply: 2.7V~5.25V DVDD for all operations (read/write/page erase/mass erase) Endurance Like their EEPROM counterparts, Flash devices have a limited number of erase/write cycles they can withstand without failure. The reason for the limitation depends on either charge trapping characteristics or the dielectric breakdown characteristics of the charge transfer oxides. This introduces a term called endurance. Endurance is a measure of the number of erase/write cycles that a Flash array can achieve while retaining data integrity. The endurance of Flash is a function of many parameters, the most important being temperature, voltage, erase-time, and write-time. 2 Maximizing Endurance of MSC121 Flash Memory

3 Endurance Mechanism To find out how to maximize the endurance of the MSC121, we need to perform an endurance test with varying parameters, and analyze the data to determine how they affect the endurance. System Setup PC or Host RS232 Master Board 37-Pin Connector Gang Board Oven Temp 4 C~85 C Figure 2. System Setup for Performing an Endurance Test The system setup to perform the endurance testing is shown in Figure 2. A master board connects to the PC through RS232 for serial communications. The PC is used to select the options, start the test, and display the results. The master board has an MSC121, which receives the signals from the PC and starts sending the Flash commands to the slaves sitting on the gang board. Each gang board can hold up to ten MSC121s, and a total of eight gang boards can be connected to the master board at the same time, giving us the flexibility to test 1 to 8 chips at a time. The gang boards go into the oven and the test is performed at varying temperatures. In order to perform the test at 3V and 5V, the gang and master boards have hardware support to run at these voltages. Flash-erase and Flash-write times are user-modifiable and can be programmed before running the test. If more accurate data is needed, the software gives the option of performing the test on more than one page for the same test conditions. Measurement Procedure The endurance test is performed without violating the Flash data retention specifications. The minimum required write-time of 3µs and erase-time of 4ms must be maintained in order to meet the data retention specifications of 1 years. The measurement procedure to find out the endurance is followed in accordance with the JEDEC specification [2]. Erase/Program Operations Pattern Flash can be erased either as a whole or by one page at a time (a page being 128 bytes). The test is performed on one page at a time. The sequences of operations that are performed to get the endurance are page-erase and then page-write. This procedure is performed until either page-erase or any one of the write operations fails. In MSC121 Flash technology, a charge is injected when you erase Flash (logic 1), and is discharged when you write Flash (logic ). Writing the bit to logic 1 does not perform any action, as the charge is already injected when it is erased. It is unknown if the ability of the gate in trapping the electrons is destroyed by injection of a charge, or by discharging. Therefore, each data bit location in Flash is programmed to a different value than what was programmed previously, in order to do average work on that bit location. The algorithm for Flash pattern generation for a page is shown in List 1. Maximizing Endurance of MSC121 Flash Memory 3

4 Parameters While(!Test Fail) { Write_value=xAA; For(i=;i<128;i++) { // Procedure call for writing the data location pointed by the address ( addr_hi, addr_low ) with Write_value. Flash write(addr_hi, addr_low, write_value ); Addr_low++; } Write_value=write_value^xFF; // Changing xaa (x55) to x55 (xaa) } List 1. Pattern Generation for Writing to the Page Endurance is a function of temperature, voltage, erase time, and write time. The experiment was performed varying these parameters. In the initial test results, it was observed that changing the write time, ranging 3µs~6µs, does not change the endurance as much as the other parameters. Therefore, write time is not changed during the course of experiment and is fixed to 3µs. The experiment is repeated with different temperatures, voltages, and erase-times. The different test conditions are shown in Table 1. -4, 27, 85 Voltage (V) 5, 3 Erase Time (ms) 4, 11 Table 1. List of All the Different Test Conditions for Endurance Testing Because the MSC121 allows you to control the erase/write times, the external clock frequency of the device does not need to be changed in order to change these parameters. Sample Size Firmware To get credible information on the endurance of MSC121 we ran the test on ten different parts for each test condition. The Flash commands issued by the master to the slave devices call the subroutines from the boot ROM. Therefore, it is very important to note how the boot ROM routines work [3]. The two routines that are used for endurance measurement are Flash write and Flash page-erase. Flash Write: This subroutine is called by the Flash write command. It attempts to write a byte of data to Flash at the specified address. The routine reads back the data after writing and verifies if the write was successful. If successful, it then sets the pass flag. Otherwise, it tries again for a maximum of three attempts. If after three attempts the write is still not successful, a fail flag is returned. Flash Page-Erase: This subroutine is called by the Flash page-erase command. It attempts to erase the page at the specified address. After page-erase is done, the routine reads the first byte of the page and verifies it with xffh. If it matches, then the pass flag is set and the routine exits. Otherwise, it tries again for a maximum of three attempts. If after three attempts the write is still not successful, a fail flag is returned. 4 Maximizing Endurance of MSC121 Flash Memory

5 Endurance Results The results of the endurance test for different temperatures, voltages and erase times are presented in Appendix A. For each test condition, the results from the ten chips are collected. The mean and standard deviation (SD) of the endurance within the sample size is calculated and tabulated. Temperature The effect of temperature on endurance is significant. From the experimental results presented in Appendix A and from the graph in Figure 3, we can see that Flash endurance increases with an increase in temperature. The same relationship exists in all the graphs for different test conditions. The graph shown in Figure 3 is for 5V and 11ms erase time. Endurance (Erase/Write Cycles) Performance (5V) Mean Mean+SD Mean-SD Temperature( C) Figure 3. Endurance Results Over a Temperature Range at 5V and 11ms of Erase Time The graph of Figure 3 plots the endurance results over the temperature range and also shows the mean +SD and mean -SD as a reference. The maximum endurance of 3.8 million cycles is attained at 85 C. Interestingly, it is also observed that the standard deviation of the endurance increases as the temperature increases. That can be seen in Figure 3; the distance between the points of the three curves increases as the temperature increases. Maximizing Endurance of MSC121 Flash Memory 5

6 Voltage Flash endurance increases as the voltage increases. This effect can be explained by the use of a charge pump at higher voltages, which helps in inducing more charges into the tunnel oxide. Figure 4 shows the endurance for 3V and 5V at 11ms. It shows that the endurance at all temperature points has increased as the voltage increased. Endurance Performance for Different Voltages No Of Cycles V 3V Figure 4. Endurance Performance for Different Voltages at an 11ms Erase Time For each temperature and erase time, the endurance measured for 3V and 5V is tabulated, and the percentage increase in endurance with respect to the endurance at 3V is calculated, and is tabulated in Table 2. It is observed that the percentage increase in the endurance is significant (close to 85%) as the voltage is increased from 3V to 5V. Endurance at 3V Endurance at 5V Percentage Increase in Endurance Test Condition (Number of Cycles) (Number of Cycles) (%) -4 C and 11ms erase time C and 11ms erase time C and 11ms erase time Table 2. Percentage Increase in Endurance vs Voltage 6 Maximizing Endurance of MSC121 Flash Memory

7 Erase Time Flash endurance increases with an increase in erase time. This can be explained by the longer amount of time it takes to charge the memory cells during erase. The charge pump is used for longer periods, and thus, helps in trapping more charge in the tunnel oxide. However, prolonged use of the charge pump at higher voltages degrades the gate oxide, and thereby decreases endurance. It is not known which parameter has more effect, but endurance increased as erase time increased. Figure 5 shows the endurance performance for 5V with different erase times. Endurance Performance for Different Erase Times ms 4ms Figure 5. Endurance Performance for Different Erase Times at 5V It can be seen from Figure 5 that the effect of erase time seems to be insignificant at lower temperatures, but becomes significant as temperature increases. The same effect is observed at 3V, as shown in Appendix B, Figure 1. An increase in erase time does not have the same effect as an increase in voltage, but the percentage increase in endurance is still significant and is in the range of 2% to 4%. Maximizing the Endurance From the results acquired, the following observations can be made: Increasing the voltage increases the endurance. Increasing the erase time increases the endurance. Increasing the temperature increases the endurance. If the user wants to maximize endurance, the MSC121 has to operate at a higher voltage, and the erase time must be set to a minimum of 1ms by setting the FTCON register. The Flash write and erase routines must be used from the boot ROM to achieve the results that are presented. No additional code is required by the user to achieve the results. Additionally, by being able to control the ambient temperature, better endurance results can be achieved. The user can also estimate the endurance for their conditions. It is very important to note that the results, and the predictions of the results, are within the test condition limits, and these results cannot be used to extrapolate outside the these limits. Maximizing Endurance of MSC121 Flash Memory 7

8 Data Retention The basic requirement for Flash is that of data retention. Flash must ensure a period over which the data will be retained by the device. The data retention strongly depends on the temperature. Data retention is defined as trying to maintain a logic value in the storage medium over a period of time. The data retention test is performed at higher temperatures for a lesser duration of time so that the results can be extrapolated using the Arrhenius equation 1 at lower temperatures. Data retention of MSC121 Flash was performed at 25 C for 1 hours, and the results showed that none of the parts failed for retention. The graph in Figure 6 plots the data retention in years over junction temperature and the tabulated data is presented in Appendix C, Table 4. Data retention at 3 C junction temperature is 244 years. Data Retention Over Temperature Retention (Years) Tj Junction Figure 6. Data Retention in Years over Junction Temperature NOTE: A minimum of 3µs for Flash write operation and a minimum of 4ms for Flash erase (mass/page) operation are required for the data retention values specified in Appendix C to be valid. (1) t1 = t exp[(q/k) (1/T1 1/T)] Where: t = Test Duration at temp T t1 = Equivalent Duration at temp T1 Q = Activation Energy (ev) k = Boltzmann Constant T = Test Temperature (K) T1 = Extrapolation Temperature (K) 8 Maximizing Endurance of MSC121 Flash Memory

9 Appendix A: Table of Endurance Results for Different Test Conditions Table 3 shows the endurance for different test conditions. The graphs for the data are shown in Appendix B. Temperature ( C) Erase Time (ms) Voltage (V) Mean (No. of Cycles) SD (No. of Cycles) Table 3. Endurance Results for Different Test Conditions Maximizing Endurance of MSC121 Flash Memory 9

10 Appendix B: Graphs for Different Test Conditions Endurance (Erase/Write Cycles) Performance (3V) Figure 7. Endurance Results at 3V and 4ms Erase Time Endurance (Erase/Write Cycles) Performance (3V) Figure 8. Endurance Results at 3V and 11ms Erase Time Endurance (Erase/Write Cycles) Performance (5V) Endurance Variations on Erase Time ms 4ms Figure 9. Endurance Results at 5V and 4ms Erase Time Figure 1. Endurance Performance for Different Erase Times at 3V Endurace Variations on Voltage V 3V Figure 11. Endurance Performance for Different Voltages at 4ms Erase Time 1 Maximizing Endurance of MSC121 Flash Memory

11 Appendix C: Data Retention at Different Junction Temperatures The difference between junction and ambient temperatures can be calculated using θ JA [1] and the power dissipated by the chip. Once the ambient temperature is known, the data retention can be calculated from the graph plotted in Figure 6. Temperature ( C) Data Retention (In Years) Table 4. Data Retention at Different Junction Temperatures References [1] MSC121 Data Sheet [2] JEDEC Standard EEPROM Program/Erase Endurance and Data Retention Test JESD22-A117 [3] MSC121: ROM Routines SBAA85 [4] MSC121: In-Application Flash Programming SBAA87 Maximizing Endurance of MSC121 Flash Memory 11

12 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box Dallas, Texas Copyright 23, Texas Instruments Incorporated