SN54LVTH16374, SN74LVTH V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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1 Members of the Texas Instruments Widebus Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Voltages With 3.3-V ) Support Unregulated Battery Operation Down to Typical V OLP ( Ground Bounce) <0.8 V at = 3.3 V, T A = 25 C I off and Power-Up 3-State Support Hot Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Distributed and Pins Minimize High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 ma Per JESD 17 ESD Protection Exceeds JESD V Human-Body Model (A114-A) 200-V Machine Model (A115-A) SN54LVTH WD PACKAGE SN74LVTH DGG OR DL PACKAGE (TOP VIEW) 1OE 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2OE CLK 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2CLK description The LVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for low-voltage (3.3-V) operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK), the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2001, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX DALLAS, TEXAS

2 description (continued) When is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using I off and power-up 3-state. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. A B C D E F G H J K GQL PACKAGE (TOP VIEW) terminal assignments A 1OE NC NC NC NC 1CLK B 1Q2 1Q1 1D1 1D2 C 1Q4 1Q3 VCC VCC 1D3 1D4 D 1Q6 1Q5 1D5 1D6 E 1Q8 1Q7 1D7 1D8 F 2Q1 2Q2 2D2 2D1 G 2Q3 2Q4 2D4 2D3 H 2Q5 2Q6 VCC VCC 2D6 2D5 J 2Q7 2Q8 2D8 2D7 K 2OE NC NC NC NC 2CLK NC No internal connection ORDERING INFORMATION TA 40 C to85 C SSOP DL PACKAGE Tube Tape and reel ORDERABLE PART NUMBER SN74LVTH16374DL SN74LVTH16374DLR TOP-SIDE MARKING LVTH16374 TSSOP DGG Tape and reel SN74LVTH16374DGGR LVTH16374 VFBGA GQL Tape and reel SN74LVTH16374GQLR LL C to 125 C CFP WD Tube SNJ54LVTH16374WD SNJ54LVTH16374WD Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at FUNCTION TABLE (each flip-flop) INPUTS OUTPUT OE CLK D Q L H H L L L L H or L X Q0 H X X Z 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 logic diagram (positive logic) 1OE 1 2OE 24 1CLK 48 2CLK 25 1D1 47 C1 1D 2 1Q1 2D1 36 C1 1D 13 2Q1 To Seven Other Channels To Seven Other Channels Pin numbers shown are for the DGG, DL, and WD packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V to 4.6 V Input voltage range, V I (see Note 1) V to 7 V Voltage range applied to any output in the high-impedance or power-off state, V O (see Note 1) V to 7 V Voltage range applied to any output in the high state, V O (see Note 1) V to V Current into any output in the low state, I O : SN54LVTH ma SN74LVTH ma Current into any output in the high state, I O (see Note 2): SN54LVTH ma SN74LVTH ma Input clamp current, I IK (V I < 0) ma clamp current, I OK (V O < 0) ma Package thermal impedance, θ JA (see Note 3): DGG package C/W DL package C/W GQL package C/W Storage temperature range, T stg C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD recommended operating conditions (see Note 4) SN54LVTH16374 SN74LVTH16374 MIN MAX MIN MAX VCC Supply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V VI Input voltage V IOH High-level output current ma IOL Low-level output current ma t/ v Input transition rise or fall rate s enabled ns/v t/ VCC Power-up ramp rate µs/v TA Operating free-air temperature C NOTE 4: All unused control inputs of the device must be held at VCC or to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX DALLAS, TEXAS

4 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54LVTH16374 SN74LVTH16374 MIN TYP MAX MIN TYP MAX VIK VCC =, II = 18 ma V II VCC = to 3.6 V, IOH = 100 µa VCC 0.2 VCC 0.2 VCC =, IOH = 8 ma VCC =3V VCC =27V CC =3V IOH = 24 ma 2 IOH = 32 ma 2 IOL = 100 µa IOL = 24 ma IOL = 16 ma IOL = 32 ma IOL = 48 ma 0.55 IOL = 64 ma 0.55 VCC = 0 or 3.6 V, VI = 5.5 V Control inputs VCC = 3.6 V, VI = VCC or ±1 ±1 Data inputs VCC =36V 3.6 VI = VCC 1 1 VI = Ioff VCC = 0, VI or VO = 0 to 4.5 V ±100 µa II(hold) Data inputs VCC =3V VI = 0.8 V VI = 2 V µa VCC = 3.6 V, VI = 0 to 3.6 V ±500 IOZH VCC = 3.6 V, VO = 3 V 5 5 µa IOZL VCC = 3.6 V, VO = 0.5 V 5 5 µa IOZPU IOZPD ICC VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don t care VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don t care V V µa ±100 ±100 µa ±100 ±100 µa s high VCC = 3.6 V, IO = 0, s low 5 5 ma VI = VCC or s disabled ICC VCC = 3 V to 3.6 V, One input at VCC 0.6 V, Other inputs at VCC or ma Ci VI = 3 V or pf Co VO = 3 V or pf On products compliant to MIL-PRF-38535, this parameter is not production tested. All typical values are at VCC = 3.3 V, TA = 25 C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or. 4 POST OFFICE BOX DALLAS, TEXAS 75265

5 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVTH16374 VCC = 3.3 V VCC = SN74LVTH16374 VCC = 3.3 VCC = MIN MAX MIN MAX MIN MAX MIN MAX fclock Clock frequency MHz tw Pulse duration, CLK high or low ns tsu Setup time, data before CLK High or low ns th Hold time, data after CLK High or low ns switching characteristics over recommended operating free-air temperature range, C L = 50 pf (unless otherwise noted) (see Figure 1) SN54LVTH16374 SN74LVTH16374 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V VCC = VCC = 3.3 V VCC = MIN MAX MIN MAX MIN TYP MAX MIN MAX fmax MHz tplh tphl CLK Q ns tpzh tpzl OE Q ns tphz tplz OE Q ns tsk(o) 0.5 ns All typical values are at VCC = 3.3 V, TA = 25 C. POST OFFICE BOX DALLAS, TEXAS

6 PARAMETER MEASUREMENT INFORMATION From Under Test CL = 50 pf (see Note A) 500 Ω 500 Ω S1 6 V Open TEST tplh/tphl tplz/tpzl tphz/tpzh S1 Open 6 V LOAD CIRCUIT Timing Input 1.5 V Input tw Data Input tsu th PULSE DURATION SETUP AND HOLD TIMES Input Control tplh tphl Waveform 1 S1 at 6 V (see Note B) tpzl 1.5 V tplz 3 V V tphl tplh PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Waveform 2 S1 at (see Note B) tpzh 1.5 V tphz ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING 0.3 V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box Dallas, Texas Copyright 2001, Texas Instruments Incorporated

SN54LVTH16240, SN74LVTH V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SN54LVTH16240, SN74LVTH V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS Members of the Texas Instruments Widebus Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input