2-WIRE. 64K Bits. Serial EEPROM

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1 G WIRE 64 Bits erial EEPROM opyright 2011 Giantec emiconductor Inc. (Giantec). ll rights reserved. Giantec reserves the right to make changes to this specification and its products at any time without notice. Giantec products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equipment, aerospace or military, or other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for the best performance and optimization on the functionality and etc. Giantec assumes no liability arising out of the application or use of any information, products or services described herein. ustomers are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for products. 4 1/23

2 able of ontents 1. Features General Description Functional Block Diagram Pin onfiguration Pin OI, OP, PDIP and MOP Lead UDFN Pin Definition Pin Descriptions Device Operation WIRE Bus he Bus Protocol tart ondition top ondition cknowledge Reset tandby Mode Device ddressing Write Operation Read Operation Diagrams iming Diagrams Electrical haracteristics bsolute Maximum Ratings Operating Range apacitance D Electrical haracteristic Electrical haracteristic Ordering Information op Markings OI package OP package PDIP package UDFN package MOP package Package Information OI OP PDIP UDFN MOP Revision History /23

3 1. Features wo-wire erial Interface, I 2 M ompatible Bi-directional data transfer protocol Wide-voltage Operation V = 1.7V to 5.5V peed: 400 Hz (1.7V) and 1 MHz (2.5V~5.5V) tandby current (max.): 1, 1.7V Operating current (max.): 3 m, 5.5V Hardware Data Protection Write Protect Pin equential & Random Read Features Memory organization: 64b (8,192 x 8) Page ize: 32 bytes Page write mode Partial page writes allowed elf timed write cycle: 5 ms (max.) Noise immunity on inputs, besides chmitt trigger High-reliability Endurance: 1 million cycles Data retention: 100 years Industrial grade Packages: OI, OP, PDIP, UDFN, MOP and P Lead-free, RoH, Halogen free, Green 2. General Description he G2464 is an industrial standard electrically erasable programmable read only memory (EEPROM) device that utilizes the industrial standard 2-wire interface for communications. he G2464 contains a memory array of 64 bits (8,192x8), which is organized in 32-byte per page. he EEPROM operates in a wide voltage range from 1.7V to 5.5V, which fits most application. he product provides low-power operations and low standby current. he device is offered in Lead-free, RoH, halogen free or Green package. he available package types are 8-pin OI, OP, PDIP, UDFN, MOP and P. he G2464 is compatible to the standard 2-wire bus protocol. he simple bus consists of erial lock (L) and erial Data (D) signals. Utilizing such bus protocol, a Master device, such as a microcontroller, can usually control one or more lave devices, alike this G2464. he bit stream over the D line includes a series of bytes, which identifies a particular lave device, an instruction, an address within that lave device, and a series of data, if appropriate. he G2464 also has a Write Protect function via WP pin to cease from overwriting the data stored inside the memory array. In order to refrain the state machine from entering into a wrong state during power-up sequence or a power toggle off-on condition, a power on reset circuit is embedded. During power-up, the device does not respond to any instructions until the supply voltage (V ) has reached an acceptable stable level above the reset threshold voltage. Once V passes the power on reset threshold, the device is reset and enters into the tandby mode. his would also avoid any inadvertent Write operations during power-up stage. During power-down process, the device will enter into standby mode, once V drops below the power on reset threshold voltage. In addition, the device will be in standby mode after receiving the top command, provided that no internal write operation is in progress. Nevertheless, it is illegal to send a command unless the V is within its operating level. 4 3/23

4 3. Functional Block Diagram V 8 HIGH VOLGE GENEROR IMING & ONROL D L WP LVE DDRE REGIER & OMPROR ONROL LOGI X DEODER EEPROM RRY WORD DDRE OUNER Y DEODER GND 4 nmo LO DI/O D REGIER 4 4/23

5 4. Pin onfiguration Pin OI, OP, PDIP and MOP Lead UDFN op View op View V V WP WP L L GND 4 5 D GND 4 5 D 4.3 Pin Definition Pin No. Pin Name I/O Definition 1 0 I Device ddress Input 2 1 I Device ddress Input 3 2 I Device ddress Input 4 GND - Ground 5 D I/O erial ddress and Data input and Data out put 6 L I erial lock Input 7 WP I Write Protect Input 8 V - Power upply 4.4 Pin Descriptions L his input clock pin is used to synchronize the data transfer to and from the device. D he D is a bi-directional pin used to transfer addresses and data into and out of the device. he D pin is an open drain output and can be wired with other open drain or open collector outputs. However, the D pin requires a pull-up resistor connected to the power supply. 0, 1, 2 he 0, 1 and 2 are the device address inputs. ypically, the 0, 1, and 2 pins are for hardware addressing and a total of 8 devices can be connected on a single bus system. When 0, 1, and 2 are left floating, the inputs are defaulted to zero. WP WP is the Write Protect pin. While the WP pin is connected to the power supply of G2464, the entire array becomes Write Protected (i.e. the device becomes Read only). When WP is tied to Ground or left floating, the normal write operations are allowed. V upply voltage GND Ground of supply voltage 4 5/23

6 5. Device Operation he G2464 serial interface supports communications using industrial standard 2-wire bus protocol, such as I WIRE Bus he two-wire bus is defined as erial Data (D), and erial lock (L). he protocol defines any device that sends data onto the D bus as a transmitter, and the receiving devices as receivers. he bus is controlled by Master device that generates the L, controls the bus access, and generates the tart and top conditions. he G2464 is the lave device. 5.2 he Bus Protocol Data transfer may be initiated only when the bus is not busy. During a data transfer, the D line must remain stable whenever the L line is high. ny changes in the D line while the L line is high will be interpreted as a tart or top condition. he state of the D line represents valid data after a tart condition. he D line must be stable for the duration of the High period of the clock signal. he data on the D line may be changed during the Low period of the clock signal. here is one clock pulse per bit of data. Each data transfer is initiated with a tart condition and terminated by a top condition. 5.3 tart ondition he tart condition precedes all commands to the device and is defined as a High to Low transition of D when L is High. he EEPROM monitors the D and L lines and will not respond until the tart condition is met. 5.4 top ondition he top condition is defined as a Low to High transition of D when L is High. ll operations must end with a top condition. 5.5 cknowledge fter a successful data transfer, each receiving device is required to generate an. he cknowledging device pulls down the D line. 5.6 Reset he G2464 contains a reset function in case the 2-wire bus transmission on is accidentally interrupted (e.g. a power loss), or needs to be terminated mid-stream. he reset is initiated when the Master device creates a tart condition. o do this, it may be necessary for the Master device to monitor the D line while cycling the L up to nine times. (For each clock signal transition to High, the Master checks for a High level on D.) 5.7 tandby Mode While in standby mode, the power consumption is minimal. he G2464 enters into standby mode during one of the following conditions: a) fter Power-up, while no Op-code is sent; b) fter the completion of an operation and followed by the top signal, provided that the previous operation is not Write related; or c) fter the completion of any internal write operations. 5.8 Device ddressing he Master begins a transmission on by sending a tart condition, then sends the address of the particular lave devices to be communicated. he lave device address is 8 bits format as shown in Figure he four most significant bits of the lave address are fixed (1010) for G2464. he next three bits, 0, 1 and 2, of the lave address are specifically related to EEPROM. Up to eight G2464 units can be connected to the 2-wire bus. he last bit of the lave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, Read operation is selected. While it is set to 0, Write operation is selected. fter the Master transmits the tart condition and lave address byte appropriately, the associated 2-wire lave device, G2464, will respond with on the D line. hen G2464 will pull down the D on the ninth clock cycle, signaling that it received the eight bits of data. he G2464 then prepares for a Read or Write operation by monitoring the bus. 5.9 Write Operation Byte Write In the Byte Write mode, the Master device sends the tart 4 6/23

7 condition and the lave address information (with the R/W set to Zero) to the lave device. fter the lave generates an, the Master sends the byte address that is to be written into the address pointer of the G2464. fter receiving another from the lave, the Master device transmits the data byte to be written into the address memory location. he G2464 acknowledges once more and the Master generates the top condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device Page Write he G2464 is capable of 32-byte Page-Write operation. Page-Write is initiated in the same manner as a Byte Write, but instead of terminating the internal Write cycle after the first data word is transferred, the Master device can transmit up to 31 more bytes. fter the receipt of each data word, the EEPROM responds immediately with an on D line, and the five lower order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. If a byte address is incremented from the last byte of a page, it returns to the first byte of that page. If the Master device should transmit more than 32 bytes prior to issuing the top condition, the address counter will roll over, and the previously written data will be overwritten. Once all 32 bytes are received and the top condition has been sent by the Master, the internal programming cycle begins. t this point, all received data is written to the G2464 in a single Write cycle. ll inputs are disabled until completion of the internal Write cycle cknowledge () Polling he disabling of the inputs can be used to take advantage of the typical Write cycle time. Once the top condition is issued to indicate the end of the host's Write operation, the G2464 initiates the internal Write cycle. polling can be initiated immediately. his involves issuing the tart condition followed by the lave address for a Write operation. If the EEPROM is still busy with the Write operation, no will be returned. If the G2464 has completed the Write operation, an will be returned and the host can then proceed with the next Read or Write operation Read Operation Read operations are initiated in the same manner as Write operations, except that the (R/W) bit of the lave address is set to 1. here are three Read operation options: current address read, random address read and sequential read urrent ddress Read he G2464 contains an internal address counter which maintains the address of the last byte accessed, incremented by one. For example, if the previous operation is either a Read or Write operation addressed to the address location n, the internal address counter would increment to address location n+1. When the EEPROM receives the lave ddressing Byte with a Read operation (R/W bit set to 1 ), it will respond an and transmit the 8-bit data byte stored at address location n+1. he Master should not acknowledge the transfer but should generate a top condition so the G2464 discontinues transmission. If 'n' is the last byte of the memory, the data from location '0' will be transmitted. (Refer to Figure 5-8. urrent ddress Read Diagram.) Random ddress Read elective Read operations allow the Master device to select at random any memory location for a Read operation. he Master device first performs a 'dummy' Write operation by sending the tart condition, lave address and byte address of the location it wishes to read. fter the G2464 acknowledges the byte address, the Master device resends the tart condition and the lave address, this time with the R/W bit set to one. he EEPROM then responds with its and sends the data requested. he Master device does not send an but will generate a top condition. (Refer to Figure 5-9. Random ddress Read Diagram.) equential Read equential Reads can be initiated as either a urrent ddress Read or Random ddress Read. fter the G2464 sends the initial byte sequence, the Master device now responds with an indicating it requires 4 7/23

8 R ONDIION OP ONDIION G2464 additional data from the G2464. he EEPROM continues to output data for each received. he Master device terminates the sequential Read operation by pulling D High (no ) indicating the last data word to be read, followed by a top condition. he data output is sequential, with the data from address n followed by the data from address n+1,n+2... etc. he address counter increments by 5.11 Diagrams one automatically, allow the entire memory contents to be serially read during sequential Read operation. When the memory address boundary of the array is reached, the address counter rolls over to address 0, and the device continues to output data. (Refer to Figure equential Read Diagram). Figure 5-1. ypical ystem Bus onfiguration V D L Master ransmitter/receiver G24XX Figure 5-2. output cknowledge L from Master Data Output from ransmitter Data Output from Receiver Figure 5-3. tart and top onditions L D 4 8/23

9 Figure 5-4. Data Validity Protocol Data hange L D Data table Data table Figure 5-5. lave ddress Bit R/W D Bus ctivity R M B Figure 5-6. Byte Write W R I Device ddress E Word ddress Word ddress Data * * * L B R/W M B * =Don t care bits O P Figure 5-7. Page Write D Bus ctivity R M B W R I Device ddress E Word ddress(n) Word ddress(n) Data(n) * * * L B R/W M B * =Don t care bits Data(n+1) Data(n+31) O P 4 9/23

10 Figure 5-8. urrent ddress Read D Bus ctivity R M B Device ddress L B R E D R/W Data N O O P Figure 5-9. Random ddress Read D Bus ctivity R M B Device ddress W R I Word E ddress(n) * * * L B R/W DUMMY WRIE Word ddress(n) * =Don t care bits R Device ddress R E D Data n N O O P Figure equential Read D Bus ctivity Device ddress R E D R/W Data Byte n Data Byte n+1 Data Byte n+2 Data Byte n+x N O O P 4 10/23

11 5.12 iming Diagrams Figure Bus iming R F HIGH LOW U:O L U: HD: HD:D U:D BUF DIN DH DOU U:WP HD:WP WP Figure Write ycle iming L D Word n WR OP ondition R ondition 4 11/23

12 6. Electrical haracteristics 6.1 bsolute Maximum Ratings ymbol Parameter Value Unit V upply Voltage -0.5 to V V P Voltage on ny Pin 0.5 to V V BI emperature Under Bias 55 to +125 G torage emperature 65 to +150 I OU Output urrent 5 m Note: tress greater than those listed under bsolute Maximum Ratings may cause permanent damage to the device. his is a stress rating only and functional operation of the device at these or any other condition outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 6.2 Operating Range Range mbient emperature () V Industrial 40 to V to 5.5V Note: Giantec offers Industrial grade for ommercial applications (0 to +70 ). 6.3 apacitance ymbol Parameter [1, 2] onditions Max. Unit IN Input apacitance V IN = 0V 6 pf I/O Input / Output apacitance V I/O = 0V 8 pf Notes: [1] ested initially and after any design or process changes that may affect these parameters and not 100% tested. [2] est conditions: = 25, f = 1 MHz, V = 5.0V. 4 12/23

13 6.4 D Electrical haracteristic Industrial: = 40 to +85, V = 1.7V ~ 5.5V ymbol Parameter [1] V est onditions Min. Max. Unit V upply Voltage V V IH Input High Voltage 0.7*V V +1 V V IL Input Low Voltage * V V I LI Input Leakage urrent 5 V V IN = V max 2 μ I LO Output Leakage urrent 5V 2 μ V OL1 Output Low Voltage 1.7V I OL = 0.15 m 0.2 V V OL2 Output Low Voltage 2.5V I OL = 2.1 m 0.4 V I B1 tandby urrent 1.7V V IN = V or GND 1 μ I B2 tandby urrent 2.5V V IN = V or GND 2 μ I B3 tandby urrent 5V V IN = V or GND 3 μ 1.7V Read at 400 Hz 1 m I 1 I 2 Read urrent 2.5V Read at 1 MHz 2 m 5.5V Read at 1 MHz 2 m 1.7V Write at 400 Hz 1 m Write urrent 2.5V Write at 1 MHz 2 m 5.5V Write at 1 MHz 3 m Note: he parameters are characterized but not 100% tested. 4 13/23

14 6.5 Electrical haracteristic Industrial: = 40 to +85, upply voltage = 1.7V to 5.5V ymbol Parameter [1] [2] 1.7V V<2.5V 2.5V V<4.5V 4.5V V 5.5V Unit Min. Max. Min. Max. Min. Max. F L lock Frequency Hz LOW lock Low Period ns HIGH lock High Period ns R Rise ime (L and D) ns F Fall ime (L and D) ns U: tart ondition etup ime ns U:O top ondition etup ime ns HD: tart ondition Hold ime ns U:D Data In etup ime ns HD:D Data In Hold ime ns DH lock to Output ccess time (L Low to D Data Out Valid) Data Out Hold ime (L Low to D Data Out hange) ns ns WR Write ycle ime ms BUF Bus Free ime Before New ransmission ns U:WP WP pin etup ime ns HD:WP WP pin Hold ime ns Notes: Noise uppression ime ns [1] he parameters are characterized but not 100% tested. [2] measurement conditions: R L (connects to V ): 1.3 kω (2.5V, 5.0V), 10 kω (1.7V) L = 100 pf Input pulse voltages: 0.3*V to 0.7*V Input rise and fall times: 50 ns iming reference voltages: half V level 4 14/23

15 7. Ordering Information Industrial Grade: -40 to +85, Lead-free Voltage Range Part Number* Package (8-pin)* 1.7V to 5.5V G2464-2GLI-R 150-mil OI G2464-2ZLI-R 3 x 4.4 mm OP G2464-2PLI 300-mil PDIP G2464-2UDLI-R 2 x 3 x 0.55 mm UDFN G2464-2LI-R 3 x 3 mm MOP G2464-2LI-R P * 1. ontact Giantec ales Representatives for availability and other package information. 2. he product is packed in tape and reel -R (4 per reel), except UDFN is 5 per reel. 3. Refer to Giantec website for related declaration document on lead free, RoH, halogen free or Green, whichever is applicable. 4. Giantec offers Industrial grade for ommercial applications (0 to +70 ). 4 15/23

G2464-2GLI-R YWW: Date ode, Y=year, WW=week

G2464-2ZLI-R YWW: Date ode, Y=year, WW=week

G2464-2PLI YWW: Date ode, Y=year, WW=week 8.

16 8. op Markings 8.1 OI package G: Giantec Logo 464-2GLI: G2464-2GLI-R YWW: Date ode, Y=year, WW=week 8.2 OP package G: Giantec Logo 464-2ZLI: G2464-2ZLI-R YWW: Date ode, Y=year, WW=week 8.3 PDIP package G: Giantec Logo PLI: G2464-2PLI YWW: Date ode, Y=year, WW=week 8.4 UDFN package G: Giantec Logo 46: G2464-2UDLI-R YWW: Date ode, Y=year, WW=week 4 16/23

17 8.5 MOP package G: Giantec Logo 4642LI: G2464-2LI-R YWW: Date ode, Y=year, WW=week 4 17/23

18 9. Package Information 9.1 OI 8L 150mil OI Package Outline Detail D E1 E ZD b Detail GUGE PLNE e 1 EING PLNE L1 L Θ YMBOL DIMENION IN MILLIMEER DIMENION IN INHE MIN NOM MX MIN NOM MX b D E E e L B B L1 ZD Θ B REF B REF Note: 1. ontrolling Dimension:MM 2. Dimension D and E1 do not include Mold protrusion 3. Dimension b does not include dambar protrusion/intrusion. 4. Refer to Jedec standard M Drawing is not to scale 4 18/23

19 9.2 OP 8L 3x4.4mm OP Package Outline 8 D e L E E (4X) Θ b mm Note: 1. ontrolling Dimension:MM 2. Dimension D and E do not include Mold protrusion 3. Dimension b does not include dambar protrusion/intrusion. 4. Refer to Jedec standard MO Drawing is not to scale 6. Package may have exposed tie bar. 1 YMBOL DIMENION IN MILLIMEER DIMENION IN INHE MIN NOM MX MIN NOM MX b c D E E1 e L B 0.65 B B B Θ /23

20 9.3 PDIP 8L 300mil PDIP Package Outline D E1 E eb ZD 2 1 L b3 e b Note: 1. ontrolling Dimension:MM 2. Dimension D and E1 do not include Mold protrusion 3. Dimension b2 and b3 do not include dambar protrusion/instrusion 4. Drawing is not to scale YMBOL DIMENION IN MILLIMEER DIMENION IN INHE MIN NOM MX MIN NOM MX b b b D E E e 2.54 B B. eb L ZD REF REF. 4 20/23

21 9.4 UDFN 8L 2x3mm UDFN Package Outline D D2 e E E2 L PIN#1 IDENIFIION HMFER PIN#1 DO BY MRING OP VIEW BOOM VIEW b 1 2 IDE VIEW YMBOL Note: DIMENION IN MILLIMEER DIMENION IN INHE MIN NOM MX MIN NOM MX b D D REF 2.00 B REF B E 3.00 B B E e B B L ontrolling Dimension:MM 2. Drawing is not to scale 4 21/23

22 9.5 MOP 8L 120mil MOP package Outline D e L E E1 12 (4X) 2 θ 1 b YMBOL DIMENION IN MILLIMEER DIMENION IN INHE MIN NOM MX MIN NOM MX b D E E1 e L B 0.65 B B B Θ Note: 1. ontrolling Dimension:MM 2. Dimension D and E do not include Mold protrusion 3. Refer to Jedec standard MO Drawing is not to scale 4 22/23

23 10. Revision History Revision Date Descriptions 0 Jan Initial version 1 Jun New datasheet format 2 Oct hange V from 1.8V to 1.7V 3 Oct Update u wire top marking 4 Oct Revise OI/OP to OI 4 23/23

GT24C64A 2-WIRE. 64K Bits. Serial EEPROM

GT24C64A 2-WIRE. 64K Bits. Serial EEPROM G2464 dvanced G2464 2-WIRE 64 Bits erial EEPROM opyright 2014 Giantec emiconductor Inc. (Giantec). ll rights reserved. Giantec reserves the right to make changes to this specification and its products