I 2 C-Compatible Serial E 2 PROM

Size: px

Start display at page:

Download "I 2 C-Compatible Serial E 2 PROM"

Chad Dorsey
5 years ago
Views:

1 P2428 I 2 -ompatible erial 2 P Data heet ev.. General Description he P2428 is a 28-bit I 2 -compatible erial P (lectrically rasable Programmable emory) device. It contains a memory array of 6 8 bits, which is organized in 64-byte per page. P2428 provides the following devices for different application. Device election able Device Name Voltage ange emp. ange ax. lock Frequency P2428-I.7V~5.5V -40 ~ 85 Hz [] P2428-N.8V~5.5V -40 ~05 Hz [] P2428-D 2.5V~5.5V -40 ~25 Hz Note : 400 khz for V < 2.5V. Features ingle upply Voltage and High peed inimum operating voltage down to.7v Hz clock from 2.5V to 5.5V 400kHz clock from.7v to 2.5V ow power technology ead current 400u, maximum rite current.6m, maximum chmitt rigger, Filtered Inputs for Noise uppression equential & andom ead Features 64 byte Page rite odes, Partial Page rites llowed rite protect of the whole memory array dditional rite ockable Page elf-timed rite ycle (5ms maximum) High eliability ndurance: illion rite ycles Data etention: 00 Years H: 6V atch up apability: +/- 200m (25 & 25 ) /9

2 P2428 Datasheet ev.. Package 8-Pin PDIP 8-Pin P 8-Pin P 8-Pin DFN. Pin onfiguration. Pin onfiguration Figure - Pin onfiguration 0 8 V P GND 4 5 D.2 Pin Definition able - Pin Definition Pin Name ype Description 0 I/ lave ddress etting 2 Input lave ddress etting 3 2 Input lave ddress etting 4 GND Ground Ground 5 D I/ erial Data Input and erial Data utput 6 Input erial lock Input 7 Input rite ontrol, ow nable rite 8 V Power Power Puya emiconductor 2/9

3 X -DD P2428 Datasheet ev...3 Pin Descriptions erial lock (): he input is used to positive-edge clock data in and negative-edge clock data out of each device. erial Data (D): he D pin is bidirectional for serial data transfer. his pin is open drain driven and may be wire-ed with any number of other open-drain or open-collector devices. Device ddresses (2,, 0): he 2,, and 0 pins are device address inputs. ypically, the 2,, and 0 pins are for hardware addressing and a total of 8 devices can be connected on a single bus system. If these pins are left floating, the 2,, and 0 pins will be internally pulled down to GND. rite ontrol (): he rite ontrol input, when is connected directly to V, all write operations to the memory are inhibited. hen connected to GND, allows normal write operations. If the pin is left floating, the pin will be internally pulled down to GND. 2. lock Diagram Figure 2- lock Diagram D tart top ontrol ogic erial us ontrol ogic N High Voltage Generator rite ontrol ogic H I N D Page Data atch 0 lave ddress omparator ddress ounter P Y 2 Dataut/ erial UX V GND Y-DD Puya emiconductor 3/9

4 P2428 Datasheet ev.. 3. I HII bsolute aximum atings torage emperature to +50 peration emperature to +25 aximum peration Voltage V Voltage on ny Pin with espect to Ground V to (Vcc+.0)V D utput urrent m NI: tresses above those listed under bsolute aximum atings may cause permanent damage to the device. his is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. xposure to maximum rating conditions for extended periods may affect device reliability. able 3- Pin apacitance [] ymbol Parameter ax. Units est ondition I/ Input/utput apacitance (D) 8 pf V I/ =GND IN Input apacitance (0,,2,,) 6 pf V IN =GND Note: [] est onditions: = 25, F = Hz, Vcc = 5.0V. able 3-2 D haracteristics(unless otherwise specified, V =.7V to 5.5V, = 40 to 25 ) ymbol Parameter in. yp. ax. Unit est ondition V P2428-I V upply Voltage V P2428-N V P2428-D u Vcc = 3.3V, = 85 Isb tandby urrent u Vcc = 5.5V, = u Vcc = 5.5V, = u Vcc = 5.5V, = 25 I upply urrent m Vcc=5.5V, ead at 400hz I 2 upply urrent m Vcc=5.5V rite at 400hz I I Input eakage urrent µ V IN = V or GND I utput eakage urrent µ V U = V or GND V I Input ow evel V V V IH Input High evel 0.7V - V +0.5 V V V 2 utput ow evel V =.7V (D) V I =.5 m utput ow evel V = 3.0V (D) V I = 2. m Puya emiconductor 4/9

5 P2428 Datasheet ev.. able 3-3 haracteristics(unless otherwise specified, V =.7V to 5.5V, = 40 to 25, =00pF, est onditions are listed in Notes [2] ) ymbol Parameter.7 V < V 5.5 in. yp. ax. in. yp. ax. f lock Frequency, khz t lock Pulse idth ow µs t HIGH lock Pulse idth High µs t lock ow to Data ut Valid µs t I Noise uppression ime µs t UF ime the bus must be free before a new transmission can start Units µs t HD. tart Hold ime µs t U. tart etup ime µs t HD.D Data In Hold ime µs t U.D Data In etup ime µs t Inputs ise ime [] µs t F Inputs Fall ime [] µs t U. top etup ime µs t DH Data ut Hold ime µs t U. pin etup ime µs t HD. pin Hold ime µs t rite ycle ime ms Notes: [] his parameter is ensured by characterization not 00% tested [2] measurement conditions: (connects to V ):.3k (2.5V, 5.5V), 0k (.7V) Input pulse voltages: 0.3 V to 0.7 V Input rise and fall times: 50ns Input and output timing reference voltages: 0.5V able 3-4 eliability haracteristic [] ymbol Parameter in. yp. ax. Unit D [2] ndurance,000,000 rite cycles D Data retention 00 Years Note: [] his parameter is ensured by characterization and is not 00% tested [2] Under the condition: 25, 3.3V, Page mode Puya emiconductor 5/9

6 P2428 Datasheet ev.. Figure 3- us iming t t F t HIGH t t U. t HD. t HD.D t U.D t U. D(IN) t t DH t UF D(U) t U. t HD. Figure 3-2 rite ycle iming D D0 t P onditon onditon Note: [] he write cycle time t is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. Puya emiconductor 6/9

7 P2428 Datasheet ev.. 4. Device peration 4. Data Input he D pin is normally pulled high with an external device. Data on the D pin may change only during low time periods (see to Figure 4-). Data changes during high periods will indicate a start or stop condition as defined below. Figure 4- Data Validity D Data table Data hange Data table 4.2 tart ondition high-to-low transition of D with high is a start condition which must precede any other command (see to Figure 4-2). 4.3 top ondition low-to-high transition of D with high is a stop condition. fter a read sequence, the stop command will place the P2428 in a standby power mode (see Figure 4-2). Figure 4-2 tart and top Definition D tart top Puya emiconductor 7/9

8 P2428 Datasheet ev cknowledge () ll addresses and data words are serially transmitted to and from the P2428 in 8-bit words. he P2428 sends a 0 to acknowledge that it has received each word. his happens during the ninth clock cycle. Figure 4-3 utput cknowledge D cknowledge 4.5 tandby ode he P2428 features a low-power standby mode which is enabled: (a) after a fresh power up, (b) after receiving a P bit in read mode, and (c) after completing a self-time internal programming operation 4.6 oft eset fter an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: (a) reate a start condition, (b) lock nine cycles, and (c) create another start bit followed by stop bit condition, as shown below. he device is ready for the next communication after the above steps have been completed. Figure 4-4 oft eset Dummy lock ycles tart tart top D Puya emiconductor 8/9

9 P2428 Datasheet ev Device ddressing he P2428 requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure4-5). he device address word consists of a mandatory one-zero sequence for the first four most-significant bits, as shown. Figure 4-5 Device ddress / he three 2,, and 0 device address bits to allow as many as eight devices on the same bus. hese bits must compare to their corresponding hardwired input pins. he 2,, and 0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are floating. he eighth bit of the device address is the read/write operation select bit. read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the hip will output a zero. If a compare is not made, the device will return to a standby state. 4.8 Data ecurity P2428 has a hardware data protection scheme that allows the user to write protect the whole memory when the pin is at Vcc. Puya emiconductor 9/9

10 P2428 Datasheet ev.. 5. Instructions 5. rite perations 5.. Y I write operation requires two 8-bit data word address (3/0) following the device address word and acknowledgment. Upon receipt of this address, the P2428 will again respond with a 0 and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the P2428 will output a 0 and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. nd then the P2428 enters an internally timed write cycle, all inputs are disabled during this write cycle and the P2428 will not respond until the write is complete (see Figure 5-). Figure 5- yte rite Device ddress I First ord ddress econd ord ddress DataIn P D IN 0 0 X X / Notes: [] x means don t care Page rite page write is initiated the same as a byte write, but the master does not send a stop condition after the first data word is clocked in. Instead, after the P2428 acknowledges receipt of the first data word, the master can transmit more data words. he P2428 will respond with a 0 after each data word received. he microcontroller must terminate the page write sequence with a stop condition. Figure 5-2 Page rite Device ddress I First ord ddress econd ord ddress DataIn(n) DataIn(n+x) P D IN X X / he lower six bits of the data word address are internally incremented following the receipt of each data word. he higher data word address bits are not incremented, retaining the memory page row location. hen the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 64 data words are transmitted to the P2428, the data word address will roll-over, and previous data will be overwritten. he address roll-over during write is from the last byte of the current page to the first byte of the same page. Puya emiconductor 0/9

11 P2428 Datasheet ev cknowledge Polling nce the internally timed write cycle has started and the P2428 inputs are disabled, acknowledge polling can be initiated. his involves sending a start condition followed by the device address word. he read/write bit is representative of the operation desired. nly if the internal write cycle has completed will the P2428 respond with a 0, allowing the read or write sequence to continue rite Identification Page he Identification Page (64 bytes) is an additional page which can be written and (later) permanently locked in ead-only mode. It is written by the rite Identification Page instruction. his instruction uses the same protocol and format as Page rite (into memory array), except for the following differences: Device type identifier = 0b address bits 3/6 are don t care except for address bit 0 which must be 0. address bits 5/0 define the byte address inside the Identification page. If the Identification page is locked, the data bytes transferred during the rite Identification Page instruction are not acknowledged (No) ock Identification Page he ock Identification Page instruction (ock ID) permanently locks the Identification page in ead-only mode. he ock ID instruction is similar to yte rite (into memory array) with the following specific conditions: Device type identifier = 0b ddress bit 0 must be ; all other address bits are don t care he data byte must be equal to the binary value xxxx xxx, where x is don t care 5.2 ead perations ead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to. here are three read operations: urrent ddress ead; andom ddress ead and equential ead urrent ddress ead he internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. his address stays valid between operations as long as the chip power is maintained. he address roll-over during read is from the last byte of the last memory page to the first byte of the first page. nce the device address with the read/write select bit set to is clocked in and acknowledged by the P2428, the current address data word is serially clocked out. he microcontroller does not respond with an input 0 but does generate a following stop condition (see Figure 5-3). Puya emiconductor /9

12 P2428 Datasheet ev.. Figure 5-3 urrent ddress ead Device ddress D Dataut P D IN / N andom ead andom ead requires a dummy byte write sequence to load in the data word address. nce the device address word and data word address are clocked in and acknowledged by the P2428, the microcontroller must generate another start condition. he microcontroller now initiates a urrent ddress ead by sending a device address with the read/write select bit high. he P2428 acknowledges the device address and serially clocks out the data word. he microcontroller does not respond with a 0 but does generate a following stop condition (see Figure 5-4). Figure 5-4 andom ead Device ddress I First ord ddress econd ord ddress Device ddress D Dataut P D IN 0 0 X X / / N Dummy rite equential ead equential eads are initiated by either a urrent ddress ead or a andom ddress ead. fter the microcontroller receives a data word, it responds with acknowledge. s long as the P2428 receives acknowledge, it will continue to increment the data word address and serially clock out sequential data words. hen the memory address limit is reached, the data word address will roll-over and the equential ead will continue. he equential ead operation is terminated when the microcontroller does not respond with a 0 but does generate a following stop condition (see Figure 5-5) Puya emiconductor 2/9

13 P2428 Datasheet ev.. Puya emiconductor 3/9 Figure 5-5 equential ead X X I D IN First ord ddress Device ddress / econd ord ddress Dummy rite Dataut(n) D Device ddress / Dataut(n+) Dataut(n+x) P N ead Identification Page he Identification Page (64 bytes) is an additional page which can be written and (later) permanently locked in ead-only mode. he Identification Page can be read by ead Identification Page instruction which uses the same protocol and format as the ead ommand (from memory array) with device type identifier defined as 0b. he address bits 3/6 are don t care, the address bits 5/0 define the byte address inside the Identification Page. he number of bytes to read in the ID page must not exceed the page boundary (e.g. when reading the Identification Page from location 0d, the number of bytes should be less than or equal to 54, as the ID page boundary is 64 bytes) ead he ock tatus he locked/unlocked status of the Identification page can be checked by transmitting a specific truncated command [Identification Page rite instruction + one data byte] to the device. he device returns an acknowledge bit if the Identification page is unlocked, otherwise a No bit if the Identification page is locked. Figure 5-5 ock tatus ead (hen Identification page locked, return No after one data byte) X I First ord ddress Device ddress / econd ord ddress DataIn P D IN N o X

14 P2428 Datasheet ev.. 6. rdering ode Detail xample: P H I ompany Designator P = Puya emiconductor Product eries Name 24 = I2-compatible Interface P Device Density 28 = 28 bit Device eversion = Version Package ption DP: PDIP : P : P DN: DFN F: F Plating echnology H: oh omplaint G: oh ompliant, Halogen-free, ntimony-free peration Voltage U:.5~5.5V :.6~5.5V :.7~5.5V N:.8~5.5V D: 2.5~5.5V Device Grade I: -40~85 : -40~05 : -40~25 : -40~50 hipping arrier ption : F : U :P & Puya emiconductor 4/9

15 P2428 Datasheet ev.. 7. Package Information 7. 8-lead PDIP able 7-8-lead PDIP package mechanical data ymbol Dimensions In illimeters Dimensions In Inches min max min max b b2.524() 0.060() D e 2.54() 0.00() e Puya emiconductor 5/9

16 P2428 Datasheet ev lead P able lead P package mechanical data ymbol Dimensions In illimeters Dimensions In Inches min max min max b c D e.270() 0.050() θ Puya emiconductor 6/9

17 P2428 Datasheet ev lead P able lead P package mechanical data ymbol Dimensions In illimeters Dimensions In Inches min max min max D b c e 0.65() 0.026() H 0.25(YP) 0.0(YP) θ 7 7 Puya emiconductor 7/9

18 P2428 Datasheet ev lead DFN able lead DFN package mechanical data ymbol Dimensions In illimeters Dimensions In Inches min max min max 0.700/ / / / F F. D D k 0.200IN IN. b e 0.500YP YP Puya emiconductor 8/9

19 P2428 Datasheet ev.. 8. evision History Version ontent Date ev.0 Initial elease ev. abel changed to P Puya emiconductor o., td. IPN NI Puya emiconductor reserves the right to make changes without further notice to any products or specifications herein. Puya emiconductor does not assume any responsibility for use of any its products for any particular purpose, nor does Puya emiconductor assume any liability arising out of the application or use of any its products or circuits. Puya emiconductor does not convey any license under its patent rights or other rights nor the rights of others. Puya emiconductor 9/9

Turbo IC, Inc. 24C128/24C256

Turbo IC, Inc. 24C128/24C256 urbo I, Inc. 2412824256 DU IINY I² 2-I U 128256 IY G 1632 X 8 I FU : xtended ower upply Voltage ingle Vcc for ead and rogramming (Vcc = 2.7 V to 5.5 V)(Vcc = 4.5V to 5.5V) ow ower (Isb = 2µa @ 5.5 V) xtended