Turbo IC, Inc. 24C128/24C256

Size: px

Start display at page:

Download "Turbo IC, Inc. 24C128/24C256"

Allyson Cross
5 years ago
Views:

1 urbo I, Inc DU IINY I² 2-I U IY G 1632 X 8 I FU : xtended ower upply Voltage ingle Vcc for ead and rogramming (Vcc = 2.7 V to 5.5 V)(Vcc = 4.5V to 5.5V) ow ower (Isb = 5.5 V) xtended I² us, 2-ire erial Interface upport yte rite and age rite (64 ytes) utomatic age write peration (maximum 10 ms) Internal ontrol imer Internal Data atches for 64 ytes Hardware Data rotection by rite rotect in High eliability echnology ell ndurance : 100,000 ycles Data etention : 100 Years 8 pin JD 300 mil wide DI ND 8 pin 150 mil wide I packages IN DIIN GND IN DIIN 8 pin I V D GND pin DI V D DIIN: he urbo I is a serial fabricated with urbo s proprietary, high reliability, high performance technology. It s of memory is organized as x 8 bits. he memory is configured as pages with each page containing 64 bytes. his device offers significant advantages in low power and low voltage applications. he urbo I uses the extended I² addressing protocol and 2-wire serial interface which includes a bidirectional serial data bus synchronized by a clock. It offers a flexible byte write and a faster 64-byte page write. he entire memory can be protected by the write protect pin. he urbo I is assembled in either a 8- pin DI or 8-pin I package. in #1 (0), #2 (1), and #3 (2) are device address input pins which are hardwired by the user. in #4 is the ground (Vss). in #5 is the serial data (D) pin used for bidirectional transfer of data. in #6 is the serial clock () input pin. in #7 is the write protect () input pin, and in #8 is the power supply (Vcc) pin. ll data is serially transmitted in bytes (8 bits) on the D bus. o access the urbo I (slave) for a read or write operation, the controller (master) issues a start condition by pulling D from high to low while is high. he master then issues the device address byte which consists of 1010 (2) (1) (0) (). he 4 most significant bits (1010) are a device type code signifying an device. he [2:0] bits represent the input levels on the 3 device address input pins. he readwrite bit determines whether to do a read or write operation. fter each byte is transmitted, the receiver has to provide an acknowledge by pulling the D bus low on the ninth clock cycle. he acknowledge is a handshake signal to the transmitter indicating a successful data transmission. DVI DD (2-0) he address inputs are used to define the 3 least significant bits of the 7-bit device address code (2) (1) (0). hese pins can be connected either high or low. maximum of eight urbo I can be connected in parallel, each with a unique device address. hen these pins are left unconnected, the device addresses are interpreted as zero. I () hen the write protect input is connected to Vcc, the entire memory is protected against write operations. For normal write operation, the write protect pin should be grounded. hen this pin is left unconnected, is interpreted as zero. I D (D) D is a bidirectional pin used to transfer data in and out of the urbo I he pin is an open-drain output. pull-up resistor must be connected from D to Vcc. I () he input synchronizes the data on the D bus. It is used in conjunction with D to define the start and stop conditions. It is also used in conjunction with D to transfer data to and from the urbo I

2 urbo I, Inc DU IINY DIIN (ontinued) For a write operation, the master issues a start condition, device address byte, 2 memory address bytes, and then up to 64 data bytes. he urbo I acknowledges after each byte transmission. o terminate the transmission, the master issues a stop condition by pulling D from low to high while is high. DVI IN: IDIIN U : he urbo I follows the extended I² bus protocol. he protocol defines any device that sends data onto the D bus as a transmitter, and the receiving device as a receiver. he device controlling the transfer is the master and the device being controlled is the slave. he master always initiates the data transfers, and provides the clock for both transmit and receive operations. he urbo I acts as a slave device in all applications. ither the master or the slave can take control of the D bus, depending on the requirement of the protocol. NDIIN ND D NIIN: hile clock is high, a high to low transition on the D bus is recognized as a condition which precedes any read or write operation. hile clock is high, a low to high transition on the D bus is recognized as a condition which terminates the communication and places the urbo I into standby mode. ll other data transitions on the D bus must occur while clock is low to ensure proper operation. For a read operation, the master issues a start condition and a device address byte. he urbo I acknowledges, and then transmits a data byte, which is accessed from the memory. he master acknowledges, indicating that it requires more data bytes. he urbo I transmits more data bytes, with the memory address counter automatically incrementing for each data byte, until the master does not acknowledge, indicating that it is terminating the transmission. he master then issues a stop condition. NDG: ll data is serially transmitted in bytes (8 bits) on the D bus. he acknowledge protocol is used as a handshake signal to indicate successful transmission of a byte of data. he bus transmitter, either the master or the slave (urbo I ), releases the bus after sending a byte of data on the D bus. he receiver pulls the D bus low during the ninth clock cycle to acknowledge the successful transmission of a byte of data. If the D is not pulled low during the ninth clock cycle, the urbo I terminates the data transmission and goes into standby mode. For the write operation, the urbo I acknowledges after the device address byte, acknowledges after each memory address byte, and acknowledges after each subsequent data byte. For the read operation, the urbo I acknowledges after the device address byte. hen the urbo I transmits each subsequent data byte, and the master acknowledges after each data byte transfer, indicating that it requires more data bytes. he urbo I monitors the D bus for the acknowledge. o terminate the transmission, the master does not acknowledge, and then sends a stop condition. rite ycle iming D 8th I D n NDIIN t NDIIN Note: he write cycle time t is the time from a valid stop condition of a write sequence to the end of the internal clear write cycle. 2

3 urbo I, Inc DU IINY Data Valid D D D D HNG tart and top Definition D utput cknowledge D IN D U NDG 3

4 urbo I, Inc DU IINY DVI DDING: Following the start condition, the master will issue a device address byte consisting of 1010 (2) (1) (0) () to access the selected urbo I for a read or write operation. he [2:0] bits must match with the address input pins of the selected urbo I If there is a match, the selected urbo I acknowledges during the ninth clock cycle by pulling the D bus low. If there is no match, the urbo I does not acknowledge during the ninth clock cycle and goes into standby mode. he () bit is a high (1) for read and low (0) for write. D INU DUING I IN: During the write operation, the urbo I latches the D bus signal on the rising edge of the clock. D UU DUING D IN: During the read operation, the urbo I serially shifts the data onto the D bus on the falling edge of the clock. Y DDING: he memory address is sent by the master in the form of 2 memory address bytes. he memory address bytes can only be sent as part of a write operation. he most significant address byte (14) (13) (12) (11) (10) (9) (8) is sent first, where (14) is a don t care bit in the hen the least significant address byte (7) (6) (5) (4) (3) (2) (1) (0) is sent last. memory address counter is automatically incremented by one. he stop condition starts the internal write cycle only if the stop condition occurs in the clock cycle immediately following the acknowledge (10th clock cycle). ll inputs are disabled until the completion of the write cycle. If the pin is high (1), then the stop condition does not start the internal write cycle, and the urbo I is immediately ready for the next command. ING NDG: During the internal write cycle of a write operation in the urbo I , the completion of the write cycle can be detected by polling acknowledge. he master starts acknowledge polling by issuing a start condition, then followed by the device address byte 1010 (2) (1) (0) 0. If the internal write cycle is finished, the urbo I acknowledges by pulling the D bus low. If the internal write cycle is still ongoing, the urbo I does not acknowledge because it s inputs are disabled. herefore, the device will not respond to any command. y using polling acknowledge, the system delay for write operations can be reduced. therwise, the system needs to wait for the maximum internal write cycle time, t, given in the spec. N : he urbo I has a ower n eset circuit () to prevent data corruption and accidental write operations during power up. n power up, the internal reset signal is on and the urbo I will not respond to any command until the V voltage has reached the threshold value. Y I IN: he master initiates the byte write operation by issuing a start condition, followed by the device address byte 1010 (2) (1) (0) 0, followed by 2 memory address bytes, followed by one data byte, then a stop condition. fter each byte transfer, the urbo I acknowledges the successful data transmission by pulling the D bus low. he stop condition starts the internal write cycle, and all inputs are disabled until the completion of the write cycle. If the pin is high, then the stop condition does not start the internal write cycle and the urbo I is immediately ready for the next command. G I IN: he master initiates the page write operation by issuing a start condition, followed by the device address byte 1010 (2) (1) (0) 0, followed by 2 memory address bytes, followed by up to 64 data bytes, then a stop condition. fter each byte transfer, the urbo I acknowledges the successful data transmission by pulling D low. fter each data byte transfer, the 4

5 urbo I, Inc DU IINY Device ddress yte rite DVI DD I FI D DD ND D DD D D IN *! age rite D IN I DVI DD FI ND D DD (n) D DD (n) *! D (n) D (n + x) * = Don't care bits! = Don't care bit for

6 urbo I, Inc DU IINY UN DD D: he internal memory address counter of the urbo I contains the last memory address accessed during the previous read or write operation, incremented by one. o start the current address read operation, the master issues a start condition, followed by the device address byte 1010 (2) (1) (0) 1. he urbo I responds with an acknowledge by pulling the D bus low, and then serially shifts out the data byte accessed from memory at the location corresponding to the memory address counter. he master does not acknowledge, then sends a stop condition to terminate the read operation. It is noted that the memory address counter is incremented by one after the data byte is shifted out. ND DD D: he master starts with a dummy write operation (one with no data bytes) to load the internal memory address counter by first issuing a start condition, followed by the device address byte 1010 (2) (1) (0) 0, followed by the 2 memory address bytes. Following the acknowledge from the urbo I , the master starts the current read operation by issuing a start condition, followed by the device address byte 1010 (2) (1) (0) 1. he urbo I responds with an acknowledge by pulling the D bus low, and then serially shifts out the data byte accessed from memory at the location corresponding to the memory address counter. he master does not acknowledge, then sends a stop condition to terminate the read operation. It is noted that the memory address counter is incremented by one after the data byte is shifted out. QUNI D: he sequential read is initiated by either a current address read or random address read. fter the urbo I serially shifts out the first data byte, the master acknowledges by pulling the D bus low, indicating that it requires additional data bytes. fter the data byte is shifted out, the urbo I increments the memory address counter by one. hen the urbo I shifts out the next data byte. he sequential reads continues for as long as the master keeps acknowledging. hen the memory address counter is at the last memory location, the counter will roll-over when incremented by one to the first location in memory (address zero). he master terminates the sequential read operation by not acknowledging, then sends a stop condition. urrent ddress ead DVI DD D D D IN N andom ead D IN DVI DD I D DD N *! DVI DD D D n N DUY I 6

7 urbo I, Inc DU IINY equential ead D DVI DD D n D n +1 D n + 2 D n + 3 D IN N U XIU ING U torage: -65 to 150 Under ias: -55 to 125 INU UU VG with respect to Vss +6 V to -0.3 V NDD ING NDIIN emperature ange: ommercial: 0 to 70 Industrial: -40 to 85 Vcc upply Voltage: 2.7 to 5.5 Volts 4.5 to 5.5 Volts * bsolute aximum atings may cause permanent damage to the device. his is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. xposure to absolute maximum rating conditions for extended periods may affect device reliability. ndurance: Data etention: 100,000 yclesyte (ypical) 100 Years D.. HII ymbol arameter ondition in ax Units I cc1 ctive Vcc urrent D at 100 HZ I cc2 ctive Vcc urrent I at 100 HZ I sb1 tandby urrent Vcc = 2.7 v 0.5 u Vcc = 5.5 v 2.0 u I sb2 tandby urrent Vcc = 4.5 v 20.0 u Vcc = 5.5 v 35.0 u I li Input eakage urrent Vin=Vcc ax 3 u I lo utput eakage urrent 3 u V il Input ow Voltage -1.0 V V ih Input High Voltage Vcc+0.5 V V ol2 utput ow Vcc=3.0v Iol=2.1 m 0.4 V V ol1 utput ow Vcc=2.7v Iol=-0.15 m 0.25 V 7

8 urbo I, Inc DU IINY us iming t F t t HIGH t t t U. t thd. HD.D t U.D t U. D IN t t DH t UF D U.. HII ymbol arameter 2.7 volt 5.5 volt Units in ax in ax lock Frequency khz t lock ow eriod us t HIGH lock High eriod us t ow to D Data ut us t UF us Free to New tart (1) us t HD. tart Hold ime us t U. tart etup ime us t HD.D Data-in Hold ime 0 0 us t U.D Data-in et-up ime ns t and D ise ime (1) us t F and D Fall ime (1) ns t U. top etup ime us t DH Data-out Hold ime ns t rite ycle ime ms Note: 1 his parameter is characterized and not 100% tested. U I DU ND DUN 1. ll documents are subject to change without notice. lease contact urbo I for the latest revision of documents. 2. urbo I does not assume any responsibility for any damage to the user that may result from accidents or operation under abnormal conditions. 3. urbo I does not assume any responsibility for the use of any circuitry other than what embodied in a urbo I product. No other circuits, patents, licenses are implied. 4. urbo I products are not authorized for use in life support systems or other critical systems where component failure may endanger life. ystem designers should design with error detection and correction, redundancy and backup features. art Numbers & rder Information U X 8 erial ackage -DI -I emperature -ommercial I -Industrial perating Voltage blank 4.5 to 5.5 V to 5.5 V urbo I, Inc aragon Drive, uite I, an Jose, hone: Fax: ee us at ev

I 2 C-Compatible Serial E 2 PROM

I 2 C-Compatible Serial E 2 PROM P2428 I 2 -ompatible erial 2 P Data heet ev.. General Description he P2428 is a 28-bit I 2 -compatible erial P (lectrically rasable Programmable emory) device. It contains a memory array of 6 8 bits, which