EDW4032BABG 8 Meg x 32 I/O x 16 banks, 16 Meg x 16 I/O x 16 banks. Options 1. Note:

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1 GR5 SGRM 4Gb: x16, x32 GR5 SGRM Features EW4032G 8 Meg x 32 I/O x 16 banks, 16 Meg x 16 I/O x 16 banks Features = = 1.6V/1.55V/1.5V ±3% and 1.35V ±3% ata rate: 6.0 Gb/s, 7.0 Gb/s, 8.0 Gb/s (MX) 16 internal banks Four bank groups for t CCL = 3 t CK 8n-bit prefetch architecture: 256-bit per array read or write access for x32; 128-bit for x16 urst length (L): 8 only Programmable CS latency: 6 27 Programmable WRITE latency: 3 7 Programmable CRC RE latency: 1 3 Programmable CRC WRITE latency: 8 14 Programmable EC hold pattern for CR Precharge: uto option for each burst access uto refresh and self refresh modes Refresh cycles: 16,384 cycles/32ms Interface: Pseudo open drain (PO-15) compatible outputs: 40Ω pull-down, 60Ω pull-up On-die termination (OT): 60Ω or 120Ω (NOM) OT and output driver strength auto calibration with external resistor ZQ pin: 120Ω Programmable termination and driver strength offsets Selectable external or internal V REF for data inputs; programmable offsets for internal V REF Separate external V REF for address/command inputs T C = 0 C to +95 C x32/x16 mode configuration set at power-up with EC pin Single-ended interface for data, address, and command Quarter data rate differential clock inputs CK_t, CK_c for address and commands Two half data rate differential clock inputs, WCK_t and WCK_c, each associated with two data bytes (Q, I_n, EC) R data (WCK) and addressing (CK) SR command (CK) Write data mask function via address bus (single/ double byte mask) ata bus inversion (I) and address bus inversion (I) Input/output PLL on/off mode uty cycle corrector (CC) for data clock (WCK) igital RS lockout ddress training: ddress input monitoring via Q pins WCK2CK clock training: Phase information via EC pins ata read and write training via read FIFO (FIFO depth = 6) Read FIFO pattern preloaded by LFF command irect write data load to read FIFO by WRTR command Consecutive read of read FIFO by RTR command Read/write data transmission integrity secured by cyclic redundancy check (CRC-8) Read/write EC on/off mode Low power modes RQS mode on EC pin On-die temperature sensor with readout utomatic temperature sensor controlled self refresh rate Vendor I, FIFO depth and density info fields for identification Mirror function with MF pin oundary scan function with SEN pin Options 1 Marking Organization ensity Meg x 32 (words x bits) 32 FG package 170-ball (12mm x 14mm) G Package environment code Lead- and halogen-free -F (RoHS-compliant) Package media ry pack (tray) - Reel -R Timing maximum data rate 6.0 Gb/s, 5.0 Gb/s Gb/s, 6.0 Gb/s Gb/s, 6.0 Gb/s -80 Operating temperature Commercial (0 C T C +95 C) None Revision Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on for available offerings. 1 Products and specifications discussed herein are subject to change by Micron without notice.

2 Features Table 1: ddressing Parameter 256 Meg x Meg x 32 Configuration 16 Meg x 16 x 16 banks 8 Meg x 32 x 16 banks Refresh count 16K/32ms 16K/32ms Refresh period 1.9µs 1.9µs Row addressing [13:0] [13:0] ank addressing [3:0] [3:0] Column addressing [6:0] [5:0] uto precharge 8 8 Page size 2K 2K Figure 1: Part Numbering Micron Memory Type = Packaged device Product Family W = GR5 SGRM E W G F - Packing Media = ry pack (tray) R = Reel Environment Code F = Lead-free (RoHS-compliant) and halogen-free ensity/ank 40 = 4Gb/16-bank Organization 32 = x32 Power Supply, Interface = = 1.6V/1.55V/1.5V Speed -60 = 6.0 Gb/s -70 = 7.0 Gb/s -80 = 8.0 Gb/s Package G = 170-ball FG, 12mm x 14mm Revision FG Part Marking ecoder ue to space limitations, FG-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FG code, see the FG Part Marking ecoder on Micron s web site: 2

3 Figure 2: 170-all FG MF = 0 (Top View) Q1 Q0 Q8 Q9 Q3 Q2 Q10 Q11 C EC0 EC1 I0_n WCK01_t WCK01_c I1_n E Q5 Q4 Q12 Q13 F Q7 Q6 Q14 Q15 G RS_n CS_n H 10, 0 9, 1 3, 3 0, 2 J MF RESET_n CKE_n I_n 12, 13 SEN CK_c CK_t ZQ V REFC K 8, 7 11, 6 1, 5 2, 4 L CS_n WE_n M Q31 Q30 Q22 Q23 N Q29 Q28 Q20 Q21 P I3_n WCK23_t WCK23_c I2_n R EC3 EC2 T Q27 Q26 Q18 Q19 U Q25 Q24 Q16 Q17 (Top view) ata ddresses GR5 Supply Ground Note: 1. alls shown with a heavy, solid outline are off in x16 mode. 3

4 Figure 3: 170-all FG MF = 1 (Top View) Q25 Q24 Q16 Q17 Q27 Q26 Q18 Q19 C EC3 EC2 I3_n WCK23_t WCK23_c I2_n E Q29 Q28 Q20 Q21 F Q31 Q30 Q22 Q23 G CS_n WE_n H 8, 7 11, 6 1, 5 2, 4 J MF RESET_n CKE_n I_n 12, 13 SEN CK_c CK_t ZQ V REFC K 10, 0 9, 1 3, 3 0, 2 L RS_n CS_n M Q7 Q6 Q14 Q15 N Q5 Q4 Q12 Q13 P I0_n WCK01_t WCK01_c I1_n R EC0 EC1 T Q3 Q2 Q10 Q11 U Q1 Q0 Q8 Q9 (Top view) ata ddresses GR5 Supply Ground Note: 1. alls shown with a heavy, solid outline are off in x16 mode. 4

5 Table 2: 170-all FG all escriptions Symbol Type escription [13:0] Input ddress inputs: Provide the row address for CTIVE commands. [5:0] (6) provide the column address and 8 defines the auto precharge bit for RE/WRITE commands, to select one location out of the memory array in the respective bank. 8 sampled during a PRECHRGE command determines whether the PRECHRGE applies to one bank (8 LOW, bank selected by [3:0]) or all banks (8 HIGH). The address inputs also provide the op-code during a MOE REGISTER SET command and the data bits during LFF commands. [12:8] are sampled with the rising edge of CK_t and [7:0], 13 are sampled with the rising edge of CK_c. I_n Input ddress bus inversion: Reduces the power requirements on address pins by limiting the number of address lines driving LOW to 5. I_n is enabled by the corresponding I mode register bit. [3:0] Input ank address inputs: efine the bank to which an CTIVE, RE, WRITE, or PRE- CHRGE command is being applied. [3:0] define which mode register is loaded during the MOE REGISTER SET command. [3:0] are sampled with the rising edge of CK_t. CK_t, CK_c Input Clock: CK_t and CK_c are differential clock inputs. Command inputs are latched on the rising edge of CK_t. ddress inputs are latched on the rising edge of CK_t and the rising edge of CK_c. ll latencies are referenced to CK_t. CK_t and CK_c are externally terminated. WCK01_t, WCK01_c/ WCK23_t, WCK23_c Input ata Clocks: WCK_t and WCK_c are differential clocks used for write data capture and read data output. WCK01_t and WCK01_c are associated with Q[15:0], I0_n, I1_n, EC0, and EC1. WCK23_t and WCK23_c are associated with Q[31:16], I2_n, I3_n, EC2, and EC3. WCK clocks operate at nominally twice the CK clock frequency. CKE_n Input Clock enable: CKE_n enables (registered LOW) and disables (registered HIGH) internal circuitry and clocks on the device. The specific circuitry that is enabled/disabled is dependent upon the device configuration and operating mode. Taking CKE_n HIGH provides PRECHRGE POWER-OWN and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE_n is synchronous for powerdown entry and exit and for self refresh entry. CKE_n must be maintained LOW throughout read and write accesses. Input buffers (excluding CKE_n) are disabled during SELF REFRESH operation. The value of CKE_n latched at power-up with RE- SET_n going HIGH determines the termination value of the address and command inputs. CS_n Input Chip select: CS_n enables (registered LOW) and disables (registered HIGH) the command decoder. ll commands are masked when CS_n is registered HIGH, but internal command execution continues. CS_n is considered part of the command code. MF Input Mirror function: CMOS input. Must be tied to or. RS_n, CS_n, WE_n Input Command inputs: RS_n, CS_n, and WE_n (along with CS_n) define the command being entered. RESET_n Input Reset: RESET_n is an active LOW CMOS input referenced to. full chip reset may be performed at any time by pulling RESET_n LOW. With RESET_n LOW all OTs are disabled. SEN Input Scan enable: CMOS input. Must be tied to when not in use. 5

6 Table 2: 170-all FG all escriptions (Continued) Symbol Type escription Q[31:0] I/O ata input/output: idirectional 32-bit data bus. I[3:0]_n I/O ata bus inversion: Reduces the C power consumption and supply noise induced jitter on data pins. I0_n is associated with Q[7:0], I1_n with Q[15:8], I2_n with Q[23:16], and I3_n with Q[31:24]. EC[3:0] Output Error detection code: The calculated CRC data is transmitted on these pins. In addition, these pins drive a hold pattern when idle and can be used as an RQS function. EC0 is associated with Q[7:0], EC1 with Q[15:8], EC2 with Q[23:16], and EC3 with Q[31:24]. Supply Power supply: 1.6V/1.55V/1.5V ±3% and 1.35V ±3%. Supply Q power supply: 1.6V/1.55V/1.5V ±3% and 1.35V ±3%. Isolated on the device for improved noise immunity. V REFC Supply Reference voltage for control and address: V REFC must be maintained at all times (including self refresh) for proper device operation. Supply Reference voltage for data: must be maintained at all times (including self refresh) for proper device operation. Supply Ground. Supply Q ground: Isolated on the device for improved noise immunity. ZQ Reference External reference ball for impedance calibration: This ball is tied to an external 120Ω resistor (ZQ), which is tied to. No connect: These balls should be left unconnected (the ball has no connection to the device or to other balls). 6

7 Package imensions Package imensions Figure 4: 170-all FG (G) 0.2 S 0.35 ± ±0.1 S 0.12 S 0.15 M S ± C E F G H J K L M N P R T U all 1 I 14.0 ± ±0.1 all 1 I 0.2 S S 10.4 Notes: 1. ll dimensions are in millimeters. 2. Solder ball material: SC302 (96.8% Sn, 3% g, 0.2% Cu) S. Federal Way, P.O. ox 6, oise, I , Tel: Sales inquiries: Micron and the Micron logo are trademarks of Micron Technology, Inc. ll other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. lthough considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 7