Correlated Double Sampler (CDS) AD9823

Transcription

1 Correlated Double Sampler (CDS) AD9823 FEATURES 40 MHz correlated double sampler (CDS) Fixed 3.5 db CDS gain Low noise optical black clamp circuit 3 V single-supply operation 4-lead TSSOP package CCDIN FUTIONAL BLOCK DIAGRAM AD dB FIXED GAIN CDS OUTPUT BUFFER OUTPUT APPLICATIONS Digital still cameras Digital video camcorders CCTV cameras PC cameras Portable CCD imaging devices BYP2 OUTPUT BUFFER INTERNAL TIMING INTERNAL REFEREE VDD BYP BYP Figure. Functional Block Diagram PRODUCT DESCRIPTION The AD9823 is a correlated double sampler for digital camera applications. It features a 40 MHz CDS amplifier with 3.5 db of fixed gain, an internal voltage reference supply, and timing control for the and sampling clocks. Output buffers are also included, providing drive strength for PCB traces and direct connection to an image signal processor such as the AD982. The AD9823 is ideal for applications that need to place the CDS and VGA/ADC circuits on separate PC boards. The pseudo differential outputs of the AD9823 provide good signal integrity when interfaced with the differential input AD982. The AD9823 operates from a single 3 V power supply, typically dissipates 50 mw, and is packaged in a 4-lead TSSOP package. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 906, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Specifications... 3 General Specifications... 3 Analog Specifications... 3 Digital Specifications... 3 Timing Specifications... 4 Absolute Maximum Ratings... 5 Thermal Characteristics...5 ESD Caution...5 Pin Configuration and Function Descriptions...6 and Timing...6 Outline Dimensions...8 Ordering Guide...8 REVISION HISTORY Revision 0: Initial Version Rev. 0 Page 2 of 8

3 SPECIFICATIONS GENERAL SPECIFICATIONS Table. Parameter Min Typ Max Unit Temperature Range Operating C Storage C Power Supply Voltage V Power Consumption: fsamp = 40 MHz, VDD = 3.0 V 50 mw Maximum Clock Rate 40 MHz Minimum Clock Rate 5 MHz ANALOG SPECIFICATIONS Table 2. TMIN to TMAX, VDD = 3.0 V, fsamp = 40 MHz, unless otherwise noted. Parameter Min Typ Max Unit Notes Analog Input (CCDIN) Max Input Range Before Saturation 850 mv p-p Allowable CCD Reset Transient 500 mv Max CCD Black Pixel Amplitude 00 mv Gain db Nonlinearity, 500 mv Input.0 % Max deviation from ideal straight line Input Referred Noise 00 µv rms Output noise divided by 3.5 db gain Clamp Time Constant 90 µsec 0. µf BYP2 capacitor (proportional to capacitor value) Analog Outputs Typical Data Out Signal Range V 0.5 V corresponds to black level Voltage Level 0.5 V Fixed dc reference for signal output Input signal characteristics defined as follows: 500mV TYP RESET TRANSIENT 00mV TYP OPTICAL BLACK PIXEL 850mV TYP INPUT SIGNAL RANGE All specifications subject to change without notice DIGITAL SPECIFICATIONS Table 3. Parameter Symbol Min Typ Max Unit Logic Inputs (,, ) High Level Input Voltage VIH 2. V Low Level Input Voltage VIL 0.6 V High Level Input Current IIH 0 µa Low Level Input Current IIL 0 µa Input Capacitance CIN 0 pf Rev. 0 Page 3 of 8

4 TIMING SPECIFICATIONS Table 4. TMIN to TMAX, VDD = 3.0 V, fsamp = 40 MHz, unless otherwise noted. Parameter (See Figure 3) Symbol Min Typ Max Unit Sample Clocks, Clock Period tcp 25 ns Pulse Width t ns Pulse Width t ns Pulse Width tcob 4 0 pixels Rising Edge to Rising Edge ts ns Rising Edge to Rising Edge ts ns Internal Clock Delay tid 3.0 ns Recommended Data CLK Timing (for AD982) trec 4.5 ns Minimum pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance. Specifications subject to change without notice. Rev. 0 Page 4 of 8

5 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter With Respect To Min Max Unit VDD V, 0.3 VDD V BYP, BYP2, BYP3 0.3 VDD V CCDIN 0.3 VDD V, 0.3 VDD V 0.3 VDD V Junction Temperature 50 C Lead Temperature (0 sec) 350 C THERMAL CHARACTERISTICS Thermal Resistance 4-Pin, TSSOP Package θja = 89.2 C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 Page 5 of 8

6 PIN CONFIGURATION AND FUTION DESCRIPTIONS VDD BYP AD9823 TOP VIEW (Not to Scale) = NO CONNECT CCDIN BYP3 BYP Figure 2. Pin Configurations Table 6. Pin Function Descriptions Pin Number Name Type Description DI Input Clamp Clock Input (active low, not latched internally). 2 No connection should be connected to or VDD. 3 VDD P Analog Supply. 4 AO Output Reference Level. 5 AO Output Data Signal. 6 P Analog Ground. BYP AO Internal Bias Level Decoupling. 8 BYP2 AO Internal Bias Level Decoupling. 9 BYP3 AO Internal Bias Level Decoupling. 0 No connection should be connected to or VDD. CCDIN AI CCD Input. 2 P Analog Ground. 3 DI CDS Sampling Clock Input (For CCD Data Level). 4 DI CDS Sampling Clock Input (For CCD Ref Level). AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power, = No Connect. AND TIMING CCD SIGNAL t ID N N+ N+2 N+9 N+0 t ID t CP t t t S t S2 DATACLK (FOR AD982) t REC Figure 3. and Timing Rev. 0 Page 6 of 8

7 EFFECTIVE PIXELS OPTICAL BLACK PIXELS HORIZONTAL BLANKING DUMMY PIXELS EFFECTIVE PIXELS CCD SIGNAL Figure 4. Timing ANALOG SUPPLY 4.µF (CONNECT TO VIN ON AD982) (CONNECT TO VIN+ ON AD982) VDD BYP AD TOP VIEW CCDIN (Not to Scale) 0 BYP3 9 BYP2 8 CCDIN = NO CONNECT Figure 5. AD9823 Circuit Configuration SERIAL INTERFACE 3.0µF.0µF DATA OUTPUTS 2 D0 D 2 D2 3 D3 4 D4 5 D5 6 D6 D 8 D8 9 D9 0 D0 (MSB) D 2 DRIVER SUPPLY SCK SDATA SL STBY DVSS DVDD2 VRB VRT PIN IDENTIFIER AD982 TOP VIEW (Not to Scale DRVDD DRVSS DVSS DATACLK DVDD PBLK OB AVSS AVDD2 BYP VIN VIN+ AVDD AVSS AVSS IMAGER INPUT, NEGATIVE IMAGER INPUT, POSITIVE 4.µF 4.µF = INTERNALLY NOT CONNECTED 2 VDD 3 AD CCDIN 4 TOP VIEW 5 (Not to Scale) 0 6 BYP 9 8 BYP3 BYP2 OUTPUT FROM CCD 3 CLOCK INPUTS Figure 6. Circuit Configuration with the AD982 2-Bit Image Signal Processor Rev. 0 Page of 8

8 OUTLINE DIMENSIONS BSC PIN BSC MAX SEATING PLANE COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-53AB Figure. 4-Lead Thin Shrink Small Outline Package [TSSOP] (RU-4) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9823BRUZ 25 C to +85 C TSSOP RU-4 Z = Pb-free part Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.. C /03(0) Rev. 0 Page 8 of 8