Low Voltage 1.65 V to 3.6 V, Bidirectional Logic Level Translation, Bypass Switch ADG3233

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1 Data Sheet Low Voltage. V to. V, Bidirectional Logic Level Translation, Bypass Switch ADG FEATURES Operates from. V to. V supply rails Bidirectional level translation, unidirectional signal path -lead SOT- and MSOP packages Bypass or normal operation Short circuit protection FUNCTIONAL BLOCK DIAGRAM A V CC V CC V CC Y APPLICATIONS JTAG chain bypassing Daisy-chain bypassing Digital switching A V CC V CC V CC V CC Y EN ADG GND Figure. 97- GENERAL DESCRIPTION The ADG is a bypass switch designed on a submicron process that operates from supplies as low as. V. The device is guaranteed for operation over the supply range. V to. V. It operates from two supply voltages, allowing bidirectional level translation, that is, it translates low voltages to higher voltages and vice versa. The signal path is unidirectional, meaning data may only flow from A Y. This type of device may be used in applications that require a bypassing function. It is ideally suited to bypassing devices in a JTAG chain or in a daisy-chain loop. One switch could be used for each device or a number of devices, thus allowing easy bypassing of one or more devices in a chain. This may be particularly useful in reducing the time overhead in testing devices in the JTAG chain or in daisy-chain applications where the user does not wish to change the settings of a particular device. The bypass switch is packaged in two of the smallest footprints available for its required pin count. The -lead SOT- package requires only.9 mm. mm board space, while the MSOP package occupies approximately mm.9 mm board area. PRODUCT HIGHLIGHTS. Bidirectional level translation matches any voltage level from. V to. V.. The bypass switch offers high performance and is fully guaranteed across the supply range.. Short circuit protection.. Tiny -lead SOT- package and -lead MSOP. Table. Truth Table EN Signal Path Function L A Y, Y VCC Enable bypass mode H A Y, A Y Enable normal mode U.S. Patent Number: 7,9, B. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 ADG TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Product Highlights... Revision History... Specifications... Test Waveforms... Absolute Maximum Ratings... Data Sheet ESD Caution... Pin Configuration and Function Descriptions...7 Typical Performance Characteristics... Theory of Operation... A and EN Input... Normal Operation... Bypass Operation... Outline Dimensions... Ordering Guide... REVISION HISTORY / Rev. B to Rev. C Changes to Table... 7 Changes to Ordering Guide... 7/ Rev. A to Rev. B Changes to Table... 7/ Rev. to Rev. A Changes to Patent Number, General Description Section, and Product Highlights Section... Changes to VCC = VCC = VCC =. V ±. V, ENABLE Time EN Y, Table... Changes to Table... Updated Outline Dimensions... Changes to Ordering Guide... / Revision : Initial Version Rev. C Page of

3 Data Sheet ADG SPECIFICATIONS VCC = VCC =. V to. V, GND = V, all specifications TMIN to TMAX, unless otherwise noted. Table. Parameter Symbol Test Conditions/Comments Min Typ Max Unit LOGIC INPUTS/OUTPUTS VCC =. V to. V, GND = V Input High Voltage VIH VCC =. V to. V. V VCC =. V to.7 V. V VCC =. V to.9 V. VCC V Input Low Voltage VIL VCC =. V to. V. V VCC =. V to.7 V.7 V VCC =. V to.9 V. VCC V Output High Voltage (Y) VOH IOH = µa, VCC =. V to. V. V IOH = µa, VCC =. V to.7 V. V IOH = µa, VCC =. V to.9 V VCC. V IOH = ma, VCC =. V to.7 V. V IOH = ma, VCC =. V to.9 V VCC. V IOH = ma, VCC =. V to. V. V Output Low Voltage (Y) VOL IOL = µa, VCC =. V to. V. V IOL = µa, VCC =. V to.7 V. V IOL = µa, VCC =. V to.9 V. V IOL = ma, VCC =. V to.7 V. V IOL = ma, VCC =. V to.9 V. V IOL = ma, VCC =. V to. V. V LOGIC OUTPUTS VCC =. V to. V, GND = V Output High Voltage (Y) VOH IOH = µa, VCC =. V to. V. V IOH = µa, VCC =. V to.7 V. V IOH = µa, VCC =. V to.9 V VCC. V IOH = ma, VCC =. V to.7 V. V IOH = ma,vcc =. V to.9 V VCC. V IOH = ma, VCC =. V to. V. V Output Low Voltage (Y) VOL IOL = µa, VCC =. V to. V. V IOL = µa, VCC =. V to.7 V. V IOL = µa, VCC =. V to.9 V. V IOL = ma, VCC =. V to.7 V. V IOL = ma, VCC =. V to.9 V. V IOL = ma, VCC =. V to. V. V SWITCHING CHARACTERISTICS, VCC = VCC = VCC =. V ±. V Propagation Delay, tpd A Y Normal Mode tphl, tplh CL = pf, VT = VCC/.. ns A Y Normal Mode tphl, tplh CL = pf, VT = VCC/.. ns A Y Bypass Mode tphl, tplh CL = pf, VT = VCC/. ns ENABLE Time EN Y t EN CL = pf, VT = VCC/ ns DISABLE Time EN Y tdis CL = pf, VT = VCC/. ns ENABLE Time EN Y t EN CL = pf, VT = VCC/.. ns DISABLE Time EN Y tdis CL = pf, VT = VCC/. ns Rev. C Page of

4 ADG Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit VCC = VCC = VCC =. V ±. V Propagation Delay, tpd A Y Normal Mode tphl, tplh CL = pf, VT = VCC/.. ns A Y Normal Mode tphl, tplh CL = pf, VT = VCC/.. ns A Y Bypass Mode tphl, tplh CL = pf, VT = VCC/.. ns ENABLE Time EN Y t EN CL = pf, VT = VCC/ 7. ns DISABLE Time EN Y tdis CL = pf, VT = VCC/..7 ns ENABLE Time EN Y t EN CL = pf, VT = VCC/ 7.7 ns DISABLE Time EN Y tdis CL = pf, VT = VCC/. 7. ns VCC = VCC = VCC =. V ±. V Propagation Delay, tpd A Y Normal Mode tphl, tplh CL = pf, VT = VCC/.7 ns A Y Normal Mode tphl, tplh CL = pf, VT = VCC/. ns A Y Bypass Mode tphl, tplh CL = pf, VT = VCC/.. ns ENABLE Time EN Y t EN CL = pf, VT = VCC/ 7. ns DISABLE Time EN Y tdis CL = pf, VT = VCC/.. ns ENABLE Time EN Y t EN CL = pf, VT = VCC/ 7 ns DISABLE Time EN Y tdis CL = pf, VT = VCC/.. ns Input Leakage Current II VIN. V ± µa Output Leakage Current IO VIN. V ± µa POWER REQUIREMENTS Power Supply Voltages VCC.. V VCC.. V Quiescent Power Supply Current ICC Digital inputs = V or VCC µa ICC Digital inputs = V or VCC µa Increase in ICC per Input ΔICC VCC =. V, one input at. V; others at VCC or GND.7 µa Temperature range is as follows: B Version: C to + C. All typical values are at VCC = VCC = VCC, TA = C, unless otherwise stated. VIL and VIH levels are specified with respect to VCC, VOH, and VOL levels for Y are specified with respect to VCC, and VOH, and VOL levels are specified for Y with respect to VCC. Guaranteed by design, not subject to production test. See the Test Waveforms section. Rev. C Page of

5 Data Sheet ADG TEST WAVEFORMS INPUT V CC V T OUTPUT t PLH t PHL Figure. Propagation Delay V V OH V T V OL 97- V CC EN V T t EN V t DIS Y (A AT GND) V T Figure. Y Enable and Disable Times V OH V T V OL 97- V CC EN t EN V T V A t DIS V CC V A V CC V V OLH Y V T Figure. Y Enable and Disable Times V T V OL 97- Rev. C Page of

6 ADG ABSOLUTE MAXIMUM RATINGS TA = C, unless otherwise noted. Table. Parameter Rating VCC to GND. V to +. V Digital Inputs to GND. V to +. V A, EN. V to +. V A. V to VCC +. V DC Output Current ma Operating Temperature Range Industrial (B Version) C to + C Storage Temperature Range C to + C Junction Temperature C -Lead MSOP θja Thermal Impedance C/W θjc Thermal Impedance C/W -Lead SOT- θja Thermal Impedance C/W Lead Temperature, Soldering ( sec) C IR Reflow, Peak Temperature (< sec) C Soldering (Pb-Free) Reflow, Peak Temperature (+/ ) C Time at Peak Temperature sec to sec Data Sheet Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Only one absolute maximum rating may be applied at any one time. ESD CAUTION Rev. C Page of

7 Data Sheet ADG PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V CC A A EN ADG TOP VIEW (Not to Scale) 7 V CC Y Y GND Figure. -Lead SOT- Package (RJ-) 97- V CC Y Y GND ADG TOP VIEW (Not to Scale) V CC 7 A A EN Figure. -Lead MSOP Package (RM-) 97- Table. Pin Function Descriptions Pin No. RJ- RM- Mnemonic Description VCC Supply Voltage, can be any supply voltage from. V to. V. VCC Supply Voltage, can be any supply voltage from. V to. V. 7 A Input Referred to VCC. A Input Referred to VCC. 7 Y Output Referred to VCC. Y Output Referred to VCC. Voltage levels appearing at Y will be translated from a VCC voltage level to a VCC voltage level. EN Active Low Device Enable. When low, bypass mode is enabled; when high, the device is in normal mode. GND Device Ground. Rev. C Page 7 of

8 ADG Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS... V CC =.V. V CC =.V I CC (na)... I CC (na) V CC =.V V CC =.V... V CC =.V V CC =.V V CC =.V.... V CC (V) TEMPERATURE ( C) 97-7 Figure 7. ICC vs. VCC Figure. ICC vs. Temperature.... V CC = V CC =.V I CC (na)... I CC (µa) V CC = V CC =.V.. V CC =.V V CC =.V..... V CC (V) Figure. ICC vs. VCC V CC =.V k k M M M FREQUENCY (Hz) Figure. ICC vs. Frequency, Normal Mode 97- V CC =.V 7 V CC = V CC =.V V CC =.V I CC (na) V CC =.V V CC =.V I CC (µa) V CC = V CC =.V 7 TEMPERATURE ( C) Figure 9. ICC vs. Temperature 97- k k M M M FREQUENCY (Hz) Figure. ICC vs. Frequency, Bypass Mode 97-9 Rev. C Page of

9 Data Sheet ADG I CC (µa) V CC = V CC =.V V CC = V CC =.V TIME (ns) t EN k k M M M FREQUENCY (Hz) Figure. ICC vs. Frequency, Normal Mode 97- V CC = V CC t DIS SUPPLY (V) Figure. Y Enable, Disable Time vs. Supply 97- I CC (µa) V CC = V CC =.V V CC = V CC =.V TIME (ns) t EN t DIS V CC = V CC =.V k k M M M FREQUENCY (Hz) Figure. ICC vs. Frequency, Bypass Mode 97- TEMPERATURE ( C) Figure 7. Y Enable, Disable Time vs. Temperature 97- t EN TIME (ns) t DIS t EN TIME (ns) t DIS V CC = V CC SUPPLY (V) Figure. Y Enable, Disable Time vs. Supply 97- V CC = V CC =.V TEMPERATURE ( C) Figure. Y Enable, Disable Time vs. Temperature 97- Rev. C Page 9 of

10 ADG Data Sheet RISE/FALL TIME (ns) V CC =.V V CC =.V DATA RATE = Mbps t PLH, LOW-TO-HIGH TRANSITION t PHL, HIGH-TO-LOW TRANSITION RISE/FALL TIME (ns) 9 7 V CC =.V V CC =.V DATA RATE = Mbps t PLH, LOW-TO-HIGH TRANSITION t PHL, HIGH-TO-LOW TRANSITION 7 9 CAPACITIVE LOAD (pf) Figure 9. Rise/Fall Time vs. Capacitive Load, A Y, A Y CAPACITIVE LOAD (pf) Figure. Rise/Fall Time vs. Capacitive Load, A Y, Bypass Mode 97-9 RISE/FALL TIME (ns) V CC =.V V CC =.V DATA RATE = Mbps t PLH, LOW-TO-HIGH TRANSITION PROPAGATION DELAY (ns) 7 V CC =.V V CC =.V DATA RATE = Mbps t PLH, LOW-TO-HIGH TRANSITION t PHL, HIGH-TO-LOW TRANSITION t PHL, HIGH-TO-LOW TRANSITION 7 9 CAPACITIVE LOAD (pf) Figure. Rise/Fall Time vs. Capacitive Load, A Y, Bypass Mode CAPACITIVE LOAD (pf) Figure. Propagation Delay vs. Capacitive Load A Y 97- RISE/FALL TIME (ns) 9 7 V CC =.V V CC =.V DATA RATE = Mbps t PLH, LOW-TO-HIGH TRANSITION t PHL, HIGH-TO-LOW TRANSITION 7 9 CAPACITIVE LOAD (pf) Figure. Rise/Fall Time vs. Capacitive Load, A Y, A Y 97- PROPAGATION DELAY (ns) 7 t PLH, LOW-TO-HIGH TRANSITION t PHL, HIGH-TO-LOW TRANSITION V CC =.V V CC =.V DATA RATE = Mbps 7 9 CAPACITIVE LOAD (pf) Figure. Propagation Delay vs. Capacitive Load A Y 97- Rev. C Page of

11 Data Sheet ADG 7.. t PHL, A Y t PHL, A Y PROPAGATION DELAY (ns) t PLH, LOW-TO-HIGH TRANSITION t PHL, HIGH-TO-LOW TRANSITION V CC =.V V CC =.V DATA RATE = Mbps 7 9 CAPACITIVE LOAD (pf) Figure. Propagation Delay vs. Capacitive Load A Y, Bypass Mode 97- PROPAGATION DELAY (ns) t PLH, A Y t PLH, A Y V CC = V CC =.V TEMPERATURE ( C) Figure. Propagation Delay vs. Temperature, Normal Mode 97-7 t PHL, A Y PROPAGATION DELAY (ns) t PLH, A Y t PHL, A Y t PHL, A Y t PLH, A Y PROPAGATION DELAY (ns) t PLH, A Y V CC = V CC..... SUPPLY (V) Figure. Propagation Delay vs. Supply, Normal Mode. 97- V CC = V CC =.V TEMPERATURE ( C) Figure 9. Propagation Delay vs. Temperature, Bypass Mode 97- EN = HIGH.V PROPAGATION DELAY (ns) t PHL, A Y t PLH, A Y A A Y Y.V.V V CC = V CC..... SUPPLY (V) Figure 7. Propagation Delay vs. Supply, Bypass Mode. 97- DATA RATE = MHz CH.V CH mv M.ns CH.V CH.VΩ CH.VΩ Figure. Normal Mode VCC =. V, VCC =. V 97-7 Rev. C Page of

12 ADG Data Sheet DATA RATE = MHz A.V A.V.V.V Y Y.V Y DATA RATE = MHz CH.VΩ CH mv M.ns CH.7V Figure. Bypass Mode, VCC =. V, VCC =. V 97- CH.V CH.V CH.VΩ M.ns CH 9mV Figure. Bypass Mode, VCC =. V, VCC =. V 97- A A CH.V CH.V CH.VΩ CH.VΩ Y Y.V.V.V.V DATA RATE = MHz M.ns CH.V Figure. Normal Mode, VCC =. V, VCC =. V 97-9 VOLTAGE (V) SINK V CC =.V V CC =.V V CC =.V V CC =.V V CC =.V V CC = V CC = V CC SOURCE V CC =.V CURRENT (ma) Figure. Y and Y Source and Sink Current 97- Rev. C Page of

13 Data Sheet THEORY OF OPERATION The ADG is a bypass switch designed on a submicron process that operates from supplies as low as. V. The device is guaranteed for operation over the supply range. V to. V. It operates from two supply voltages, allowing bidirectional level translation, that is, it translates low voltages to higher voltages and vice versa. The signal path is unidirectional, meaning data may only flow from A Y. A AND EN INPUT The A and enable (EN) inputs have VIL/VIH logic levels so that the part can accept logic levels of VOL/VOH from Device or the controlling device independent of the value of the supply being used by the controlling device. These inputs (A, EN) are capable of accepting inputs outside the VCC supply range. For example, the VCC supply applied to the bypass switch could be. V while Device could be operating from a. V or. V supply rail, there are no internal diodes to the supply rails, so the device can handle inputs above the supply but inside the absolute maximum ratings. V CC V CC ADG NORMAL OPERATION Figure shows the bypass switch being used in normal mode. In this mode, the signal paths are from A Y and A Y. The device will level translate the signal applied to A to a VCC logic level (this level translation can be either to a higher or lower supply) and route the signal to the Y output, which will have standard VOL/VOH levels for VCC supplies. The signal is then passed through Device and back to the A input pin of the bypass switch. The logic level inputs of A are with respect to the VCC supply. The signal will be level translated from VCC to VCC and routed to the Y output pin of the bypass switch. Y output logic levels are with respect to the VCC supply. V CC DEVICE DEVICE DEVICE SIGNAL INPUT SIGNAL OUTPUT V CC V CC A Y A Y LOGIC EN BYPASS SWITCH Figure. Bypass Switch in Normal Mode 97- Rev. C Page of

14 ADG BYPASS OPERATION Figure illustrates the device as used in bypass mode. The signal path is now from A directly to Y, thus bypassing Device completely. The signal will be level translated to a VCC logic level and available on Y, where it may be applied directly to the input of Device. In bypass mode, Y is pulled up to VCC. Data Sheet The three supplies in Figure and Figure may be any combination of supplies, that is., VCC, VCC, and VCC may be any combination of supplies, for example,. V,. V, and. V. V CC V CC V CC DEVICE DEVICE DEVICE SIGNAL INPUT SIGNAL OUTPUT V CC V CC A Y A Y LOGIC EN BYPASS SWITCH Figure. Bypass Switch in Bypass Mode 97- Rev. C Page of

15 Data Sheet ADG OUTLINE DIMENSIONS PIN IDENTIFIER. BSC COPLANARITY.... MAX MAX..9 COMPLIANT TO JEDEC STANDARDS MO-7-AA Figure 7. -Lead Mini Small Outline Package [MSOP] (RM-) Dimensions shown in millimeters B PIN INDICATOR.9 BSC. BSC...9. MAX. MIN. MAX. MIN. MAX.9 MIN SEATING PLANE. MAX. MIN. BSC... COMPLIANT TO JEDEC STANDARDS MO-7-BA Figure. -Lead Small Outline Transistor Package [SOT-] (RJ-) Dimensions shown in millimeters ---A Rev. C Page of

16 ADG Data Sheet ORDERING GUIDE Model Temperature Range Package Description Branding Package Option ADGBRJ-REEL7 C to + C -Lead SOT- WB RJ- ADGBRJZ-REEL7 C to + C -Lead SOT- SS RJ- ADGBRMZ C to + C -Lead MSOP SS RM- Z = RoHS Compliant Part. Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D97--/(C) Rev. C Page of

Low Voltage 1.65 V to 3.6 V, Bidirectional Logic Level Translation, Bypass Switch ADG3233

Low Voltage 1.65 V to 3.6 V, Bidirectional Logic Level Translation, Bypass Switch ADG3233 Low Voltage. V to. V, Bidirectional Logic Level Translation, Bypass Switch FEATURES Operates from. V to. V supply rails Bidirectional level translation, unidirectional signal path -lead SOT- and MSOP packages