204PIN DDR3 1333Mhz SO-DIMM 2Rank 8GB With 512Mx8 CL9. Description. Placement. Features PCB: Transcend Information Inc.

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1 Description Placement The TS1GSK643H is a 1G x 64bits DDR Rank SO-DIMM. The TS1GSK643H consists of 16pcs 512Mx8bits DDR3 SDRAMs FBGA packages and a 2048 bits serial EEPROM on a 204-pin printed circuit board. The TS1GSK643H is a Dual In-Line Memory Module and is intended for mounting into 204-pin edge connector D sockets. B A Synchronous design allows precise cycle control with the E use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, C programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Features RoHS compliant products. JEDEC standard 1.5 ± Power supply J H I G F K DDQ=1.5 ± Clock Freq: 667MHZ for 1333Mb/s/. Programmable CAS Latency: 5, 6, 7, 8, 9 Programmable Additive Latency (Posted /CAS): 0, CL-2 or CL-1 clock PCB: Programmable /CAS Write Latency (CWL) = 7 (DDR3-1333) 8 bit pre-fetch Burst Length: 4, 8 Bi-directional Differential Data-Strobe Internal calibration through pin On Die Termination with ODT pin Serial presence detect with EEPROM Asynchronous reset Transcend Information Inc. 1

2 Dimensions Identification Side Millimeters Inches Symbol Function A 67.60± ±0.006 B C D E F 2.15± ±0.006 G H I J A0~A15, BA0~BA2 Address/Bank input DQ0~DQ63 Data Input / Output. DQS0~DQS7 Data strobes /DQS0~/DQS7 Differential Data strobes CK0, /CK0,CK1, /CK1 Clock Input. (Differential pair) CKE0, CKE1 Clock Enable Input. ODT0, ODT1 On-die termination control line /CS0, /CS1 DIMM Rank Select Lines. /RAS Row Address Strobe K 1.0± ±0.004 (Refer Placement) /CAS /WE 0~7 DD DDQ REF DQ/ REF CA DDSPD SA0~SA2 SCL SDA SS /RESET TT NC Column Address Strobe Write Enable Data masks/high data strobes oltage power supply oltage Power Supply for DQS Power Supply for Reference SPD EEPROM Power Supply I2C serial bus address select for EEPROM I2C serial bus clock for EEPROM I2C serial bus data for EEPROM Ground Set DRAMs Known State SDRAM I/O termination supply Connection Transcend Information Inc. 2

3 outs: 01 REFDQ 69 DQ DQS4 02 SS 70 DQ SS 03 SS 71 SS 139 SS 04 DQ4 72 SS 140 DQ38 05 DQ0 73 CKE0 141 DQ34 06 DQ5 74 CKE1 142 DQ39 07 DQ1 75 DD 143 DQ35 08 SS 76 DD 144 SS 09 SS 77 NC 145 SS 10 DQS0 78 A DQ BA2 147 DQ40 12 / DQS0 80 A DQ45 13 SS 81 DD 149 DQ41 14 SS 82 DD 150 SS 15 DQ2 83 A SS 16 DQ6 84 A /DQS5 17 DQ3 85 A DQ7 86 A7 154 DQS5 19 SS 87 DD 155 SS 20 SS 88 DD 156 SS 21 DQ8 89 A8 157 DQ42 22 DQ12 90 A6 158 DQ46 23 DQ9 91 A5 159 DQ43 24 DQ13 92 A4 160 DQ47 25 SS 93 DD 161 SS 26 SS 94 DD 162 SS 27 /DQS1 95 A3 163 DQ A2 164 DQ52 29 DQS1 97 A1 165 DQ49 30 /RESET 98 A0 166 DQ53 31 SS 99 DD 167 SS 32 SS 100 DD 168 SS 33 DQ CK0 169 /DQS6 34 DQ CK DQ /CK0 171 DQS6 36 DQ /CK1 172 SS 37 SS 105 DD 173 SS 38 SS 106 DD 174 DQ54 39 DQ A10/AP 175 DQ50 40 DQ BA1 176 DQ55 41 DQ BA0 177 DQ51 42 DQ /RAS 178 SS 43 SS 111 DD 179 SS 44 SS 112 DD 180 DQ60 45 /DQS2 113 /WE 181 DQ /CS0 182 DQ61 47 DQS2 115 /CAS 183 DQ57 48 SS 116 ODT0 184 SS 49 SS 117 DD 185 SS 50 DQ DD 186 /DQS7 51 DQ A DQ ODT1 188 DQS7 53 DQ /CS1 189 SS 54 SS 122 NC 190 SS 55 SS 123 DD 191 DQ58 56 DQ DD 192 DQ62 57 DQ TEST 193 DQ59 58 DQ REFCA 194 DQ63 59 DQ SS 195 SS 60 SS 128 SS 196 SS 61 SS 129 DQ SA0 62 /DQS3 130 DQ /EENT DQ DDSPD 64 DQS3 132 DQ SDA 65 SS 133 SS 201 SA1 66 SS 134 SS 202 SCL 67 DQ /DQS4 203 tt 68 DQ tt Transcend Information Inc. 3

4 Block Diagram /S0 /S1 /DQS0 DQS0 0 /DQS4 DQS4 4 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D0 D8 DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39 D4 D12 /DQS1 DQS1 1 /DQS5 DQS5 5 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 D1 D9 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47 D5 D13 /DQS2 DQS2 2 /DQS6 DQS6 6 DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 D2 D10 DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55 D6 D14 /DQS3 DQS3 3 /DQS7 DQS7 7 DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31 D3 D11 DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63 D7 D15 BA0~BA2 A0~A15 CKE1 CKE0 /RAS /CAS /WE ODT0 ODT1 CK0 /CK0 CK1 /CK1 240 Ohm *16 of D0 D15 BA0 BA2: SDRAMs D0 D15 A0-A15: SDRAMs D0 D15 CKE: SDRAMs D8 D15 CKE: SDRAMs D0 D7 /RAS: SDRAMs D0 D15 /CAS: SDRAMs D0 D15 /WE: SDRAMs D0 D15 ODT: SDRAMs D0 D7 ODT: SDRAMs D8 D15 CK: SDRAMs D0 D7 /CK: SDRAMs D0 D7 CK: SDRAMs D8 D15 /CK: SDRAMs D8 D15 SCL SA0 SA1SA2 NOTE: EEPROM WP A0 A1 A2 DDSPD DD/DDQ SDA REFDQ SS REFCA EEPROM D0~D15 D0~D15 D0~D15 D0~D15 DQ-to-I/O wiring is shown as recommended but may be changed. DQ,DQS,/DQS,ODT,,CKE,/S relationships must be maintained as shown. DQ,,DQS,/DQS resistors: Refer to associated topology diagram. For each DRAM,a unique resistor is connected to ground. The resistor is 240 Ohm +/-1% This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications at any time without prior notice. Transcend Information Inc. 4

5 Operating Temperature Condition Parameter Symbol Rating Unit te Operating Temperature TOPER 0 to 85 C 1,2 te: 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard. 2. At 0-85 C, operation temperature range are the temperature which all DRAM specification will be supported. Absolute imum DC Ratings Parameter Symbol alue Unit tes oltage on DD relative to ss DD -0.4 ~ oltage on DDQ pin relative to ss DDQ -0.4 ~ oltage on any pin relative to ss IN, OUT -0.4 ~ Storage temperature TSTG -55~+100 C 1,2 te: 1.Stress greater than those listed under Absolute imum Ratings may cause permanent damage to the stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2.Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. AC & DC Operating Conditions Recommended DC operating conditions (SSTL 1.5) Parameter Symbol Rating Min Typ. Unit tes Supply voltage DD , 2 Supply voltage for Output DDQ , 2 I/O Reference oltage (DQ) REF DQ (DC) 0.49*DDQ 0.50*DDQ 0.51*DDQ 3, 4 I/O Reference oltage (CMD/ADD) REF CA (DC) 0.49*DDQ 0.50*DDQ 0.51*DDQ 3, 4 AC Input Logic High IH(AC) REF AC Input Logic Low IL(AC) - - REF DC Input Logic High IH(DC) REF DD DC Input Logic Low IL(DC) SS - REF-0.1 te: There is no specific device DD supply voltage requirement for SSTL-1.5 compliance. 1.Under all conditions DDQ must be less than or equal to DD. 2.DDQ tracks with DD, AC parameters are measured with DD and DDQ tied together. 3.Peak to peak AC noise on REF may not allow deviate from REF(DC) by more than +/-1% DD. 4.For reference: approx. DD/2 +/-15m 5.For DQ and, REF=REFDQ. For input only pins except RESET, or REF=REFCA. AC Input Level for Differential Signals Parameter Symbol alue Unit te Differential Input Logical High IHdiff Differential Input Logical Low ILdiff m Transcend Information Inc. 5

6 IDD Specification parameters Definition ( IDD values are for full operating range of voltage and Temperature) Transcend Information Inc. 6 Parameter Symbol. Unit te Operating One bank Active-Precharge current; tck = tck(idd), trc = trc(idd), tras = trasmin(idd); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tck = tck(idd), trc = trc (IDD), tras = trasmin(idd), trcd = trcd(idd); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tck = tck(idd); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tck = tck(idd); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tck = tck(idd); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD0 480 ma IDD1 560 ma IDD2P 240 ma IDD2Q 320 ma IDD2N 320 ma Active power - down current; All banks open; tck = tck(idd); CKE is LOW; Other control and address bus inputs IDD3P 320 ma are STABLE; Data bus inputs are FLOATING Active standby current; All banks open; tck = tck(idd), tras = trasmax(idd), trp = trp(idd); CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs IDD3N 400 ma are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tck = tck(idd), tras = trasmax(idd), trp = trp(idd); CKE is HIGH, /CS is HIGH IDD4R 840 ma between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL = CL(IDD), AL = 0; tck = tck(idd), tras = trasmax(idd), trp = trp(idd); CKE is HIGH, /CS is HIGH IDD4W 880 ma between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD4R Burst refresh current; tck = tck(idd); Refresh command at every trfc(idd) interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are IDD ma SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and /CKat 0; CKE 0.2; Other control and address bus inputs are IDD6 240 ma FLOATING; Data bus inputs are FLOATING Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = trcd(idd)-1*tck(idd); tck =tck(idd), trc = trc(idd), trrd = trrd(idd), trcd = 1*tCK(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are STABLE during Deselects; Data pattern is same as IDD4R IDD ma te: 1. Module IDD was calculated on the specific brand DRAM component IDD and can be differently measured according to DQ loading capacitor.

7 Slew Rate Definition for Single Ended AC Input Signals Input Setup Time (tis) Input Hold Time (tih) SWING(max) delta TFS Falling Slew = SWING(max) delta TFH Falling Slew = REF IL(AC) max delta TFS delta TRS Rising Slew = Input Slew Rate for Setup REF IL(DC) max delta TFH delta TRH Input Slew Rate for Hold DD IH(AC) min IH(DC) min REF IL(DC) max IL(AC) max SSQ IH(AC)min delta TRS REF DD IH(AC) min IH(DC) min REF IL(DC) max IL(AC) max SSQ IH(DC)min Rising Slew = delta TRH REF Slew Rate Definition for Differential Input Signals IHdiff min REF ILdiff max delta TF diff delta TR diff IHdiff min ILdiff Falling Slew = delta TF diff max Differential Input Slew Rate IHdiff min ILdiff Rising Slew = delta TR diff max Input/Output Capacitance (DD = 1.5, DDQ = 1.5, TA = 25 C) Parameter Symbol Min Unit Input capacitance (CK and /CK) Input capacitance (All other input pins) Input capacitance ( pins) Input capacitance (DQ,, DQS, /DQS, TDQS, /TDQS) CCK CI C CDIO pf pf pf pf te: is internally loaded to match DQ and DQS identically. Transcend Information Inc. 7

8 Timing Parameters & Specifications Parameter Symbol Min Unit te Average Clock Period, CL=9 / CWL=7 tck 1.5 <1.875 ns CK high-level width tch tck CK low-level width tcl tck DQS, /DQS to DQ skew, per group, per access tdqsq ps DQ output hold time from DQS, /DQS tqh tck DQ low-impedance time from CK, /CK tlz(dq) ps DQ high-impedance time from CK, /CK thz(dq) ps Data setup time to DQS, /DQS reference to ih(ac)il(ac) levels Data hold time to DQS, /DQS reference to ih(ac)il(ac) levels tds 30 - ps tdh 65 DQ and input pulse width for each input tdipw ps DQS, /DQS Read preamble trpre tck DQS, /DQS differential Read postamble trpst tck DQS, /DQS Write preamble twpre tck DQS, /DQS Write postamble twpst tck DQS, /DQS low-impedance time tlz(dqs) Ps DQS, /DQS high-impedance time thz(dqs) ps DQS, /DQS differential input low pulse width tdqsl tck DQS, /DQS differential input high pulse width tdqsh tck DQS, /DQS rising edge to CK, /CK rising edge tdqss tck DQS, /DQS falling edge setup time to CK, /CK rising edge DQS, /DQS falling edge hold time to CK, /CK rising edge Delay from start of Internal write transaction to Internal read command tdss tck tdsh tck twtr (4tck, 7.5ns) Write recovery time twr 15 - ns Mode register set command cycle time tmrd 4 - tck /CAS to /CAS command delay tccd 4 - nck Auto precharge write recovery + precharge time tdal twr+trp/tck nck Active to active command period for 1KB page size trrd (4tck, 6ns) - ns Active to active command period for 2KB page size trrd (4tck,7.5ns) - ns Four Activate Window for 1KB page size products tfaw 30 - ns - ps Transcend Information Inc. 8

9 Four Activate Window for 2KB page size products tfaw 45 - ns Power-up and RESET calibration time tinitl tck rmal operation Full calibration time toper tck rmal operation short calibration time tcs 64 - tck Exit self refresh to commands not requiring a locked txs (5tCK, DLL - ns trfc+10) Exit self refresh to commands requiring a locked DLL txsdll tdll(min) - tck Internal read to precharge command delay Minimum CKE low width for Self refresh entry to exit timing trtp (4tck, 7.5ns) - ns tckesr tck(min)+1tck - - Exit power down with DLL to any valid command: Exit Precharge Power Down with DLL txp (3tCK, 6ns) CKE minimum pulse width (high and low pulse width) tcke (3tCK, 5.625ns) - - Asynchronous RTT turn-on delay (Power-Down mode) taonpd ns Asynchronous RTT turn-off delay (Power-Down mode) taofpd ns ODT turn-on taon ps ODT turn-off taof tck - Transcend Information Inc. 9

10 SERIAL PRESENCE DETECT SPECIFICATION Serial Presence Detect Byte. Function Described Standard Specification endor Part 0 CRC:0-116Byte Number of SPD Bytes written / SPD device size / CRC coverage during module production SPD Byte use: 176Byte SPD Byte total: 256Byte 92 1 SPD Revision ersion Key Byte / DRAM Device Type DDR3 SDRAM 0B 3 Key Byte / Module Type SODIMM 03 4 SDRAM Density and Banks 4Gb 8banks 04 5 SDRAM Addressing ROW:16, Column: Reserved Module Organization 2Rank / x Module Memory Bus Width n ECC, 64bit 03 9 Fine Timebase Dividend and Divisor 2.5ps Medium Timebase Dividend 0.125ns Medium Timebase Divisor 0.125ns SDRAM Minimum Cycle Time (tckmin) 1.5ns 0C 13 Reserved CAS Latencies Supported, Least Significant Byte 5, 6, 7, 8, 9 3E 15 CAS Latencies Supported, Most Significant Byte Minimum CAS Latency Time (taamin) ns Minimum Write Recovery Time (twrmin) 15ns Minimum /RAS to /CAS Delay Time (trcdmin) ns Minimum Row Active to Row Active Delay Time (trrdmin) 6ns Minimum Row Precharge Time (trpmin) ns Upper Nibble for tras and trc Minmum Active to Precharge Time (trasmin) 36ns Minmum Active to Active/Refresh Time (trcmin) ns Minmum Refresh Recovery Time (trfcmin), Least Significant Byte 300ns Minmum Refresh Recovery Time (trfcmin), Most Significant Byte 300ns Minmum Internal Write to Read Command Delay Time (twtmin) 7.5ns 3C 27 Minimum Internal Read to Precharge Command Delay Time (trtpmin) 7.5ns 3C 28 Upper Nibble for tfaw 30ns Minmum Four Active Window Delay Time (tfawmin) 30ns F0 30 SDRAM Optional Features DLL off Mode, R/6, R/ SDRAM Thermal and Refresh Options ODTs, ASR Reserved Module minal Height 30mm 0F 61 Module Thickness Planar Double Sides 11 Transcend Information Inc. 10

11 62 Reference Raw Card Used R/C F Address Mapping from Edge Connector to DRAM Standard Reserved Module Manufacturer ID Code, Least Significant Byte Transcend Module Manufacturer ID Code, Most Significant Byte Transcend 4F 119 Module Manufacturing Location Taipei Module Manufacturing Date Module Serial Number Cyclical Redundancy Code - 27, B Module Part Number TS1GSK643H Revision Code DRAM Manufacturer ID Code By Manufacturer ariable Manufacturer Specific Data By Manufacturer ariable Open for customer use Undefined 00 Transcend Information Inc. 11