VersaClock 6E 5P49V6967/68 Evaluation Board User Manual. Contents. List of Figures

Transcription

1 VersaClock E P49V9/ Evaluation Board User Manual Contents. Introduction...3. Board Overview Board Power Supply Connecting the Board to a Computer.... Functions of the U Switches on the P49V Functions of the U Switches on the P49V Operating Modes.... On-Board Crystal Configuration and Setup Board Schematics...3. Signal Termination Options...9. Termination Options for the P49V9 Board...0. Termination Options for the P49V9 Board.... Ordering Information Revision History... List of Figures Figure. P49V9 EVB Top View...3 Figure. P49V9 EVB Top View... Figure 3. VDDO_ Voltage Selector on the P49V9 and P49V9 EVBs... Figure 4. VDDA/D Power Source Selector P49V9 EVB Example... Figure. VDDO LP-HCSL Power Source Selector P49V9 EVB Example... Figure. Aardvark Connector on the P49V9 and P49V9 EVBs... Figure. U Switches on the P49V9...9 Figure. U Switches on the P49V9...0 Figure 9. Crystal Circuit P49V9 EVB Example... Figure 0. P49V9 Evaluation Board Schematics Page...3 Figure. P49V9 Evaluation Board Schematics Page...3 Figure. P49V9 Evaluation Board Schematics Page Figure 3. P49V9 Evaluation Board Schematics Page 4... Figure 4. P49V9 Evaluation Board Schematics Page... Figure. P49V9 Evaluation Board Schematics Page... Figure. P49V9 Evaluation Board Schematics Page 3... Figure. P49V9 Evaluation Board Schematics Page 4... Figure. P49V9/ Output Termination Options Integrated Device Technology, Inc. January, 0

2 List of Tables Table. P49V9 EVB Pins and Functions...4 Table. P49V9 EVB Pins and Functions... Table 3. Functions of U Switches on the P49V9...9 Table 4. Functions of U Switches on the P49V9...0 Table. P49V9 Termination Options for OUTPUT...0 Table. P49V9 Termination Options for OUTPUT...0 Table. P49V9 Termination Options for OUTPUT4...0 Table. P49V9 Termination Options for OUTPUT... Table 9. P49V9 Termination Options for OUTPUT... Table 0. P49V9 Termination Options for OUTPUT Integrated Device Technology, Inc. January, 0

3 . Introduction The P49V9 and P4V9 Evaluation Boards are designed to help users evaluate the VersaClock E P49V9 and P49V9 respectively. When the Evaluation Board (EVB) is connected via USB to the user s computer running the IDT s VersaClock E Timing Commander Software, the P49V9/ can be configured and programmed to generate frequencies with best-in-class performance. In addition to one single-ended output and three programmable differential outputs, the P49V9 has four additional LP-HCSL outputs and the P49V9 has eight additional LP-HCSL outputs.. Board Overview Figure. P49V9 EVB Top View Integrated Device Technology, Inc. 3 January, 0

4 Table. P49V9 EVB Pins and Functions Note: See Figure for reference numbers in the following table. Ref. Name On-Board Connector Label Function Output 0 J3 Single-ended LVCMOS clock output Output J9, J0 Differential clock output 3 VDDD_J J VDD jack for VDD digital external power supply 4 VDDO_0 JP Power supply voltage selector for Output 0 Output J, J Differential clock output VDDO_ JP4 Power supply voltage selector for Output Output J3, J3 LP-HCSL differential clock output Output 3 J, J Differential clock output 9 VDDO_ JP Power supply voltage selector for Output 0 XIN J Input for overdriving XIN pin Ground Jack J Ground jack for external power supply P49V9 U Evaluation device 3 VDDO_3 JP Power supply selector for LP-HCSL outputs 4 VDDO LP-HCSL Jack J33 VDD jack for VDDO_LP-HCSL (.V) external power supply Aardvark Connector JP For Aardvark connection Output J9, J30 LP-HCSL differential clock output DIP Switch U S: Output Enable (OE/SD) S: Sel0 S3: Sel S4: OE Buffer S: OEB3, S: OEB, S: Sel [:0] ; Default: IC mode VDDO_4 JP Power supply voltage selector for Output 4 9 Output 4 J3, J4 Differential clock output 0 USB Interface J Used for connection with the user s computer for interaction with the IDT Timing Commander Software. Output J, J LP-HCSL differential clock output VDDO Jack J VDD jack for external power supply 0 Integrated Device Technology, Inc. 4 January, 0

5 Figure. P49V9 EVB Top View Integrated Device Technology, Inc. January, 0

6 Table. P49V9 EVB Pins and Functions Note: See Figure for reference numbers in the following table. Ref. Name On-Board Connector Label Function Output 0 J3 Single-ended LVCMOS clock output Output 0 J3, J3 LP-HCSL differential clock output 3 Output J39, J40 LP-HCSL differential clock output 4 VDDD_J J VDD jack for VDD digital external power supply Ground Jack J Ground jack for external power supply VDDO_0 JP Power supply voltage selector for Output 0 Output J9, J0 Differential clock output Output 9 J3, J3 LP-HCSL differential clock output 9 VDDA/D JP3 Power supply voltage selector for VDDA and VDDD 0 VDDO_ JP4 Power supply voltage selector for Output VDDO_ JP Power supply voltage selector for Output Output J, J Differential clock output 3 XIN J Input for overdriving the XIN pin. 4 Output J33, J34 LP-HCSL differential clock output P49V9 U Evaluation device VDDO_3 JP Power supply selector for LP-HCSL outputs Output 3 J4, J43 Differential clock output Aardvark Connector JP For Aardvark connection 9 Output J3, J3 LP-HCSL differential clock output 0 DIP Switch U S: Output Enable (OE/SD) S: Sel0 S3: Sel S4: OE Buffer S: OEB-0 S: OEB3- S: Sel [:0] ; Default: IC mode VDDO_4 JP Power supply voltage selector for Output 4 Output 4 J3, J4 Differential clock output 3 Output J9, J30 LP-HCSL differential clock output 4 USB Interface J Used for connection with the user s computer for interaction with the IDT Timing Commander Software. Output J, J LP-HCSL differential clock output VDDO Jack J VDD jack for external power supply VDDO LP-HCSL Jack J4 VDD jack for VDDO_LP-HCSL (.V) external power supply. 0 Integrated Device Technology, Inc. January, 0

7 3. Board Power Supply The voltage for each of the 4 VDDO pins can be selected with jumpers. In the -pin configuration, the center pin is connected to the VDDO pin on the P49V9/ device. The 4 pins around it are connected to different power sources. A jumper connects the VDDO pin to a power source of choice. In Figure 3, the voltage for VDDO_ is chosen to be 3.3V. Move the jumper to the right side to select.v, to the bottom to select.v, or to the left to select the VDDO_J Jack. The 3.3V,.V, and.v supplies are from on-board regulators that get their power from the USB connector. The VDD jacks are for connecting to a bench power supply. Figure 3. VDDO_ Voltage Selector on the P49V9 and P49V9 EVBs For both EVBs, JP3 selects the power source for the VDDA and VDDD pins: either an on-board 3.3V regulator or the VDDD_J jack for a bench power supply. In Figure 4, the source for VDDA and VDDD is chosen to be the on-board 3.3V regulator. Figure 4. VDDA/D Power Source Selector P49V9 EVB Example 0 Integrated Device Technology, Inc. January, 0

8 For both EVBs, JP selects the power source for the VDDO LP-HCSL pins between an on-board.v regulator and the VDDO-LP-HCSL jack for a bench power supply. In Figure, the source for VDDO LP-HCSL is chosen to be the on-board.v regulator. Figure. VDDO LP-HCSL Power Source Selector P49V9 EVB Example 4. Connecting the Board to a Computer The Evaluation Board can be connected to a computer via the USB connector. The on-board USB-to-IC bridge (FTDI chip) handles the data communication and the +V in the USB bus powers the on-board regulators. Using a bench power supply with the VDD jacks is optional. The board can fully function with just the USB cable to a computer. IDT s Timing Commander Software can control the P49V9/ on the board. Timing Commander is compatible with both the on-board USB-to-IC bridge and the Aardvark adapter. Timing Commander displays a block diagram for entering the configuration and allows programming that configuration into the P49V9 or P49V9 on the board. Timing Commander handles defining the proper hex-code sequence to program into the device. The Aardvark adapter can be plugged into JP as shown in Figure. In this case, also connect the USB port to a computer to power the FTDI chip so it does not load the SDA and SCL lines. With the USB cable connected to a computer, the USB can be used to power the P49V9 or P49V9 EVB as well. Figure. Aardvark Connector on the P49V9 and P49V9 EVBs LD Green R.K VDDD R.K R 0 R 0 TP4 TP3 SCL_AADVAR SDA_AADVAR 3 9 AARDVARK JP 4 0 Header_0Pin SEL0_SCL SEL_SDA SEL0_SCL {,3,} SEL_SDA {,3,} 0 Integrated Device Technology, Inc. January, 0

9 . Functions of the U Switches on the P49V9 On the P49V9, the switch block U has switches. Only of the switches are used. Figure. U Switches on the P49V9 The switches connect to pins on the P49V9 device. The middle position leaves the pin open. This is the default for each switch. Move to the + side to pull the pin HIGH and move to the side to pull the pin LOW. Table 3. Functions of U Switches on the P49V9 Switch Name Function OE Connects to the SD/OE pin for Output Enable or Shut-Down operation. SEL0 Connects to the SEL0/SCL pin. The main purpose of this switch is to operate SEL0 when the device has started in Hardware Select Mode. This switch can also be used to add an extra pull-up (0KΩ) on the SCL line for IC operation. 3 SEL Connects to the SEL/SDA pin. The main purpose of this switch is to operate SEL when the device has started in Hardware Select Mode. This switch can also be used to add an extra pull-up (0KΩ) on the SDA line for IC operation. 4 OE Buffer Connects to the OE Buffer pin to enable/disable only the LP-HCSL outputs. OEB3, Connects to the OEB3, pin to enable/disable only outputs 3 and. OEB, Connects to the OEB, pin to enable/disable only outputs and. Unused. Pulls on the OUT0_SELB_IC pin on the device to select the operation mode at power up. The state of the OUT0_SELB_IC pin is latched at power up. The operation mode effectively sets the function of the SEL0/SCL and SEL/SDA pins. The OUT0_SELB_IC pin has an on-chip pull-down so switch in the center or position has the same effect and results in startup with the IC Mode. In IC Mode, the two pins have the SDA and SCL function for IC operation. With the switch in the + position, the device will start in Hardware Select Mode. In Hardware Select Mode, the two pins have the SEL0 and SEL function for selecting a preprogrammed configuration. 0 Integrated Device Technology, Inc. 9 January, 0

10 . Functions of the U Switches on the P49V9 On the P49V9, the switch block U has switches. Only of the switches are used. Figure. U Switches on the P49V9 The switches connect to pins on the P49V9 device. The middle position leaves the pin open. This is the default for each switch. Move to the + side to pull the pin HIGH and move to the side to pull the pin LOW. Table 4. Functions of U Switches on the P49V9 Switch Name Function OE Connects to the SD/OE pin for Output Enable or Shut-Down operation. SEL0 Connects to the SEL0/SCL pin. The main purpose of this switch is to operate SEL0 when the device has started in Hardware Select Mode. This switch can also be used to add an extra pull-up (0KΩ) on the SCL line for IC operation. 3 SEL Connects to the SEL/SDA pin. The main purpose of this switch is to operate SEL when the device has started in Hardware Select Mode. This switch can also be used to add an extra pull-up (0KΩ) on the SDA line for IC operation. 4 OE Buffer Connects to the OE Buffer pin to enable/disable only the LP-HCSL outputs. OEB_0 Connects to the OEB_0 pin to enable/disable only outputs,, 9 and 0. OEB3_ Connects to the OEB3_ pin to enable/disable only outputs 3,, and. Unused. Pulls on the OUT0_SELB_IC pin on the device to select the operation mode at power up. The state of the OUT0_SELB_IC pin is latched at power up. The operation mode effectively sets the function of the SEL0/SCL and SEL/SDA pins. The OUT0_SELB_IC pin has an on-chip pull-down so switch in the center or position has the same effect and results in startup with the IC Mode. In IC Mode, the two pins have the SDA and SCL function for IC operation. With the switch in the + position, the device will start in Hardware Select Mode. In Hardware Select Mode, the two pins have the SEL0 and SEL function for selecting a preprogrammed configuration. 0 Integrated Device Technology, Inc. 0 January, 0

11 . Operating Modes As explained above at switch, the P49V9/ can start up in two different operating modes: IC Mode or Hardware Select Mode. The Evaluation Board is shipped with a blank P49V9/ device, without a configuration preprogrammed into the one-time-programmable (OTP) memory. Without a configuration preprogrammed, the Hardware Select Mode cannot be used. The blank device will start with a default or test configuration where output 0 and output are enabled. Output 0 will be MHz and output will be 00MHz with LVCMOSD logic. Next, Timing Commander can be used to program a configuration into the volatile registers in the device to test a configuration. This works without burning the permanent OTP memory, and most users of this Evaluation Board do not burn the OTP. This way the board can be used repeatedly to test configurations. Burning configurations into OTP is only useful when studying the Hardware Select Mode and the transition from one configuration to another. Important Note: Burning configurations into the OTP is permanent and cannot be undone.. On-Board Crystal A MHz crystal (X_NP) is installed on the P49V9/ Evaluation Board. Figure 9 shows the location on the board and the schematic for the P49V9 EVB. Refer to Figure for the schematic for the P49V9 EVB. Figure 9. Crystal Circuit P49V9 EVB Example C3 0pF_NP 4 3 C X_NP 0pF_NP R R9 XIN 0_NP XIN {} X MHz(pf ) 0_NP XOUT XOUT {} Unpopulate C when Crystal is used as input reference J XIN_CONN R 33 C uf XIN R 49.9_NP The board is shipped with a small MHz SMD crystal installed. The crystal can be replaced with a different frequency if needed. Note: The output with the default or test mode will only work when using a MHz crystal. 0 Integrated Device Technology, Inc. January, 0

12 A thru-hole crystal can be assembled in the X position. In this case, remove the small MHz crystal and also assemble the resistors R and R9 to connect the thru-hole crystal. Another useful modification can be to remove the MHz crystal and assemble C to connect the SMA connector J. Now a clock from a generator or other source can be used to drive the XIN pin. In this case, also assemble R when termination of the external clock is needed. See the requirements for the XIN amplitude in the P49V9/ Datasheet. Essentially, the amplitude on XIN should not exceed.vpp. Recommendation: Use.0Vpp for most tests. When doing phase noise measurements of the output clocks, use a very low noise clock for XIN. The best phase noise at the outputs is achieved when using a crystal. Only the very best of low noise RF signal generators connected to XIN can result in the same phase noise performance. 9. Configuration and Setup Use the following steps to setup the P49V9/ EVB using IC and start the configuration of the board.. Set the SEL switch (switch ) of the U dip switch bank to "O" to select IC Mode.. Connect J to a USB port of the user s computer using the USB cable supplied with the board. 3. Launch IDT s VersaClock E Timing Commander Software according to the instructions in the VersaClock E Timing Commander User Guide. The software and guide can be downloaded on the product pages: Following the Getting Started steps in the Timing Commander Software, an IC connection is established between the GUI software and the VersaClock E P49V9/.. Select Open Settings File to use existing settings, or select New Settings File and choose P49V9 or P49V9 depending on the Evaluation Board. On the same screen, browse for a personality file to be used with the Evaluation Board by clicking on the button at the bottom right.. Connect to the EVB by clicking on the microchip icon located at the top right of the Timing Commander screen.. Once the EVB is connected, new options will be available on a green background indicating that the EVB has successfully connected with the board. Write settings to the chip by clicking on the Write all registers to the chip option.. All enabled outputs should now be available for measurement. 0 Integrated Device Technology, Inc. January, 0

13 0. Board Schematics Figure 0. P49V9 Evaluation Board Schematics Page P49V9 CONNECTIONS VDDO0 VDDD XOUT {3} XOUT XIN {3} XIN SEL_SDA {3,} SEL_SDA SEL0_SCL {3,} SEL0_SCL SD_OE {3} SD_OE OE_buf f er {3} OE_buf f er OEB3, {3} OEB3, OEB, {3} OEB, Stand Offs H H H3 H4 C OUT R uF U VDD_CORE 3 VDD VDD 3 VDD3 VDD4 NC NC 3 NC3 NC4 3 XOUT XIN/REF SEL/SDA SEL0/SCL 0 SD/OE 3 OE_BUFFER OEB3, 34 OEB, IDTP49V9 4 EPAD 4 VDDA VDDO_ 4 VDDO_ 3 VDDO_3 39 VDDO0 40 OUT0_SEL_ICB 33 VDDO 3 OUT 3 OUTB 30 VDDO 9 OUT OUTB VDDO4 9 OUT4 0 OUT4B 4 OUT3 3 OUT3B OUT OUTB OUT 9 OUTB OUT OUTB LP HCSL TERMINATION J30 VDDA {3} OUT0_SELB_IC VDDO_3 VDDO0 VDDO0 OUT0_SELB_IC VDDO VDDO R0 0 OUT R09 0 OUTB VDDO VDDO R0 0 OUT R 0 OUTB VDDO4 VDDO4 OUT4 OUT4B OUT3 OUT3B OUT OUTB OUT OUTB OUT OUTB Place 33 OHM Resistors Close to Main Device Place AC Coupling Capacitors Close to SMA C OUT3 R9 33 J 0.uF C4 OUT0_SELB_IC R9 33 J3 0.uF 3.3V LVPECL TERMINATION C OUT J0 0.uF C OUTB J9 R0 0_% 0.uF R 0_% R3 0 C OUT J 0.uF C9 OUTB J R DNP 0.uF R DNP R3 DNP R _NP R4 4_NP VDDO R R9 _NP _NP R3 R4 4_NP 4_NP VDDO R30 R3 _NP _NP R3 R3 4_NP 4_NP OUTB R9 33 OUT R9 33 OUTB R9 33 C3 0.uF C4 0.uF C 0.uF J9 J3 J3 OUT3B R9 33 OUT R93 33 OUTB R94 33 C9 0.uF C0 0.uF C 0.uF J J J OUT4 OUT4B R 33 R 33 R9 DNP.V and 3.3V HCSL TERMINATION R90 DNP C 0.uF C 0.uF J4 J3 VDDO4 R3 R40 _NP _NP R4 R4 4_NP 4_NP Place 33 OHM Resistors Close to Main Device R9 & R90 Should be Closer to the SMA Figure. P49V9 Evaluation Board Schematics Page C3 0pF_NP 3 R9 C X_NP 0pF_NP R 4 XIN XIN {} 0_NP X MHz(pf ) 0_NP XOUT XOUT {} VDDD U VCC VEE DIP_SW s s s3 s4 s s s s R R R 0K 0K 0K SD_OE SEL0_SCL SEL_SDA OE_buf f er OEB3, OEB, OUT0_SELB_IC SD_OE {} SEL0_SCL {,3,} SEL_SDA {,3,} OE_buf f er {} OEB3, {} OEB, {} LABEL: OE SEL0 SEL OE_buffer OEB3, OEB, OUT0_SELB_IC {} SEL[:0]/IC VDDD J XIN_CONN R 33 R 49.9_NP C uf XIN Unpopulate C when Crystal is used as input reference LD Green R.K R.K R 0 R 0 TP4 TP3 SEL0_SCL SEL_SDA JP SCL_AADVAR SDA_AADVAR 3 9 SEL0_SCL {,3,} SEL_SDA {,3,} AARDVARK 4 0 Header_0Pin 0 Integrated Device Technology, Inc. 3 January, 0

14 L L 3mm Figure. P49V9 Evaluation Board Schematics Page 3 J J VDD_J _J VDD_J C0 0.uF C4 0uF C LABEL AS INDICATED FOR 3-PIN HEADERS 0.uF VDDA_J VDDA_REG JP3 VDDA_REG VDDA_ R3. FB BLMBBSND C 0.uF FB3 BLMBBSND C 0.uF C 0uF C 0uF VDDA C3 0.uF VDDD C 0.uF C 0.uF C 0.uF C 0.uF J C 0.uF VDDO_J C9 0.uF C 0.uF C9 0uF LABEL ON EACH RESPECTIVE PIN OF HEADERS:.V,.V, 3.3V TP VDDO_J JP TP TP3 VDDO_J JP4 TP4 VDDO_.V VDDO_.V VDDO_3.3V VDDO_.V VDDO_.V VDDO_3.3V VDDO_0 VDDO_ VDDO_0 C 0.uF VDDO_ FB BLMBBSND C9 0.uF FB4 BLMBBSND C 0uF C30 0uF C 0.uF C3 0.uF VDDO0 VDDO Locate near DUT power pin TP VDDO_J VDDO_.V VDDO_ VDDO_ FB VDDO VDDO_.V BLMBBSND USB_V C3 0.uF C0 0uF U3 3 INPUT OUTPUT_ OUTPUT_ Adjust LM3DCY R 0_% 4 R4 43_% VDDO_.V C3 0uF Tantalum preferred USB_V C3 0.uF C 0uF U4 VIN 3 VOUT_ 4 VOUT_3 Adjust LM3LBD R NC_ VOUT_ VOUT_ NC_ 43_% R 43_% VDDO_.V C3 0uF J33 VDDO_3_J JP TP JP VDDO_3.3V VDDO_.V C3 0.uF VDDO_3 FB VDDO_3 BLMBBSND C0 0.uF C33 0uF C9 0uF C34 0.uF VDDO_3 C 0.uF USB_V C4 0.uF C 0uF U VIN 3 VOUT_ 4 VOUT_3 Adjust LM3LBD NC_ VOUT_ VOUT_ NC_ R 43_% VDDO_3.3V C4 0uF PCB Copper Decal Recommandations for LM3LD SO-.0 oz Copper TP0 VDDO_J JP TP9 VDDO_.V VDDO_.V VDDO_3.3V VDDO_4 FB VDDO_4 BLMBBSND C3 0.uF C 0uF C4 0.uF VDDO4 USB_V VDDA_REG R9 40_% USB_V {} VDDA_REG {} L = mm is more than enough Header Alignment: Single pin header above and below the center pin of 3-pin header so that center pin can be jumped with the surrounding 4 pins, as shown at left. 0 Integrated Device Technology, Inc. 4 January, 0

15 9 Figure 3. P49V9 Evaluation Board Schematics Page 4 C4 0nF {4} USB_V TP L 300ohm A R R0 0 L 00 ohm 00mA C4 0.uF TP C 4uF 00 J VBUS D- D+ 3 4 USB PORT L3 300ohm A R3 C90 C9 R C4 33pF 0uF 0.uF R4.K C Y MHz 33pF XTIN LD Green VCC3_3V 3V3_USB C 0.04uF R0 0K XTOUT VCC3 C49 0.uF VCC3 C0 0uF R 40 C 3V3_USB 0.uF U 3V3OUT USBDM USBDP RSTOUT# 43 XTIN 44 XTOUT 4 RESET# 4 EECS EESK EEDATA 4 TEST f t3_chip 4 AVCC 4 A VCC 3 VCC VCCIOA 3 VCCIOB TCK/SK 4 TDI/DO 3 TDO/DI TMS/CS 0 GPIOL0 9 GPIOL GPIOL GPIOL3 GPIOH0 3 GPIOH GPIOH GPIOH3 0 SI/WUA 40 UNUSED0 39 UNUSED 3 UNUSED 3 UNUSED3 3 UNUSED4 3 UNUSED 33 UNUSED 3 UNUSED 30 UNUSED 9 UNUSED9 UNUSED0 UNUSED SI/WUB 4 PWREN# R 0K R 0K 3V3_USB USB_V C 0.uF C4 0uF R 0 R 0 U VIN 3 VOUT_ 4 VOUT_3 Adjust LM3LBD R3 0_% NC_ VOUT_ VOUT_ NC_ SEL0_SCL {,3} SEL_SDA {,3} VDDA_REG VDDA_REG {4} R C 43_% 0uF 0 Integrated Device Technology, Inc. January, 0

16 Figure 4. P49V9 Evaluation Board Schematics Page {3,} {3,} {3} {3} {3} {3} {3} {3} XOUT XIN SEL_SDA SEL0_SCL SD_OE OE_buf f er OEB_0 OEB3, XOUT XIN SEL_SDA SEL0_SCL SD_OE Stand Offs H H H3 H4 VDDD OE_buf f er OEB_0 OEB3, P49V9 CONNECTIONS 30 U P49V9 VDD_CORE 3 VDD 44 VDD VDD3 3 NC NC 40 NC3 NC4 3 XOUT XIN/REF SEL/SDA SEL0/SCL SD/OE OE_BUFFER OEB_0 OEB3, 49 EPAD VDDA 4 VDDO_ VDDO_ VDDO_3 43 VDDO_4 4 VDDO0 4 OUT0_SEL_ICB 39 VDDO 3 OUT 3 OUTB 3 VDDO 3 OUT 34 OUTB VDDO4 OUT4 3 OUT4B 9 OUT3 OUT3B 9 OUT 0 OUTB OUT OUTB 0 OUT OUTB OUT 9 OUTB OUT9 OUT9B 4 OUT0 OUT0B 4 OUT 4 OUTB VDDA VDDO0 VDDO0 OUT0_SELB_IC VDDO VDDO R 0 OUT R 0 OUTB VDDO VDDO R9 0 OUT R30 0 OUTB VDDO4 VDDO4 OUT4 OUT4B OUT3 OUT3B OUT OUTB OUT OUTB OUT OUTB OUT OUTB OUT9 OUT9B OUT0 OUT0B OUT OUTB VDDO_3_- {3} C4 OUT0_SELB_IC OUT0_SELB_IC R9 33 J3 0.uF 3.3V LVPECL TERMINATION C9 OUT J0 0.uF C93 OUTB J9 R0 0_% 0.uF R3 0_% R33 0 C94 OUT J 0.uF C9 OUTB J R0 DNP 0.uF R DNP R3 DNP VDDO0 R _NP R4 4_NP VDDO R09 R0 _NP _NP R R 4_NP 4_NP VDDO R3 R4 _NP _NP R R 4_NP 4_NP Place 33 OHM Resistors Close to Main Device For LP HCSL TERMINATION Place AC Coupling Capacitors Close to SMA Place R & R 33 OHM Resistors Close to Main Device For HCSL TERMINATION R9 & R90 Should be Closer to the SMA LP HCSL TERMINATION C9 OUT3 R34 33 J43 0.uF C99 OUT3B R3 33 J4 0.uF OUT4 OUT4B R 33 R 33.V and 3.3V HCSL TERMINATION R9 DNP R90 DNP C90 0.uF C9 0.uF J4 J3 VDDO4 R3 _NP R4 4_NP R40 _NP R4 4_NP 0 Integrated Device Technology, Inc. January, 0

17 L L 3mm Figure. P49V9 Evaluation Board Schematics Page C3 NP C NP 4 3 X_NP R R9 XIN XIN {} 0_NP X MHz(pf ) 0_NP XOUT XOUT {} VDDD U VCC VEE DIP_SW s s s3 s4 s s s s SD_OE 4 3 R R 0K 0K SEL0_SCL SEL_SDA 0 9 R 0K OUT0_SELB_IC SD_OE {} SEL0_SCL {,3,} SEL_SDA {,3,} LABEL: OE SEL0 SEL OUT0_SELB_IC {} SEL[:0]/IC VDDD J XIN_CONN R 33 R 49.9_NP C uf XIN Unpopulate C when Crystal is used as input reference LD Green R.K R.K R 0 R 0 TP4 TP3 SEL0_SCL SEL_SDA JP SCL_AADVAR SDA_AADVAR 3 9 SEL0_SCL {,3,} SEL_SDA {,3,} AARDVARK 4 0 Header_0Pin Figure. P49V9 Evaluation Board Schematics Page 3 J J VDD_J _J VDD_J C0 0.uF C4 0uF LABEL AS INDICATED FOR 3-PIN HEADERS C 0.uF VDDA_J VDDA_REG JP3 VDDA_REG VDDA_ R3. FB BLMBBSND C 0.uF FB3 BLMBBSND C 0.uF C 0uF C 0uF VDDA C3 0.uF VDDD C 0.uF C 0.uF C 0.uF C 0.uF J C 0.uF VDDO_J C 0.uF C9 0uF LABEL ON EACH RESPECTIVE PIN OF HEADERS:.V,.V, 3.3V TP VDDO_J JP TP TP3 VDDO_J JP4 TP4 VDDO_.V VDDO_.V VDDO_3.3V VDDO_.V VDDO_.V VDDO_3.3V VDDO_0 VDDO_ VDDO_0 C 0.uF VDDO_ FB BLMBBSND C9 0.uF FB4 BLMBBSND C 0uF C30 0uF C 0.uF C3 0.uF VDDO0 VDDO Locate near DUT power pin TP VDDO_J VDDO_.V VDDO_ VDDO_ FB VDDO VDDO_.V BLMBBSND USB_V C3 0.uF C4 0uF U3 3 INPUT OUTPUT_ OUTPUT_ Adjust LM3DCY R 0_% 4 R4 43_% VDDO_.V C3 0uF Tantalum preferred USB_V C3 0.uF C 0uF U4 VIN 3 VOUT_ 4 VOUT_3 Adjust LM3LBD R NC_ VOUT_ VOUT_ NC_ 43_% R 43_% VDDO_.V C3 0uF J4 VDDO_3_-_J JP TP JP VDDO_3.3V VDDO_.V C3 0.uF VDDO_3 FB VDDO_3 BLMBBSND C0 0.uF C33 0uF C9 0uF C34 0.uF VDDO_3_- C 0.uF USB_V C4 0.uF C 0uF U VIN 3 VOUT_ 4 VOUT_3 Adjust LM3LBD NC_ VOUT_ VOUT_ NC_ R 43_% VDDO_3.3V C4 0uF PCB Copper Decal Recommandations for LM3LD SO-.0 oz Copper TP0 VDDO_J JP TP9 VDDO_.V VDDO_.V VDDO_3.3V VDDO_4 FB VDDO_4 BLMBBSND C3 0.uF C 0uF C4 0.uF VDDO4 R9 40_% USB_V USB_V {} VDDA_REG VDDA_REG {} L = mm is more than enough Header Alignment: Single pin header above and below the center pin of 3-pin header so that center pin can be jumped with the surrounding 4 pins, as shown at left. 0 Integrated Device Technology, Inc. January, 0

18 9 Figure. P49V9 Evaluation Board Schematics Page 4 C4 0nF {4} USB_V TP L 300ohm A R R0 0 L 00 ohm 00mA C4 0.uF C49 0.uF TP C9 4uF 00 J VBUS D- 3 D+ 4 USB PORT L3 300ohm A R3 C9 C9 R C4 33pF 0uF 0.uF R4.K C Y MHz 33pF XTIN LD Green VCC3_3V 3V3_USB C 0.04uF R0 0K XTOUT VCC3 VCC3 C0 0uF R 40 C 3V3_USB 0.uF U 3V3OUT USBDM USBDP RSTOUT# 43 XTIN 44 XTOUT 4 RESET# 4 EECS EESK EEDATA 4 TEST f t3_chip 4 AVCC 4 A VCC 3 VCC VCCIOA 3 VCCIOB TCK/SK 4 TDI/DO 3 TDO/DI TMS/CS 0 GPIOL0 9 GPIOL GPIOL GPIOL3 GPIOH0 3 GPIOH GPIOH GPIOH3 0 SI/WUA 40 UNUSED0 39 UNUSED 3 UNUSED 3 UNUSED3 3 UNUSED4 3 UNUSED 33 UNUSED 3 UNUSED 30 UNUSED 9 UNUSED9 UNUSED0 UNUSED SI/WUB 4 PWREN# R 0K R 0K 3V3_USB USB_V C 0.uF C 0uF R 0 R 0 U VIN 3 VOUT_ 4 VOUT_3 Adjust LM3LBD R3 0_% NC_ VOUT_ VOUT_ NC_ SEL0_SCL {,3} SEL_SDA {,3} VDDA_REG VDDA_REG {4} R C 43_% 0uF 0 Integrated Device Technology, Inc. January, 0

19 . Signal Termination Options Termination options for OUTPUT 4 for the P49V9/ Evaluation Board are shown in Figure. The termination circuits are designed to optionally terminate the output clocks in LVPECL, LVDS, LVCMOS and HCSL signal types by populating (or not-populating) some resistors. DC or AC coupling of these outputs is also supported. Table 4 through Table 9 define the components that must be installed to support LVPECL, HCSL, LVCMOS and LVDS signal types for OUTPUT 4 on the P49V9/ EVB. Note that with the specified components the output signals should be measured and terminated by test equipment with a 0Ω internal termination. Figure. P49V9/ Output Termination Options LVPECL TERMINATION OUT C J0 LVDS TERMINATION OUTB R0 0_% R 0_% R3 0 0.uF C 0.uF J9 OUT OUTB C 0.uF C9 0.uF J J HCSL TERMINATION OUT4 R 33 C J4 0.uF LP HCSL TERMINATION = LVCMOS TERMINATION OUT4B R 33 C J3 OUT R9 33 C J30 0.uF 0.uF R9 DNP R90 DNP OUTB R9 33 C3 J9 0.uF 0 Integrated Device Technology, Inc. 9 January, 0

20 . Termination Options for the P49V9 Board Note: In the tables in this section, the components given for the HCSL termination scheme are the default configuration of the Evaluation Board. This scheme allows quick measurements of every logic type without modification of the Evaluation Board. When using the unmodified board with equipment with AC coupled inputs, such as a spectrum analyzer or phase noise test set, use a 3dB or db attenuator to facilitate a DC path to ground to allow the output driver to toggle. This is only needed with LVPECL and HCSL logic. Table. P49V9 Termination Options for OUTPUT Signal Type Series Resistors: R0, R09 0 Pull-Down: R0, R, R3 Series Capacitor: C, C LVPECL 0Ω Installed (see Figure ) 0.µF HCSL 33 Not installed 0 (short) LVCMOS 33 Not installed 0.µF LVDS 0 Not installed 0.µF Table. P49V9 Termination Options for OUTPUT Signal Type Series Resistors: R0, R 0 Pull-Down: R, R, R3 Series Capacitor: C, C9 LVPECL 0Ω Installed (see Figure ) 0.µF HCSL 33 Not installed 0 (short) LVCMOS 33 Not installed 0.µF LVDS 0 Not installed 0.µF Table. P49V9 Termination Options for OUTPUT4 Signal Type Series Resistors: R, R 0 Pull-Down: R9, R90 Series Capacitor: C, C LVPECL 0 Ω Installed (see Figure ) 0.µF HCSL 33 Not installed 0 (short) LVCMOS 33 Not installed 0.µF LVDS 0 Not installed 0.µF 0 Integrated Device Technology, Inc. 0 January, 0

21 . Termination Options for the P49V9 Board Note: In the tables in this section, the components given for the HCSL termination scheme are the default configuration of the Evaluation Board. This scheme allows quick measurements of every logic type without modification of the Evaluation Board. When using the unmodified board with equipment with AC coupled inputs, such as a spectrum analyzer or phase noise test set, use a 3dB or db attenuator to facilitate a DC path to ground to allow the output driver to toggle. This is only needed with LVPECL and HCSL logic. Table. P49V9 Termination Options for OUTPUT Signal Type Series Resistors: R, R 0 Pull-Down: R0, R3, R33 Series Capacitor: C9, C93 LVPECL 0 Ω Installed (see Figure ) 0.µF HCSL 33 Not installed 0 (short) LVCMOS 33 Not installed 0.µF LVDS 0 Not installed 0.µF Table 9. P49V9 Termination Options for OUTPUT Signal Type Series Resistors: R9, R30 0 Pull-Down: R0, R, R3 Series Capacitor: C94, C9 LVPECL 0 Ω Installed (see Figure ) 0.µF HCSL 33 Not installed 0 (short) LVCMOS 33 Not installed 0.µF LVDS 0 Not installed 0.µF Table 0. P49V9 Termination Options for OUTPUT4 Signal Type Series Resistors: R, R 0 Pull-Down: R9, R90 Series Capacitor: C90, C9 LVPECL 0 Ω Installed (see Figure ) 0.µF HCSL 33 Not installed 0 (short) LVCMOS 33 Not installed 0.µF LVDS 0 Not installed 0.µF 0 Integrated Device Technology, Inc. January, 0

22 . Ordering Information Orderable Part Number P49V9-EVK P49V9-EVK Description P49V9 Evaluation Board; A-male to B-male USB cable. P49V9 Evaluation Board; A-male to B-male USB cable. 3. Revision History Revision Date January, 0 Initial release. Description of Change Corporate Headquarters 04 Silver Creek Valley Road San Jose, CA 93 Sales or Fax: Tech Support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as IDT ) reserve the ri ght to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are d etermined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of a ny kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit All contents of this document are copyright of Integrated Device Technology, Inc. All rights reserved. 0 Integrated Device Technology, Inc. January, 0