CY3685 EZ-USB NX2LP Development Kit User s Guide Rev 1.2

Transcription

1 CY EZ-USB NXLP Development Kit User s Guide Rev. Cypress Semiconductor Personal Communication Division 0 North First Street San Jose, CA (0) -00

2 Cypress Disclaimer Agreement The information in this document is subject to change without notice and should not be construed as a commitment by Cypress Semiconductor Corporation Incorporated. While reasonable precautions have been taken, Cypress Semiconductor Corporation assumes no responsibility for any errors that may appear in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Cypress Semiconductor Corporation. Cypress Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Cypress Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Cypress Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Cypress Semiconductor and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Cypress Semiconductor was negligent regarding the design or manufacture of the part. The acceptance of this document will be construed as an acceptance of the foregoing conditions. CY EZ-USB NXLP Development Kit User s Guide, Version.. Copyright 00, Cypress Semiconductor Corporation. All rights reserved.

3 Table of Contents NXLP Development Kit Overview Introduction Development Kit Contents Development Kit Requirements Hardware Features Development Board Features Development Board Layout Hardware Configuration Technical Support i

4 ii Table of Contents

5 CY EZ-USB NXLP Development Kit User s Guide.0 NXLP Development Kit Overview. Introduction The CY EZ-USB NXLP Development Kit is a complete design environment for use in NAND flash-based systems. The combination of hardware and programming utility software provide the designer with complete development and manufacturing support. This development kit is designed to allow scalable testing and evaluation of the Cypress EZ-USB NXLP NAND Flash Controller device (CYC0 and CYC0) with different NAND flash devices. The hardware platform is designed to support between - single-device NAND flash chips, or - dual-device NAND flash chips for scalable density testing. Additionally, Cypress has created a device Programming Utility to assist in the manufacturing environment. This programming utility allows easy NAND flash configuration during the design and manufacturing process. Figure -. (CYC0 and CYC0) NAND Flash Controller Development Platform Development Board Page -

6 CY EZ-USB NXLP Development Kit User s Guide. Development Kit Contents The CY Development Kit should contain the following items: Hardware: Hardware Development Platform (with no sockets populated with NAND flash devices) USB Cable CD-ROM Paper copies of the following documents: Cover Letter CY EZ-USB NXLP Development Kit User s Guide (this manual) EZ-USB NXLP Programming Utility Installation Guide CD-ROM with complete contents of all design materials including: PDFs of all documents above CYC0/CYC0 Datasheet Hardware files Schematics, Bill of Materials, OrCAD files Installation files for the EZ-USB NXLP Programming Utility. Development Kit Requirements The Development Kit supports Windows SE, Windows ME, Windows 000 and Windows XP. The recommended environment is: Windows XP USB.0 Host Controller For Windows SE and Windows ME support, please follow installation instructions in the enclosed EZ-USB NXLP NAND Programming Utility Installation Instructions. The Cypress EZ-USB NXLP Programming Utility software is designed to run on the Windows operating system. It will not run on Mac OS. The Cypress EZ-USB NXLP development board and the EZ-USB NXLP NAND Flash Controller, however, will operate in a Mac environment if the NAND flash is pre-configured and the Mac OS supports USB mass storage devices. Page - CY EZ-USB NXLP Development Kit User s Guide Rev.

7 .0 Hardware Features. Development Board Features The EZ-USB NXLP Development kit hardware supports the following NAND flash features: - single-device or - dual-device NAND flash chips with X organization -byte per page (BPP) or,0 (K) BPP NAND flash devices BPP supports Mbit to Gbit NAND flash devices K BPP supports Gbit to Gbit NAND flash devices Jumper options for flexible testing and configuration Pin headers for easy debug and signal analysis -pin TSOP NAND flash package support Write-protect switch Dual-LED operation and power control feature Download-over-USB for device programming. Development Board Layout The CY EZ-USB NXLP Development kit comes with all the hardware design files necessary to fully evaluate and customize the Cypress development board for your design; these files are available on the CD-ROM contained in this kit. Please refer to the development board schematics. Development Board Page -

8 CY EZ-USB NXLP Development Kit User s Guide Jumper and Switch Configurations Jumper/Switch Location Jumper default configuration and functionality is discussed below in the Hardware Configuration section. Header Configurations Jumper/Switch Descriptions Default Jumper Install Connection J Power on/off to EZ-USB NXLP On - J Power on/off for all NAND flash devices On - J LED enable/disable On - NAND flash activity indicator J LED D enable/disable (Spare) On - J U enable/disable control On - J U enable/disable control On - J U enable/disable control On - J0 U enable/disable control On - J U enable/disable control On - J U0 enable/disable control On - J U enable/disable control On - J U enable/disable control On - J SW IC enable/disable control. Note: For the next revision of the NXLP chips, jumper J and IC U should be disabled (removed). Write-protect Switch ON Write-protect Switch OFF On - See label on Board This design contains six logic analyzer headers. The functionality of these headers is described below. Please refer to the EZ-USB NXLP Datasheet for more specific chip pin descriptions and functionality. Header Label Header Pin Pin Name EZ-USB NXLP Signal P NC No connect VCC_..V Power NC No connect nxce Chip enable # nxce Chip enable # nxce Chip enable # nxce Chip enable # nxce Chip enable # nxce Chip enable # 0 nxce Chip enable # Page - CY EZ-USB NXLP Development Kit User s Guide Rev.

9 nxce0 Chip enable #0 Data D Data D Data D Data D Data D Data D Data D0 Data 0 0 GND Ground P NC No connect VCC_..V Power NC No connect R_nB Ready/Busy R_nB Ready/Busy NC No connect NC No connect NC No connect nx Read enable 0 nx0 Read enable 0 nxwe Write enable NC No connect NC No connect n_sw Write-protect switch input n_nf Write-protect NAND flash nled Chip active LED sink nled Data activity LED sink Address latch enable Command latch enable 0 GND Ground P Unused header P Unused header P Unused header P Unused header Development Board Page -

10 CY EZ-USB NXLP Development Kit User s Guide NXLP.v Power LEDs NAND Flash chip jumpers for enable/disable Write-Protect Switch NAND Flash Chips Power Figure -. Key Component Locations. Hardware Configuration This section describes how to properly configure the EZ-USB NXLP Development board. Sockets are provided on the NXLP Development Board for development convenience in testing a variety of NAND flash parts. Because of the many different NAND types available on the market, it is important to configure the EZ-USB NXLP Development Board properly to ensure correct operation. The following table provides four simple questions that will assist in understanding how to configure your board: Note: All NAND configuration changes should be performed while DISCONNECTED from the USB bus. Page - CY EZ-USB NXLP Development Kit User s Guide Rev.

11 Table. NAND Flash Parameters Question Q: NAND flash vendor? Q: NAND flash part number? Q: Single- or dual-device part? (Note: Single-device parts have one CE pin, dual-device parts have two CE pins.) Q: Total NAND flash devices (- for singledevice or - for dual-device)? Response Step : Inserting NAND Devices into Sockets (U-U) The NXLP DVK supports up to single-device or dual-device NAND flash chips. The same part type (vendor, part number) must be loaded in the NXLP DVK board for it to function correctly. Do not mismatch NAND flash devices as it could lead to data corruption. Warning: The NAND flash sockets are rated by their manufacturer for 0 insertions and can be damaged by careless handling. However, with care, more insertions are possible. Please use caution when inserting or removing NAND flash devices from the sockets. Be certain to install the parts so pin is in the upper left corner. Pin is clearly marked on the EZ-USB NXLP DVK Board with a triangle at each socket. Depending on the response to Question # above, follow the directions below: Single-Device Parts - one CE pin Install the NAND flash devices in the following order until you reach the total listed in response to Q: U, U, U, U, U, U0, U, U Dual-Device Parts - two CE pins Install the NAND flash devices in the following order until you reach the total listed in response to Q: U, U, U, U Step : Configure NAND Flash Jumpers J-J It is possible to enable or disable individual NAND flash chips using jumpers J-J. The EZ- USB NXLP device detects NAND flash in the following order: For single-device parts: U, U, U, U, U, U0, U, U For dual-device parts: U, U, U, U For example, for single-device parts, if U is disabled by shunting pins - of jumper J (see Table below) then U and the parts after it (U, U, U0, U, and U) will not be detected by the NXLP at power-on. Development Board Page -

12 CY EZ-USB NXLP Development Kit User s Guide By default J-J should be shunted across pins -. The following tables show how to enable or disable NAND flash devices by configuring J-J. This is preferable to removing NAND flash devices and extends socket life. Single-Device Parts Individual NAND flash devices can be enabled and disabled as shown below: Table. Single-Device Parts Configuration of J-J Jumper Settings Shunt - Shunt - J Disable U Enable U J Disable U Enable U J Disable U Enable U J0 Disable U Enable U J Disable U Enable U J Disable U0 Enable U0 J Disable U Enable U J Disable U Enable U Dual-Device Parts For dual-die NAND flash devices the jumpers must be enabled or disabled in pairs as shown below: Table. Dual-Device Parts Configuration of J-J Jumper Settings Shunt - Shunt - J and J Disable U Enable U J and J0 Disable U Enable U J and J Disable U Enable U J and J Disable U Enable U Page - CY EZ-USB NXLP Development Kit User s Guide Rev.

13 Step : Device Programming and Configuration Provided the guidelines above have been followed, your EZ-USB NXLP development kit should now be properly configured. The next step is to plug the DVK into the USB port on your target PC and to write the configuration data with the EZ-USB NXLP Programmer Utility. Please follow the installation guidelines provided in the enclosed EZ-USB NXLP Programming Utility Installation instructions.. Technical Support For feedback or technical support regarding Cypress EZ-USB NXLP products, please contact Cypress at >Technical Support >Create a Case. Development Board Page -

14 CY EZ-USB NXLP Development Kit User s Guide VCC_. VCC_NXLP NAND Flash PIN HDR 0. ufd 0. ufd 0. ufd 0. ufd 0. ufd 0. ufd 0. ufd 0. ufd 0 ufd v U- are for single- or U- are for single-die dual-die NAND Flash devices. NAND Flash devices only. J U U R_nB R_nB NC NC VCC_. VCC_NF NC NC NC NC NC NC PIN HDR NC NC J NC NC NC NC R_nB NC I/O D NC I/O D C R_nB R/B I/O D R_nB R/B I/O D 0 ufd v n0 R/B I/O D n R/B I/O D D 0 D PIN HDR nce0 I/O nce I/O VCC_. VCC_. nce CE NC 0 CE NC 0 0 VCC_NF CE NC 0 VCC_NF VCC_NF CE NC VCC_NF P P VCC VCC C C VCC VCC SW LED VSS VSS D C VSS VSS VCC_. NC0 C Switch Indicators 0. ufd 0. ufd NC ufd 0. ufd P D D HW Power-On / VCC_. nwe0 I/O LED Green LED Green D nwe I/O D +V CLK nxce USB Suspend n_nf WE I/O D n_nf WE I/O D nxce CLK D nxce I/O 0 0 J D0 I/O D0 nxce D D 0 nxce VCC_. R 0 C PIN HDR R nxce D D nxce n_nf 0 NC0 NC0 nxce0 D0 D 0 00 R 0 NC NC 0. ufd D D D NC NC NC NC 00K D D D SW D nled NC NC NC NC R D D D D n_sw nled D0 D D TSOP SOCKET TSOP SOCKET D0 GND 0 NO LOAD LOGIC ANALYZER HDR SPDT VCC_. P J PIN HDR U U +V CLK R_nB R_nB CLK D C NC NC D D NC NC NC NC nx D D 00 nx0 0. ufd NC NC NC NC nxwe D0 D 0 NC NC NC NC NC NC D n_sw R_nB NC I/O D NC I/O D n_nf D D nled R_nB R/B I/O D R_nB R/B I/O D nled D D n0 R/B I/O D n R/B I/O D D D VCC_V VCC_NXLP VCC_. VCC_. nce I/O nce I/O D0 GND 0 nce CE NC 0 CE NC 0 0 LOGIC ANALYZER HDR VCC_NF CE NC 0 VCC_NF VCC_NF CE NC VCC_NF P P VCC_. VCC VCC C C VCC VCC VSS VSS P C R R R R R0 C VSS VSS C 00 NC0 C ufd 0. ufd NC0 +V CLK ufd 0. ufd CLK D D D D D nwe0 I/O C D nwe I/O D D D R_nB n_nf WE I/O D n_nf WE I/O D D0 D 0 0 C R_B# R_nB nwe0 I/O R0 zero D0 I/O 0 D0 D 00 0 nxwe R zero nwe 0 0. ufd 0 ufd v R_B# D D 0 WE# nx0 n0 NC0 NC0 R zero D D AVCC 0# 0 nx n NC NC R zero D D AVCC # NC NC NC NC D0 GND 0 J nset NC NC NC NC LOGIC ANALYZER HDR SET# VBUS TSOP SOCKET TSOP SOCKET DM DM DP DMINUS D0 VCC_. DP DPLUS DD0 D GND U J DD D VCC_. S DD 0 D nce0 P S DD D nxce0 USB B RA R DD D U U0 NC +V CLK CYC0-LFXC DD D PIN HDR VCC_. CLK D DD NC zero J NC D D C D NC NC NC NC D D nce NC NC 0 C NC NC D0 D XTALOUT nled nxce NC NC NC NC 00 D pfd LED# nled R_nB NC I/O 0. ufd Y D NC I/O D D D LED# n_nf PIN HDR VCC_. R_nB R/B I/O D R_nB R/B I/O D D D _NF# n_sw n0 R/B I/O D n D D D J R/B I/O C nce I/O 0 MHz _SW# nce I/O D0 GND nce nce CE NC 0 CE NC 0 0 LOGIC ANALYZER HDR XTALIN nxce0 nxce VCC_NF CE NC 0 VCC_NF VCC_NF CE NC VCC_NF pfd CE0# nxce P P VCC_. CE# nxce VCC_. C VCC VCC PIN HDR C VCC VCC CE# nxce J0 VSS VSS C VSS VSS C CE# nxce 0. ufd NC0 0. ufd NC0 00 nxce nce 00 CE# 0. ufd 0. ufd R CE# 0 nxce nxce D D VCC_. CE# nxce nwe0 I/O D nwe I/O D 00K B CE# n_nf D n_nf D B PIN HDR VCC_. WE I/O P WE I/O 0 J I/O 0 D0 I/O 0 D0 NC +V CLK 0 CLK D nce NC0 NC0 D D nxce NC NC D D NC NC 0 C NC NC D0 D PIN HDR VCC_. NC NC D 00 NC NC 0. ufd J D D TSOP SOCKET TSOP SOCKET D D nce D D nxce D0 GND 0 LOGIC ANALYZER HDR PIN HDR VCC_. J U U VCC_. VCC_. VCC_. P nce NC NC nxce NC NC NC NC +V CLK NC NC NC NC CLK D VCC_. C PIN HDR VCC_. NC NC NC NC D D R R R J R_nB NC I/O D NC I/O D D D SDA 00 U R_nB D R_nB R/B I/O 0 C R/B I/O D SCL D0 D 0. ufd nce n0 R/B I/O D n R/B I/O D D 00.K.K 0K A0 Vcc nxce nce nce I/O D D 0. ufd I/O A 0 0 SCL nce CE NC CE NC D D A SCL 0 0 SDA PIN HDR VCC_NF CE NC VCC_NF VCC_NF CE NC VCC_NF D D Vss SDA P P D0 GND 0 VCC VCC LC-I/P C0 VCC VCC C VSS VSS LOGIC ANALYZER HDR VSS VSS C NC0 C ufd NC ufd 00 J 0. ufd ufd EEPROM D D nwe0 I/O D nwe I/O D n_nf WE I/O D n_nf WE I/O 0 0 D VCC_. I/O D0 I/O 0 0 D0 Reset NC0 NC0 Alternate Reset NC NC Voltage Regulation A VCC_V VCC_. NC NC NC NC A U R VCC_. NO LOAD ALL NC NC NC NC U COMPONENTS VIN VOUT TSOP SOCKET TSOP SOCKET 0K C C0 EN SR ufd v 0. ufd WDI nset R D SET TP Note: All NAND flash devices must be TPS MR 00K DIODE MAJ TP-R identical (i.e. same vendor, part VCC_V VCC_. C0 nset number, capacity, package, etc). TPS0-DVT CYPSS SEMICONDUCTOR ufd ms Reset C Title This board supports eight () NXLP Development Kit Board ufd single-die devices or four () dual-die NAND flash devices. Size Document Number Rev TP TP PCB: PDC- C F-0 *B TP-R TP-R PCA: -xx Date: Thursday, December 0, 00 Sheet of 00 NC NC NC NC SCL SDA PLACE ONE CAP PER EACH VCC PIN ON U C C C C C C SMINIP 00 NO LOAD 00 J C 00 NO LOAD 00 GND VDD C.K NO LOAD AGND AGND GND GND GND GND GND GND GN TAB NC NC NC NC VCC VCC VCC VCC VCC VCC SERVED SERVED SERVED K 00 C GND 00 Figure -. NXLP DVK Schematic Page -0 CY EZ-USB NXLP Development Kit User s Guide Rev.