STEVAL-IME011V1 evaluation board based on the STHV748 ultrasound pulser

Transcription

1 UM1957 User manual STEVAL-IME011V1 evaluation board based on the STHV748 ultrasound pulser Introduction The STEVAL-IME011V1 is an evaluation board designed around the STHV748 ultrasound pulser IC, a state of the art product in ultrasound imaging applications. The system drives four transducers as 4- channel transmitters, and can output waveforms directly to an oscilloscope by connecting the scope probe on the relative BNCs. Four preset waveforms are available to test the HV pulser under different conditions. Figure 1: STEVAL-IME011V1 evaluation board November 2015 DocID Rev 1 1/28

2 Contents UM1957 Contents 1 Board features Getting starting Hardware layout and configuration Power supply MCU Stored patterns STHV748 stage Operating supply conditions Connectors Power supply MCU Schematic PCB layout Revision history /28 DocID Rev 1

3 UM1957 Board features 1 Board features Suitable for ultrasound imaging applications 4 monolithic channels, 5 level high voltage pulser Integrated T/R switch On-board equivalent piezoelectric load implemented through an R/C equivalent network USB interface available for uploading customized output waveforms Embedded Microcontroller Flash memory available for storing customized waveforms High voltage screw connectors to power the STHV748 Automatic lockout overvoltage protection 7 LEDs to signal EVAL BOARD status and proper operation Human Machine Interface to select, start and stop the stored output waveforms DocID Rev 1 3/28

4 Getting starting UM Getting starting The STEVAL-IME011V1 is shipped by STMicroelectronics ready to use. The user only needs to: 1. Plug the right power supply to the board (see Section 1: "Board features" for further details) 2. Connect the BNC to the oscilloscope 3. Check that LED PROGRAM 1 (LD1) turns on 4. Select the waveform with the PROGRAM button. The corresponding PROGRAM LED (LD1-LD4) turns on 5. Press the START button to run the selected program; the START LED L5 turns on. When the program ends, the microcontroller returns to the IDLE state (LED L5 off) 6. If a continuous wave program is selected, the STOP button must be pressed to stop program execution. The microcontroller returns to the IDLE state and the STOP led (L5) turns off 7. To run the same program again, restart from step 5. To run another program, restart from step 4 8. An overvoltage protection mechanism suspends pattern generation if the HV supply exceeds 90 V and the red L6 LED switches on. Pattern generation will restart once the HV supply voltage falls back into the allowed range. 4/28 DocID Rev 1

5 UM1957 Hardware layout and configuration 3 Hardware layout and configuration The STEVAL-IME011V1 evaluation board is designed around the STHV748. The hardware block diagram below illustrates the main connection between STHV748 and the STM32F4. Figure 3: "STEVAL-IME003V1 board layout" will help you to locate connectors, LEDs and features on the board. Figure 2: Hardware block diagram Figure 3: STEVAL-IME003V1 board layout 3.1 Power supply The low voltage block of the STEVAL-IME011V1 board is designed to be powered: during programming and when the board is connected to the PC: 5V DC through USB Mini B connector to supply the STM32F4 During pattern generation and when high voltage is powered on: 5V DC connected to VDD to supply STM32F4 and STHV748 through an LDO -5V DC connected to VSS to supply STHV748 through an LDO DocID Rev 1 5/28

6 Hardware layout and configuration the USB link must be removed when high voltage is connected to the board UM1957 The high voltage block of the STEVAL-IME011V1 is designed to be powered: VDD: Positive supply voltage, 5 V (2 - VDD conn.) GND: Ground (1 VDD conn. And 2 VSS conn) VSS: Negative supply voltage 5 V (1 - VSS conn.) GND: Ground (1 HVP0 conn.) HVP0: TX0 High voltage positive supply (2 - HVP0 conn.) GND: Ground (1 HVP1 conn.) HVP1: TX1 High voltage positive supply (2 - HVP1 conn.) HVM1: TX1 high voltage negative supply (1 - HVM1 conn.) GND: Ground (2 - HVM1 conn.) HVM0: TX0 high voltage negative supply (1 - HVM0 conn.) GND: Ground (2 HVM0 conn.) Figure 4: STEVAL-IME011V1 board connections 3.2 MCU The STM32F427 is fully dedicated to generating the bitstream on its GPIO pins to drive the pulser s output channels. It is already pre-programmed as a DFU (device firmware upgrade) device with the ability to upgrade internal FLASH memory. The STM32F427 manages all the DFU operations, such as the authentication of product identifier, vendor identifier and Firmware version. The MCU drives the pulser channels through the use of different General Purpose IO (GPIO) pins. You can simulataneously drive from 1 to 16 different pins by simply writing a 16-bit word into the GPIO Output Data Register (ODR). The board can be connected to a PC via USB. The required pattern is sent as a sequence of states for each pulser channel and of durations for each state. Here, all durations are expressed in units of MCU system clock cycles. Once the information is received, the channel states are converted into 16-bit words for the GPIO peripheral and they are stored in the embedded Flash, together with the timing information. After programming, the PC is 6/28 DocID Rev 1

7 UM1957 Hardware layout and configuration no longer required, so the board can act as a stand-alone device. Different patterns can be stored and the user can select which one to use at run-time. The same MCU can implement two different solutions for real-time execution. The first solution involves the use of the STM32 Direct Memory Access (DMA) peripheral. The DMA is able to transfer data from memory to any peripheral register, GPIO included, without the intervention of the MCU core. To trigger DMA transfer, a general purpose TIMER is used. The timer works at the system clock frequency and basically acts as a counter and the reload value (the value at which the counter returns to zero) is stored in the Auto Reload Register (ARR). The timer triggers two different DMA channels in two different moments: the first channel is triggered at each reload event and transfers the new GPIO word into the ODR; the second is triggered at a constant time after reload and transfers the new duration information into the ARR The timer preload feature is enabled, so that the new ARR value is effective only at the next reload. Since the time needed by the first DMA channel to update the ODR is a constant, considering the reload trigger as the starting point, the time between two different GPIO updates is simply given by the ARR value. The Circular buffer feature of the DMA can be enabled to allow the automatic regeneration of the same pattern at each end. This solution has the advantage of being fully managed by hardware. The MCU core is completely free for any user requirement. The main drawback is that each timing value between two subsequent states cannot be lower than a minimum value in order to guarantee enough time for both DMA channels to perform their transfers. Figure 5: Solution 1 The second solution is designed to overcome the minimum duration requirement of the DMA solution and involves the MCU core directly. During run-time, the core generates the binary assembly code it needs to load and store each word in the ODR. Any unnecessary instructions like control loops are avoided; the code is only a succession of simple load/store instructions. To adapt the timing to the pattern needs, dummy instructions are inserted in the assembly code. To avoid wasting time to load each word from memory, the word is inserted as a literal in the assembly instruction itself, which means that a 32-bit instruction is needed instead of a 16-bit equivalent. DocID Rev 1 7/28

8 Hardware layout and configuration UM1957 In order to avoid any latency due to the instruction fetch from Flash, the code is executed from the embedded RAM. Moreover, the RAM is configured to be accessed by the core through a different bus to the one used to access the ODR. Thanks to all these solutions, it is possible to achieve a minimum time of two system clock cycles before two updates and maintain a one system clock cycle resolution. For instance, if you consider a STM32F4 clocked at 168 MHz, the minimum timing you can achieve is 12 ns and you can set the duration of each state with a resolution of 6 ns. For a repetitive pattern, a branch instruction is added at the end of the routine to restart the pattern generation. In this case, the clock cycles needed for the branch instruction has to be considered for the last state. The main drawback of this solution is that the MCU core is 100% involved in the pattern generation even though it can still be called by peripheral interrupts and stop pattern generation to perform other tasks. Figure 6: Solution Stored patterns The STEVAL-IME011V1 can memorize four patterns in the MCU FLASH memory in order to demonstrate the achievable performance at the pulser outputs. Four selectable patterns already stored into STM32 flash memory form the default set which is available and ready to use. A detailed description of the programs is listed below. Programmed waveform description, flagged by LED L1 to L4. Program 1 (see Figure 7: "Scheme of program 1 ") XDCR_A: Pulse Wave mode, TX0 switching, 5 pulses, time-period TP=400ns and PRF=150µs XDCR_B: Pulse Wave mode, TX0 switching, 5 pulses in counter phase respect to XDCR_A, time-period TP=400ns and PRF=150µs XDCR_C: Pulse Wave mode, TX1 switching, 5 pulses, time-period TP=200ns and PRF=150µs XDCR_D: Pulse Wave mode, TX1 switching, 5 pulses in counter phase respect to XDCR_C, time-period TP=200ns and PRF=150µs 8/28 DocID Rev 1

9 UM1957 Hardware layout and configuration TX0 means H-Bridge supplied by HVP/M0, while TX1 means H-Bridge supplied by HVP/M1. Figure 7: Scheme of program 1 DocID Rev 1 9/28

10 Hardware layout and configuration UM1957 Mode Table 1: Program "1" PW 5pulses - HV0/1=±60 V; LOAD: 270 pf//100 Ω Frequenc y (MHz) Number of pulses Initial pulse H-bridge PRF Ch A PW positive TX0 150 µs Ch B PW negative TX0 150 µs Ch C PW 5 5 positive TX1 150 µs Ch D PW 5 5 negative TX1 150 µs Figure 8: Acquisition by Program 1 Program "2" (see Figure 9: "Scheme of program 2 ") XDCR_A: Pulse Wave mode, TX0 switching, 5 pulses, time-period TP=200ns and PRF=150 µs XDCR_B: Pulse Wave mode, TX0 switching, 5 pulses in counter phase respect to XDCR_A, time-period TP=200ns and PRF=150 µs XDCR_C: Pulse Wave mode, TX1 switching, 5 pulses, time-period TP=100ns and PRF=150 µs XDCR_D: Pulse Wave mode, TX1 switching, 5 pulses in counter phase respect to XDCR_C, time-period TP=100ns and PRF=150 µs 10/28 DocID Rev 1

11 UM1957 Figure 9: Scheme of program 2 Hardware layout and configuration DocID Rev 1 11/28

12 Hardware layout and configuration UM1957 Mode Table 2: Program "2" PW TX0&TX1 5pulses - HV0/1=±60 V; LOAD: 270 pf//100 Ω Frequenc y (MHz) Number of pulses Initial pulse H-bridge PRF Ch A PW 5 5 positive TX0 & TX1 150 µs Ch B PW 5 5 negative TX0 & TX1 150 µs Ch C PW 10 5 positive TX0 & TX1 150 µs Ch D PW 10 5 negative TX0 & TX1 150 µs Figure 10: Acquisition by Program 2 Program "3" (see Figure 11: "Scheme of program 3 ") XDCR_A: Continuous Wave mode, TX-CW switching, time-period TP=400 ns XDCR_B: Continuous Wave mode, TX-CW switching in counter-phase respect to XDCR_A, time-period TP=400 ns XDCR_C: Continuous Wave mode, TX-CW switching, time-period TP=200 ns XDCR_D: Continuous Wave mode, TX-CW switching in counter-phase respect to XDCR_C, time-period TP=200 ns 12/28 DocID Rev 1

13 UM1957 Figure 11: Scheme of program 3 Hardware layout and configuration DocID Rev 1 13/28

14 Hardware layout and configuration Table 3: Program "3" Continuous Wave - HV1=±10V; LOAD: 270 pf//100 Ω mode Ch A CW 2.5 Ch B CW 2.5 Ch C CW 5 Ch D CW 5 Frequency (MHz) Number of pulses continuous wave continuous wave continuous wave continuous wave Initial pulse positive negative positive negative UM1957 H-Bridge TX-CW TX-CW TX-CW TX-CW Figure 12: Acquisition by Program 3 Program 4 (see Figure 13: "Scheme of program "4"") XDCR_A: Pulse Wave mode, TX0 switching, 1.5 pulses, time-period TP=400 ns and consequently TX1 switching, 5 pulses, time-period=200 ns and PRF=150 µs XDCR_B: Pulse Wave mode, TX0 switching, 1.5 pulses, time-period TP=400 ns and consequently TX1 switching, 5 pulses, time-period=200 ns and PRF=150 µs XDCR_C: Pulse Wave mode, TX0 switching, 1.5 pulses, time-period TP=200 ns and consequently TX1 switching, 5 pulses, time-period=200 ns and PRF=150 µs XDCR_D: Pulse Wave mode, TX0 switching, 1.5 pulses, time-period TP=200 ns and consequently TX1 switching, 5 pulses, time-period=200 ns and PRF=150 µs 14/28 DocID Rev 1

15 UM1957 Figure 13: Scheme of program "4" Hardware layout and configuration DocID Rev 1 15/28

16 Hardware layout and configuration UM1957 Mode Table 4: Program "4" Pulse Cancellation - HV0/1=±60 V; LOAD: 270 pf//100 Ω Frequency (MHz) Ch A PW Ch B PW Ch C PW 5 Ch D PW 5 Number of pulses 3 half pulse then 4 pulse 3 half pulse then 4 pulse 3 half pulse then 4 pulse 3 half pulse then 4 pulse Initial pulse H-bridge PRF positive negative positive negative TX0 then TX1 TX0 then TX1 TX0 then TX1 TX0 then TX1 150 µs 150 µs 150 µs 150 µs Figure 14: Acquisition by Program 4 The board can be connected to a PC via USB cable and patterns can be edited by means of a user interface. the USB link must be removed when a high voltage is connected to the board 3.4 STHV748 stage The STHV748 high-voltage, high-speed ultrasound pulser IC features four independent channels. It is designed for medical ultrasound applications, but can also be used for other piezoelectric, capacitive, or MEMS transducers. The device contains a controller logic interface circuit, level translators, MOSFET gate drivers, noise blocking diodes, and highpower P-channel and N-channel MOSFETs as output stages for each channel. There is also clamping-to-ground circuitry, anti-leakage, an anti-memory effect block, a thermal sensor, and a HV receiver switch (HVR_SW), which guarantees strong decoupling during the transmission phase. Moreover, the STHV748 includes self-biasing and thermal 16/28 DocID Rev 1

17 UM1957 Hardware layout and configuration shutdown blocks (see Figure 15: "STHV748 single channel block diagram"). Each channel can support up to five active output levels with two half bridges. The output stage of each channel is able to provide a ±2 A peak output current. In order to reduce power dissipation during continuous wave mode, the peak current is limited to 0.6 A (a dedicated half bridge is used). For further information, please refer to the STHV748 datasheet. Figure 15: STHV748 single channel block diagram The STHV748 output waveforms can be displayed directly for each channel Ch A/B/C/D using an oscilloscope by connecting the scope probe to the XDCRA, XDCRB, XDCRC, and XDCRD SMB connectors. Moreover, the pulser outputs are connected to the onboard equivalent load, a 270 pf 200 V capacitor paralleled with a 100 Ω, 2 W resistor. A coaxial cable can also be used to easily connect the user transducer; in this case, the equivalent load should be removed from the board. Furthermore, four low voltage outputs are available to receive the echo traduced signal coming from the piezo-element through HVR_SW (LVOUTA, LVOUTB, LVOUTC, LVOUTD). The main issues in this PCB design are the capacitance values necessary to ensure good filtering and the effective decoupling between the low voltage inputs (IN1, IN2, IN3, IN4, and EN for each channel) and the HV switching signals (XDCR, HVOUT, etc.,), which is ensured by the implemented layer separation. 3.5 Operating supply conditions DocID Rev 1 17/28

18 Hardware layout and configuration UM1957 Table 5: DC working supply conditions Operating supply voltages Symbol Parameter Min. Typ. Max. Value VDD Positive supply voltage V VSS Negative supply voltage V HVP0 HVP1 HVM0 HVM1 TX0 high voltage positive supply TX1 high voltage positive supply TX0 high voltage negative supply TX1 high voltage negative supply 95 V 95 V -95 V -95 V The high voltage pins must be HVP0 HVP1 and HVM1 HVM0 18/28 DocID Rev 1

19 UM1957 Connectors 4 Connectors 4.1 Power supply The STEVAL-IME011V1 board is powered through the screw connectors as shown in the following figures. Figure 16: Power supply connector VDD (+5V - GND) Figure 17: Power supply connector VSS (GND - -5V) DocID Rev 1 19/28

20 Connectors Figure 18: Power supply connector HVP0 HVP1 and HVM0 HVM1 UM MCU Figure 19: USB mini-b connector (CN1) 20/28 DocID Rev 1

21 UM1957 Connectors Table 6: USB mini B connector pin out Pin number Description 1 Vbus (power) 2 DM (STM32 PA11) 3 DP (STM32 PA12) 4 N.C. 5 Ground Figure 20: JTAG connector Table 7: JTAG connector 1 DVDD 2 JTDI 3 JTMS 4 JTCK 5 JTDO 6 JRST 7 GND 8 NRST DocID Rev 1 21/28

22 Connectors UM1957 Figure 21: Boot connector Table 8: Boot connector 1 GND 2 BOOT0 (boot from flash memory) 3 DVDD (DFU mode) 22/28 DocID Rev 1

23 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD12 PD13 PD14 PD15 ADC_IN0 ADC_IN2 SPI_CLK SPI_CLK SPI1_MISO USBDM JTMS JTCK JTDI SPI3_MISO L5 L6 SPI_JTAG_1 JTDO SPI_JTAG_2 SPI2_MISO SPI_CLK JRST , VDDM1 VDDM2 DGND AGND1 AGND2 REF1_HVM0 REF2_HVM0 REF1_HVM1 REF2_HVM1 HVM0_A HVM0_B HVM0_C HVM0_D HVM1_A HVM1_B HVM1_C HVM1_D GND_PWR 6, UM1957 Schematic 5 Schematic Figure 22: STEVAL-IME011V1 circuit schematic AUX0 +5V +5V VDD LV+ LV- VSS LV- LV+ L1 L2 L3 L4 L1 L2 L3 L4 RL1 56 CF1 10F -5V R DVDD R1_F2 0 Shell RL2 56 D1 BAT20J -5V USB RL3 56 REG1 LD1117 VBUS D+ D- CB1 RL4 56 IN OUT GND CF3 10F CF4 10F ID 4 GND 5 BOOT0 R2_F2_F4 0 R1_F1_F4 R2_F1 0 0 AUX1 AUX2 AUX3 SHD 10,12 SHD INP 4,5 USB_PWR L5 R3_F L5 L6 RL5 56 D4 D3 L6 DVDD GND INN VDD GND RL6 56 CF2 10F REG2 OUTP BYPP ADJP 2 3 ADJN 8 BYPN 11 OUTN LT3032 BAT20J D2 UF1 DVDD D1 1 D2 3 DVDD OSC_IN 12 OSC_OUT 13 NRST C1_F2_F4 20 C2_F2_F F 2.2F AUX4 AUX5 AUX6 AUX7 USBUF01W6 PA0 23 PA1 24 PA2 25 PA3 26 PA4 29 PA5 30 PA6 31 PA7 32 PA8 67 PA9 68 PA10 69 PA11 70 PA12 71 PA13 72 PA14 76 PA V ADC_IN1 CC1 10nF CC2 10nF USBDM USBDP VDD1 VDD2 VDD3 VDD4 VDD5 VDDA VREF+ OSC_IN OSC_OUT NRST BOOT VSSA VSS3 VSS1 NC VREF- VSS2 VSS4 VSS5 RF1 107k RF2 62k RF3 62k RF4 107k OSC_OUT X1 Rosc 1M AVDD CF5 10F CF6 10F 8MHz Cosc1 22pF 22pF Cosc2 OSC_IN USBDP AN_SUPPLY AVSS PB0 35 PB1 36 PB2 37 PB3 89 PB4 90 PB5 91 PB6 92 PB7 93 PB8 95 PB9 PB PB11 48 PB12 51 PB13 52 PB14 53 PB15 54 U1 STM32F427 CB2 SPI_CLK CB7 CB3 CB8 CB11 CB4 SPI2_MISO CB9 CB12 SPI1_MISO SPI3_MISO PD11 CB5 CB10 AVSS DVDD SPI1 SPI2 SPI3 AVDD CB6 PC11 PC10 PC12 VBAT 6 PC0 15 PC1 16 PC0 PC2 17 PC1 PC3 18 PC2 PC4 33 PC3 PC5 34 PC4 PC6 63 PC5 PC7 64 PC6 PC8 65 PC9 66 PC10 78 PC11 79 PC10 PC12 PC PC11 PC12 PC14 8 PC13 PC15 9 PC14 PC15 AVDD PC15 PC14 PC13 PC0 PC1 PC2 PC5 PC4 PC3 PC10 PC11 PC12 PC6 THSD AVSS RP1 10k DVDD VDDP VDDP2 53 INT_BIAS REF1_HVP REF2_HVP0 REF1_HVP REF2_HVP1 HVP0_A 6 39 HVP0_B 11 HVP0_C 38 HVP0_D HVP1_A 8 43 HVP1_B 9 HVP1_C 40 HVP1_D IN3_A IN2_A IN1_A 19 IN1_B 20 IN2_B 31 IN3_B IN3_C IN2_C IN1_C IN1_D 52 IN2_D D_CTR IN4 IN3_D 32 THSD AVDD PC HVM1 RAD1 2.7k RAD2 100k HVP0 CR1 22nF CR5 3.9nF HVM0 RP2 10k CR2 22nF U2 STHV748 CR6 ZAD1 DZ2S033 ADC_IN0 CAD1 3.9nF HVP1 CR3 22nF CR7 DZ2S033 ZAD2 POT1 50 % 3.9nF HVM1 CR4 USR_RX 22nF RP3 10k XDCR_A XDCR_B XDCR_C 26 XDCR_D HVOUT_A 5 55 HVOUT_B 12 HVOUT_C 37 HVOUT_D 44 LVOUT_A LVOUT_B LVOUT_C 25 LVOUT_D GND_PWR_D GND_PWR_C GND_PWR_B GND_PWR_A 59 CR8 3.9nF HVP1 RAD3 100k ADC_IN2 DVDD CAD2 RAD4 2.7k ADC_IN1 RP4 10k HVP0 HVP1 P1 P2 P3 P4 HVM1 HVM1 HVM0 DVDD RHVM 0 HVP0 HVM0 HVP1 HVM1 NRST HVM0 CLA 270pF RLA 100 CRA 270pF RRA 100 CB13 CB17 CB21 CB25 HVP1 CLB 270pF RLB 100 CB14 CB18 CB22 CB26 RHVP 0 CRB 270pF RRB 100 CLC 270pF RLC 100 CRC CB15 CB19 CB23 CB27 HVP0 270pF RRC 100 CLD 270pF RLD 100 CRD 270pF RRD 100 CB16 CB20 CB24 CB28 RGND 0 CF7 10F CF8 10F CF9 10F CF10 10F GND_PWR NRST HVP0 HV+ HV- GND_PWR HVM0 HV+ HV- HVP1 HV+ HV- GND_PWR HVM1 HV+ HV- JTAG XDCRA XDCRB XDCRC XDCRD GND_PWR LVOUTA LVOUTB LVOUTC LVOUTD RE0 RE1 RE2 RE3 RE4 RE5 RE RE7 56 AUX7 AUX6 AUX5 AUX4 AUX3 AUX2 AUX1 AUX0 P4 P3 P2 P1 L4 L3 L2 L1 RSHD 330 RTHSD 10k CP1 STRCP2 PRGCP3 STP CP4 USRCRST RST JRST JTDO SHD THSD JTCK JTMS JTDI GSPG SG DVDD DocID Rev 1 23/28

24 PCB layout UM PCB layout Figure 23: Top layer Figure 24: Inner 1 24/28 DocID Rev 1

25 UM1957 Figure 25: Inner 2 PCB layout Figure 26: Inner 3 DocID Rev 1 25/28

26 PCB layout Figure 27: Inner 4 UM1957 Figure 28: Bottom layer 26/28 DocID Rev 1

27 UM1957 Revision history 7 Revision history Table 9: Document revision history Date Version Changes 26-Nov Initial release. DocID Rev 1 27/28

28 UM1957 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document STMicroelectronics All rights reserved 28/28 DocID Rev 1