Virtex-II Pro FF1152 Development Board User s Guide

Transcription

1 Virtex-II Pro FF1152 Development Board User s Guide Version 1.3 October 2004 PN# DS-MANUAL-2VPx-FF1152

2 Table of Contents 1 OVERVIEW THE VIRTEX-II PRO FF1152 SYSTEM BOARD FUNCTIONAL DESCRIPTION XILINX VIRTEX-II PRO FPGA (XC2VP20/P30/P40/P50-FF1152) MGT INTERFACE MGT Reference Clock Inputs MGT SMA Connectors GbE Interface Infineon isfp Gb Module Host Board Connector LVDS INTERFACE SPI-4.2 Interface SPI-4.2 Pin Assignments LVDS Connector MEMORY Two Blocks of x32 Memory Configuration Single Block of x64 Memory Configuration SDRAM Interfaces CLOCK SOURCES FPGA_GCLK0 Clock Source Programmable LVDS Clock Sources ICS8442 Programmable LVDS Clock Synthesizer ICS8442 Clock Generation ICS8442 Programming Modes ICS8442 M and N Settings MISCELLANEOUS I/O INTERFACE /100 Ethernet IDE/General-Purpose 40-Pin Header LCD Panel RS User DIP and PB Switches User LEDs CONFIGURATION AND DEBUG PORTS JTAG Chain System ACE Module Connector Serial Flash JTAG Port (PC4) CPU JTAG Port CPU Debug Port CPU Trace Port Configuration Modes SUPPLY VOLTAGES BANK I/O VOLTAGE P160 EXPANSION MODULE SIGNAL ASSIGNMENTS REVISIONS...53 October 27, 2004 i

3 Figures FIGURE 1 - VIRTEX-II PRO FF1152 DEVELOPMENT PLATFORM BLOCK DIAGRAM...4 FIGURE 2 - MGT PORTS ON THE FF1152 SYSTEM BOARD...6 FIGURE 3 - GBE INTERFACE USING ISFP MODULES...11 FIGURE 4 - ISFP MODULE (PHOTO TAKEN FROM INFINEON WEB PAGE)...11 FIGURE 5 - HOST BOARD CONNECTOR AMP (PHOTO TAKEN FROM AMP WEB PAGE)...12 FIGURE 6 ISFP MODULE INTERFACE TO THE VIRTEX-II PRO FPGA...13 FIGURE 7 - SPI-4.2 INTERFACE...15 FIGURE 8 SAMTEC QSE TYPE CONNECTOR FOR THE SPI-4.2 INTERFACE...17 FIGURE 9 32-BIT SDRAM INTERFACE...18 FIGURE BIT SDRAM INTERFACE...19 FIGURE 11 - SDRAM INTERFACE...19 FIGURE 12 - CLOCK SOURCES ON THE FF1152 BOARD...23 FIGURE 13 FPGA_GCLK0 CLOCK SOURCE JUMPER SETTINGS...25 FIGURE 14 ICS8442 CLOCK SYNTHESIZER...26 FIGURE 15 ICS8442 CLOCK SYNTHESIZER INTERFACE TO THE FPGA...29 FIGURE 16 ICS8442 CLOCK SYNTHESIZER M AND N DIP SWITCHES...30 FIGURE 17 M AND N DIP SWITCHES FOR THE SYNTHESIZERS...31 FIGURE 18 10/100 ETHERNET INTERFACE...34 FIGURE PIN USER HEADER WITH IDE PINOUT...35 FIGURE 20 IDE INTERFACE...36 FIGURE 21 RS232 INTERFACE...37 FIGURE 22 JTAG CHAIN...39 FIGURE 23 FF1152 DEVELOPMENT BOARD CONFIGURATION INTERFACE...42 FIGURE 24 FF1152 DEVELOPMENT BOARD JTAG CHAIN...43 FIGURE 25 SERIAL FLASH CONFIGURATION INTERFACE...44 FIGURE 26 PC4 JTAG PORT CONNECTOR...46 FIGURE 27 - CPU JTAG PORT CONNECTOR...47 FIGURE 28 - CPU DEBUG PORT CONNECTOR...47 FIGURE 29 CPU TRACE PORT CONNECTOR...48 FIGURE 30 - VOLTAGE REGULATORS...50 October 27, 2004 ii

4 Tables TABLE 1 - DIFFERENCES BETWEEN 2VP20 AND 2VP30 DEVICES...5 TABLE 2 - COMMUNICATIONS STANDARDS SUPPORTED BY ROCKETIO TRANSCEIVER...5 TABLE 3 VIRTEX-II PRO BOARD TOP MGT4 AND TABLE 4 VIRTEX-II PRO BOARD TOP MGT7 AND TABLE 5 VIRTEX-II PRO BOARD BOTTOM MGT16 AND TABLE 6 VIRTEX-II PRO BOARD BOTTOM MGT19 AND TABLE 7 ISFP HOST CONNECTOR PIN DESCRIPTION...12 TABLE 8 ISFP PIN ASSIGNMENTS...14 TABLE 9 SPI-4.2 TRANSMIT PIN ASSIGNMENTS...15 TABLE 10 SPI-4.2 RECEIVE PIN ASSIGNMENTS...16 TABLE 11 SDRAM1 INTERFACE PIN ASSIGNMENTS...19 TABLE 12 SDRAM2 INTERFACE PIN ASSIGNMENTS...21 TABLE 13 - CLOCK SOURCES...24 TABLE 14 JP25 JUMPER SETTINGS...25 TABLE 15 JUMPER SETTINGS FOR ROUTING THE P160 CLOCK TO FPGA I/O PIN...25 TABLE 16 ICS8442 CLOCK SYNTHESIZER PIN DESCRIPTION...27 TABLE 17 INPUT CLOCK SELECT SIGNAL DESCRIPTION...27 TABLE 18 ICS8442 N SETTINGS...28 TABLE 19 EXAMPLES OF THE ICS8442 M AND N SETTINGS...28 TABLE 20 DIP SWITCH SETTING FOR M[8:0]...31 TABLE 21 DIP SWITCH SETTING FOR N[1:0]...31 TABLE 22 SYNTHESIZER CLOCK OUTPUTS FOR M AND N VALUES...32 TABLE 23 FPGA PIN ASSIGNMENTS FOR THE SYNTHESIZER INTERFACE...33 TABLE 24 ETHERNET PIN ASSIGNMENTS...34 TABLE 25 IDE CONNECTOR PIN ASSIGNMENTS...36 TABLE 26 LCD INTERFACE SIGNALS...37 TABLE 27 RS232 SIGNALS...38 TABLE 28 PUSH SWITCH PIN ASSIGNMENTS...38 TABLE 29 DIP SWITCH PIN ASSIGNMENTS...38 TABLE 30 LED PIN ASSIGNMENTS...39 TABLE 31 SYSTEM ACE CLOCK SOURCE...41 TABLE 32 - SAM INTERFACE SIGNALS...41 TABLE 33 JTAG CHAIN JUMPER SETTINGS...43 TABLE 34 FILES IN THE FLASH_UTILITIES FOLDER...45 TABLE 35 PLATFORM FLASH SELECTION...45 TABLE 36 CPU DEBUG INTERFACE SIGNALS...48 TABLE 37 TRACE PORT PIN ASSIGNMENTS...49 TABLE 38 - FPGA CONFIGURATION MODE JUMPER SETTINGS...49 TABLE 39 CURRENT PROVIDED FOR EACH VOLTAGE SOURCE ON THE BOARD...50 October 27, 2004 iii

5 TABLE 40 I/O BANK VOLTAGES...50 TABLE 41 P160 CONNECTOR PIN ASSIGNMENTS...51 TABLE 42 - P160 CONNECTOR PIN ASSIGNMENTS...52 October 27, 2004 iv

6 1 Overview The Memec Design Virtex-II Pro FF1152 Development Kit provides a complete development platform for designing and verifying applications based on the Xilinx Virtex-II Pro FPGA family. This kit enables designers to implement embedded processor based applications with extreme flexibility using IP cores and customized modules. The Virtex-II Pro FPGA with its integrated PowerPC processor and powerful RocketIO Multi-Gigabit Transceivers (MGT) makes it possible to develop highly flexible and high-speed serial transceiver applications. The kit bundles the Xilinx Embedded Development Kit (EDK) with an advanced Virtex-II Pro hardware platform, power supply, and reference designs. Xilinx ISE software and a JTAG cable are also required and available as kit options. The EDK includes standard peripherals, GNUbased software tools, and system configuration tools. The GNU-based development tools are composed of a C compiler, assembler, linker and debugger. The Virtex-II Pro FF1152 system board utilizes the Xilinx XC2VP20-6FF1152C, XC2VP30-6FF1152C, XC2VP40-6FF1152C, or XC2VP50-6FF1152C FPGA. These FPGA devices contain two PowerPC processors and eight/twelve/sixteen RocketIO transceivers supporting data transfer rates of up to Gbps/port (P40/P50 have eight/sixteen MGT ports). The Virtex-II Pro system board is designed to provide eight RocketIO transceivers, hence, when the board is populated with the XC2VP40 or XC2VP50 FPGA, four/eight out of the twelve/sixteen RocketIO transceivers on the XC2VP40/P50 FPGA will not be available to the users. The Virtex-II Pro FF1152 system board includes two memory blocks of 8Mx32 SDRAM memory each, five clock sources, two RS-232 ports, high-speed 16-bit LVDS interface supporting SPI-4.2, two isfp GbE optical interfaces, 10/100 Ethernet PHY, IDE connector, and additional user support circuitry to develop a complete system. The board also supports the Memec Design P160 expansion module standard, allowing application specific expansion modules to be easily added. A System ACE interface on the Virtex-II Pro system board gives software designers the ability to run real-time operating systems (RTOS) from removable CompactFlash cards. The Virtex-II Pro FPGA family has the advanced features needed to fit demanding and highperformance applications. The Virtex-II Pro FF1152 Development Kit provides an excellent platform to explore these features so that you can quickly and effectively meet your time-tomarket requirements. The Virtex-II Pro FF1152 Development Kit includes the following: - Virtex-II Pro FF1152 development board with 2VP20, P30, P40, or P50 FPGA (Rev 1 Board) - 70W switching power supply - RS-232 serial cable - Two coax loop back cables for MGT testing - Documentation CD Optional items that support development efforts: - Xilinx Embedded Development Kit CDs (EDK) - Xilinx ISE software - JTAG cable - isfp transceiver modules and fiber loop back cable - System ACE Module (included with P40 and P50 kits) October 27,

7 - Additional coax loop back cables - Wind River visionprobe-ii and visionice-ii tools Contact your local Memec distributor for assistance with any of these items. 2 The Virtex-II Pro FF1152 System Board 3 Functional Description A high-level block diagram of the Virtex-II Pro FF1152 development platform is shown below followed by a brief description of each sub-section. A list of features for this board is shown below: Xilinx XC2VP20/P30/P40/P50-FF1152C FPGA Support for 10G Optical Module High-speed LVDS Interface Supporting SPI-4.2 Six Rocket I/O Ports Supporting up to 3.125Gbits/port Two Optical GbE Ports Support for GbE Optical Module Three Programmable LVDS Clock Sources (25 700MHz) On-board LVTTL 100MHz Oscillators On-board LVTTL Oscillator Socket (4/8-Pin Oscillators) Two User LVDS Clock Inputs via Differential SMA Connectors October 27,

8 Three User LVDS Clock Outputs via Differential SMA Connectors Two SDRAM Memory Blocks (32MB each, x32 memory configuration) SDRAM Memory Blocks can be used as a single x64 Memory P160 Connectors 10/100 PHY A 40-Pin User Header to be used as General-Purpose I/O or IDE interface LCD Panel 16/32Mb Atmel Data Flash for FPAG configuration JTAG Programming/Configuration Port CPU JTAG/Debug Ports CPU TRACE Port SystemACE Module Connector Two RS232 Port User LEDs User DIP and Push-Button Switches October 27,

9 MGT Interface RocketIO SMA Connectors (6 MGT ports) isfp GbE Module Connectors (2 MGT ports) 80-Pin Connector P160 Module 80-Pin Connector Configuration and Debug Ports LVDS Interface System ACE Connector LVDS connectors CPU JTAG Port Memory Interface XC9536XV Parallel Cable IV JTAG Port 32MB SDRAM (x32) 32MB SDRAM (x32) Virtex-II Pro FPGA XC2VP20/P30 (FF1152) Atmel Flash Parallel Cable IV Flash Prog. CPU Debug Port Miscellaneous I/O CPU TRACE Port 10/100 PHY 40-Pin Header (IDE Pinout) Clock Sources Programmable LVDS Clock Source (3) Voltage Regulators 2.5V Regulator RS232 Ports (2) SMA Clock Outputs (3 clock sources) 1.5V Regulator LCD Panel LVTTL 2.5V RocketIO Supply User Switches User LEDs LVTTL OSC Socket (4/8-Pin) SMA Clock Inputs (2 clock sources) Regulated Voltages 3.3V, 5.0V, +12, -12, and -5.0V Figure 1 - Virtex-II Pro FF1152 Development Platform Block Diagram October 27,

10 3.1 Xilinx Virtex-II Pro FPGA (XC2VP20/P30/P40/P50-FF1152) The P20/P30/P40/P50 Virtex-II Pro FPGA devices have two PowerPC processors and 8 DCMs. The following table shows the differences among these devices in the FF1152-pin package. Table 1 - Differences between 2VP20 and 2VP30 devices Device Number of Slices BlockRAM (Kb) Available User I/O Multipliers RocketIO Transceivers Configuration PROM XC2VP20 9,280 1, x XCF04S XC2VP30 13,696 2, x XCF04S XC2VP40 19, x XCF08 XC2VP50 23,616 4, x XCF08 In order to have a common PCB design for the P20/P30/P40/P50 devices, the board will be designed to utilize the user I/O pins that are common among these devices. Hence, the maximum available user I/O pins on the P20/P30/P40/P50 development board will be MGT Interface The RocketIO transceiver is based on Mindspeed s SkyRail technology. Up to 16 transceiver modules are available on a single Virtex-II Pro FPGA, depending on the part being used. The transceiver module is designed to operate at any serial bit rate in the range of 500 Mb/s to Gb/s per channel, including the specific bit rates used by the communications standards listed in the following table. The serial bit rate need not be configured in the transceiver, as the received data, the applied reference clock, and the SERDES_10B attribute imply the operating frequency of the transceiver. Table 2 - Communications Standards Supported by RocketIO Transceiver Mode Channels (# of transceivers) I/O Bit Rate (Gb/s) Internal Clock Rate (REFCLK Mhz) Fibre Channel Gbit Ethernet XAUI (10-Gbit Ethernet) Infiniband 1, 4, Aurora (Xilinx protocol) 1, 2, Custom Mode 1, 2, 4, 8, up to The following figure shows the four RocketIO transceiver ports used on the Virtex-II Pro development board. These transceivers are physically located at the top and the lower side of the Virtex-II Pro FPGA. The Virtex-II Pro development board is designed to provide programmable reference clock inputs to the top and bottom RocketIO transceivers (refer to the Clock Sources section for more information on the MGT reference clock inputs). October 27,

11 SMA Connectors SMA Connectors SMA Connectors SMA Connectors SMA Connectors TXP TXN RXP RXN TXP TXN RXP RXN TXP TXN RXP RXN TXP TXN RXP RXN RocketIO Port0 RocketIO Port1 Top MGTs RocketIO Port2 RocketIO Port3 Programmable LVDS Clock Source Programmable LVDS Clock Source RocketIO Ref Clock (Top) RocketIO Ref Clock (Bot) Virtex-II Pro XC2VP20/P30-FF1152 Bottom MGTs RocketIO Port7 RocketIO Port6 RocketIO Port5 RocketIO Port4 TXP TXN RXP RXN TXP TXN RXP RXN RXN RXP TXN TXP RXN RXP TXN TXP isfp GbE Module Connector isfp GbE Module Connector SMA Connectors SMA Connectors Figure 2 - MGT Ports on the FF1152 System Board October 27,

12 RocketIO Port # 0 1 Table 3 Virtex-II Pro Board Top MGT4 and 6 Signal Name Virtex-II Pro Description Pin # AVCCAUXRX4 B26 Analog power supply for receive circuitry of the multi gigabit transceiver (2.5V). VTRXPAD4 B27 Receive termination supply for the multi gigabit transceiver (1.8V to 2.8V). RXNPAD4 A26 Negative differential receive port of the multi RXPPAD4 A27 Positive differential receive port of the multi GNDA4 C27 Ground for the analog circuitry of the multi TXNPAD4 A29 Negative differential transmit port of the multi TXPPAD4 A28 Positive differential transmit port of the multi AVCCAUXTX4 B28 Analog power supply for transmit circuitry of the multi gigabit transceiver (2.5V). VTTXPAD4 B29 Transmit termination supply for the multi gigabit transceiver (1.8V to 2.8V). AVCCAUXRX6 B18 Analog power supply for receive circuitry of the multi gigabit transceiver (2.5V). VTRXPAD6 B19 Receive termination supply for the multi gigabit transceiver (1.8V to 2.8V). RXNPAD6 A18 Negative differential receive port of the multi RXPPAD6 A19 Positive differential receive port of the multi GNDA6 C20 Ground for the analog circuitry of the multi TXNPAD6 A21 Negative differential transmit port of the multi TXPPAD6 A20 Positive differential transmit port of the multi AVCCAUXTX6 B20 Analog power supply for transmit circuitry of the multi gigabit transceiver (2.5V). VTTXPAD6 B21 Transmit termination supply for the multi gigabit transceiver (1.8V to 2.8V). RocketIO Port # 2 Table 4 Virtex-II Pro Board Top MGT7 and 9 Signal Name Virtex-II Pro Description Pin # AVCCAUXRX7 B14 Analog power supply for receive circuitry of the multi gigabit transceiver (2.5V). VTRXPAD7 B15 Receive termination supply for the multi gigabit transceiver (1.8V to 2.8V). RXNPAD7 A14 Negative differential receive port of the multi RXPPAD7 A15 Positive differential receive port of the multi GNDA7 C15 Ground for the analog circuitry of the multi TXNPAD7 A17 Negative differential transmit port of the multi October 27,

13 3 TXPPAD7 A16 Positive differential transmit port of the multi AVCCAUXTX7 B16 Analog power supply for transmit circuitry of the multi gigabit transceiver (2.5V). VTTXPAD7 B17 Transmit termination supply for the multi gigabit transceiver (1.8V to 2.8V). AVCCAUXRX9 B6 Analog power supply for receive circuitry of the multi gigabit transceiver (2.5V). VTRXPAD9 B7 Receive termination supply for the multi gigabit transceiver (1.8V to 2.8V). RXNPAD9 A6 Negative differential receive port of the multi RXPPAD9 A7 Positive differential receive port of the multi GNDA9 C8 Ground for the analog circuitry of the multi TXNPAD9 A9 Negative differential transmit port of the multi TXPPAD9 A8 Positive differential transmit port of the multi AVCCAUXTX9 B8 Analog power supply for transmit circuitry of the multi gigabit transceiver (2.5V). VTTXPAD9 B9 Transmit termination supply for the multi gigabit transceiver (1.8V to 2.8V). RocketIO Port # 4 5 Table 5 Virtex-II Pro Board Bottom MGT16 and 18 Signal Name Virtex-II Pro Description Pin # AVCCAUXRX16 AN6 Analog power supply for receive circuitry of the multi gigabit transceiver (2.5V). VTRXPAD16 AN7 Receive termination supply for the multi gigabit transceiver (1.8V to 2.8V). RXNPAD16 AP6 Negative differential receive port of the multi RXPPAD16 AP7 Positive differential receive port of the multi GNDA16 AM8 Ground for the analog circuitry of the multi TXNPAD16 AP9 Negative differential transmit port of the multi TXPPAD16 AP8 Positive differential transmit port of the multi AVCCAUXTX16 AN8 Analog power supply for transmit circuitry of the multi gigabit transceiver (2.5V). VTTXPAD16 AN9 Transmit termination supply for the multi gigabit transceiver (1.8V to 2.8V). AVCCAUXRX18 AN14 Analog power supply for receive circuitry of the multi gigabit transceiver (2.5V). VTRXPAD18 AN15 Receive termination supply for the multi gigabit transceiver (1.8V to 2.8V). RXNPAD18 AP14 Negative differential receive port of the multi RXPPAD18 AP15 Positive differential receive port of the multi GNDA18 AM15 Ground for the analog circuitry of the multi October 27,

14 TXNPAD18 AP17 Negative differential transmit port of the multi TXPPAD18 AP16 Positive differential transmit port of the multi AVCCAUXTX18 AN16 Analog power supply for transmit circuitry of the multi gigabit transceiver (2.5V). VTTXPAD18 AN17 Transmit termination supply for the multi gigabit transceiver (1.8V to 2.8V). RocketIO Port # 6 7 Table 6 Virtex-II Pro Board Bottom MGT19 and 21 Signal Name Virtex-II Pro Description Pin # AVCCAUXRX19 AN18 Analog power supply for receive circuitry of the multi gigabit transceiver (2.5V). VTRXPAD19 AN19 Receive termination supply for the multi gigabit transceiver (1.8V to 2.8V). RXNPAD19 AP18 Negative differential receive port of the multi RXPPAD19 AP19 Positive differential receive port of the multi GNDA19 AM20 Ground for the analog circuitry of the multi TXNPAD19 AP21 Negative differential transmit port of the multi TXPPAD19 AP20 Positive differential transmit port of the multi AVCCAUXTX19 AN20 Analog power supply for transmit circuitry of the multi gigabit transceiver (2.5V). VTTXPAD19 AN21 Transmit termination supply for the multi gigabit transceiver (1.8V to 2.8V). AVCCAUXRX21 AN26 Analog power supply for receive circuitry of the multi gigabit transceiver (2.5V). VTRXPAD21 AN27 Receive termination supply for the multi gigabit transceiver (1.8V to 2.8V). RXNPAD21 AP26 Negative differential receive port of the multi RXPPAD21 AP27 Positive differential receive port of the multi GNDA21 AM27 Ground for the analog circuitry of the multi TXNPAD21 AP29 Negative differential transmit port of the multi TXPPAD21 AP28 Positive differential transmit port of the multi AVCCAUXTX21 AN28 Analog power supply for transmit circuitry of the multi gigabit transceiver (2.5V). VTTXPAD21 AN29 Transmit termination supply for the multi gigabit transceiver (1.8V to 2.8V). October 27,

15 3.2.1 MGT Reference Clock Inputs The top and bottom MGT ports have two sources for the reference clock input. A dedicated programmable LVDS synthesizer is used to provide a variable clock source to the top and bottom MGT ports to support up to 3.125Gbps data rate. The top and bottom MGT ports are also provided with a dedicated pair of differential SMA connectors for user clock inputs. The following figure shows the clock sources provided to the MGT ports. SMA Connectors SMA Connectors Programmable LVDS Clock Source BREFCLK Clock Inputs (Bank 0) Top MGTs BREFCLK2 Clock Inputs (Bank 1) Virtex-II Pro XC2VP20/P30/P40/P50-FF1152 BREFCLK Clock Inputs (Bank 5) Bottom MGTs BREFCLK2 Clock Inputs (Bank 4) Programmable LVDS Clock Source SMA Connectors SMA Connectors The differential clock outputs of the Programmable LVDS Clock Source that are connected to the SMA connectors, are the same as the clock outputs going to the BREFCLK clock inputs of the top and bottom MGT ports. Hence, the clock outputs at the SMA connectors can be used to provide a trigger input to the scope during MGT testing MGT SMA Connectors The MGT SMA connectors on the board can be used as general-purpose high-speed serial links to support data rates up to 3.125Gbps. The Virtex-II Pro development board uses four of these MGT ports to support a 10GbE interface via using a 10GbE P160 module. October 27,

16 3.2.3 GbE Interface The following figure shows a high-level block diagram of the GbE interface on the FF1152 development board. This interface utilizes two of the bottom MGT ports and a set of low-speed control signals to interface to two Infineon isfp modules. The programmable LVDS synthesizer on the board is used to operate the MGT ports at 1.25Gbps to meet the GbE data rate. MGT Gbps Control Infineon isfp GbE Module GbE Virtex-II Pro FPGA P20/P30 (FF1152) MGT Gbps Control Infineon isfp GbE Module GbE Figure 3 - GbE Interface Using isfp Modules Infineon isfp Gb Module The Gb interface is designed around the Intelligent Small Form-factor Pluggable (isfp) and the Small Form-factor Pluggable (SFP) modules from Infineon. Two Infineon tri-mode modules (part # V23848-M305-C56) are included in the isfp kit, although any SFP compatible module can be used. The Infineon isfp family is based on the Physical Medium Depend (PMD) sub-layer and baseband medium compliant to SONET OC-48 SR-1 and SDH STM I-16. This transceiver supports the LC connection concept that is compatible with RJ-45 style interconnect. The module is designed to support data rates from 155Mbps to 2.67Gbps. The following figure shows the isfp module from Infineon. For more information, please refer to the Infineon isfp module data sheet. Figure 4 - isfp Module (photo taken from Infineon Web Page) October 27,

17 3.2.5 Host Board Connector The isfp module connects to the FF1152 board via the Host Board Connector (the FF1152 board acts as the Host Board for the isfp module). This 20-pin connector provides connections for power, ground, high-speed serial link, and the low-speed control signals for controlling the operation of the isfp module. Figure 5 - Host Board Connector AMP (photo taken from AMP Web Page) The following table shows the Host Board Connector pin assignments and provides a brief description of each signal. Table 7 isfp Host Connector Pin Description Pin Number Name Function 1 VEET Transmitter Ground 2 Tx Fault Transmitter Fault Indication 3 Tx Disable Transmitter Disable 4 MOD-DEF(2) Module Definition 2 (Serial Interface Data Line) 5 MOD-DEF(1) Module Definition 1 (Serial Interface Clock Line) 6 MOD-DEF(0) Module Definition 0 (Module Present Signals, active low) 7 Rate Select Not Connected 8 LOS Loss of Signal 9 VEER Receiver Ground 10 VEER Receiver Ground 11 VEER Receiver Ground 12 RD- Inverse Received Data Out 13 RD+ Received Data Out 14 VEER Receiver Ground 15 VCCR Receiver Power 16 VCCT Transmitter Power 17 VEET Transmitter Ground 18 TD+ Transmitter Data In 19 TD- Inverse Transmitter Data In 20 VEET Transmitter Ground October 27,

18 isfp GbE Module Connector isfp_td1_p isfp_td1_n isfp_rd1_p isfp_rd1_n TD+ TD- RD+ RD- isfp_tr1_txdisable isfp_tr1_rateselect isfp_tr1_moddef2 isfp_tr1_moddef1 isfp_tr1_moddef0 isfp_tr1_txfault isfp_tr1_los Tx Disable Rate Select MOD-DEF(2) MOD-DEF(1) MOD-DEF(0) Tx Fault LOS System Interface GbE Virtex-II Pro FPGA P20/P30/P40/P50- FF1152 isfp GbE Module Connector isfp_td2_p isfp_td2_n isfp_rd2_p isfp_rd2_n TD+ TD- RD+ RD- isfp_tr2_txdisable isfp_tr2_rateselect isfp_tr2_moddef2 isfp_tr2_moddef1 isfp_tr2_moddef0 isfp_tr2_txfault isfp_tr2_los Tx Disable Rate Select MOD-DEF(2) MOD-DEF(1) MOD-DEF(0) Tx Fault LOS System Interface GbE Figure 6 isfp Module Interface to the Virtex-II Pro FPGA October 27,

19 Table 8 isfp Pin Assignments Signal Name Virtex-II Pro Pin # isfp #1 isfp_td1_p AP28 isfp_td1_n AP29 isfp_rd1_p AP27 isfp_rd1_n AP26 isfp_tr1_los AL29 isfp_tr1_moddef0 AL24 isfp_tr1_moddef1 AM24 isfp_tr1_moddef2 AL27 isfp_tr1_rateselect AM28 isfp_tr1_txdisable AL28 isfp_tr1_txfault AL30 isfp #2 isfp_td2_p AP20 isfp_td2_n AP21 isfp_rd2_p AP19 isfp_rd2_n AP18 isfp_tr2_los AM22 isfp_tr2_moddef0 AL19 isfp_tr2_moddef1 AL20 isfp_tr2_moddef2 AL21 isfp_tr2_rateselect AL22 isfp_tr2_txdisable AM21 isfp_tr2_txfault AL LVDS Interface The FF1152 development board provides high-speed LVDS connectors supporting a SPI-4.2 interface. This interface consists of 36 LVDS signal pairs (72 FPGA signals) and 6 single-ended signals. In addition to the SPI-4.2 interface, the LVDS interface is designed to support XSBI 16-bit to support a 10GbE interface on the FF1152 development platform. The following sections provide a brief description of the LVDS interface on this development board SPI-4.2 Interface The FF1152 development board provides a SPI-4.2 via a 16-bit parallel LVDS electrical interface. The following figure shows the SPI-4.2 interface on the board. The transmit and receive interface of the SPI-4.2 are implemented using LVDS signals while the status flow control signals are implemented using single-ended LVTTL signals. October 27,

20 SysClk_P SysClk_N TDat[15:0] TDClk LVDS Signals TDat[15:0] TDClk Transmit Link Layer TCtl TCtl TStat[1:0] TStat[1:0] TSClk TSClk Virtex-II Pro FPGA P20/P30-FF1152 LVTTL Signals LVDS Connectors LVDS Signals RDat[15:0] RDat[15:0] RDClk RDClk Receive Link Layer RCtl RCtl RStat[1:0] RStat[1:0] RSClk RSClk LVTTL Signals SPI-4.2 Pin Assignments Figure 7 - SPI-4.2 Interface The following table shows the SPI-4.2 pin assignments for the 2VP20/P30/P40/P50 FPGA in the FF1152-pin package. These pin assignments must be used in the board design in order to meet the SPI-4.2 interface core requirements. Table 9 SPI-4.2 Transmit Pin Assignments Virtex-II Pro Pin # LVDS Signal Name J29 Connector Pin # LVDS TX LVDS Signal Name 5.0V V 5.0V V GND 5 6 GND 3.3V V 3.3V V GND GND 2.5V V 2.5V V GND GND E17 TSCLK NC NC NC GND GND AK28 TSTAT NC Virtex-II Pro Pin # October 27,

21 AK29 TSTAT NC GND GND AA33 TDat_N(15) TDat_N(14) W26 AB33 TDat_P(15) TDat_P(14) W25 GND GND AA32 TDat_N(13) TDat_N(12) Y26 AA31 TDat_P(13) TDat_P(12) Y25 AA30 TDat_N(11) TDat_N(10) AB32 AA29 TDat_P(11) TDat_P(10) AB31 GND GND AA28 TDat_N(9) TDat_N(8) AB30 AA27 TDat_P(9) TDat_P(8) AB29 GND GND AA26 TDat_N(7) TDat_N(6) AC32 AA25 TDat_P(7) TDat_P(6) AC31 GND GND AD34 TDat_N(5) TDat_N(4) AB28 AE34 TDat_P(5) TDat_P(4) AB27 GND GND AC29 TDat_N(3) TDat_N(2) AB26 AC28 TDat_P(3) TDat_P(2) AB25 GND GND AD30 TDat_N(1) TDat_N(0) AE33 AD29 TDat_P(1) TDat_P(0) AF33 GND GND AD28 TCtl_N TDCLK_N AE31 AD27 TCtl_P TDCLK_P AE30 GND GND GND GND GND GND GND GND Table 10 SPI-4.2 Receive Pin Assignments LVDS Signal J30 Connector Pin # LVDS Signal Name LVDS RX Name 5.0V V 5.0V V GND 5 6 GND 3.3V V 3.3V V GND GND 2.5V V 2.5V V GND GND AK22 RSCLK NC NC NC GND GND AK24 RSTAT NC AK27 RSTAT NC GND GND H33 RDat_N(15) RDat_N(14) M25 H34 RDat_P(15) RDat_P(14) M26 GND GND K30 RDat_N(13) RDat_N(12) L27 Virtex-II Pro Pin # Virtex-II Pro Pin # October 27,

22 K31 RDat_P(13) RDat_P(12) L28 L29 RDat_N(11) RDat_N(10) N25 L30 TDat_P(11) RDat_P(10) N26 GND GND M28 RDat_N(9) RDat_N(8) N27 M29 RDat_P(9) RDat_P(8) N28 GND GND L31 RDat_N(7) RDat_N(6) P25 L32 RDat_P(7) RDat_P(6) P26 GND GND N29 RDat_N(5) RDat_N(4) P27 N30 RDat_P(5) RDat_P(4) P28 GND GND N31 RDat_N(3) RDat_N(2) R25 N32 RDat_P(3) RDat_P(2) R26 GND GND P29 RDat_N(1) RDat_N(0) T24 P30 RDat_P(1) RDat_P(0) U24 GND GND R28 RCtl_N RDCLK_N E18 R29 RCtl_P RDCLK_P D18 GND GND GND GND GND GND GND GND LVDS Connector The design of the SPI-4.2 interface requires use of a high-speed and high quality connector. The FF1152 development board uses the SAMTEC QSE type connector for this interface. The QSE L-Dx-A connector from SAMTEC provides up to 28 LVDS signals connections in addition to adequate number ground connections for improving the signal quality. Two of these connectors are used on the FF1152 development board to implement the SPI-4.2 interface. In addition, a mating LVDS cable is available from Samtec (part number #EQCD TTR-TBL-1). The following figure shows the QSE type connector from SAMTEC (the picture is obtained from the SAMTEC web site ( Figure 8 SAMTEC QSE Type Connector for the SPI-4.2 Interface October 27,

23 3.4 Memory The FF1152 development board provides two separate interfaces to physical memory blocks. A dedicated set of pins interface to 32 MB of SDRAM and another set of FPGA pins provide an interface to a second 32 MB block of SDRAM. These two dedicated memory interfaces improve the performance of the processor-based designs in networking applications where 10GbE and/or GbE ports are utilized. A typical application of this dual-memory subsystem design would be a PowerPC based design where the processor executes code from the SDRAM and also sets up a DMA controller to move data to/from a high-speed serial link such as 10GbE and the second memory bank. The following figure shows the Virtex-II Pro interface to the SDRAM banks. These interfaces will be described in the subsequent sections Two Blocks of x32 Memory Configuration Address[0:13] Data[0:31] SDRAM (32MB) Control Virtex-II Pro FPGA P20/P30 (FF1152) Address[0:13] Data[0:31] SDRAM (32MB) Control Figure 9 32-bit SDRAM Interface October 27,

24 3.4.2 Single Block of x64 Memory Configuration Address[0:13] Virtex-II Pro FPGA P20/P30 (FF1152) Data[0:63] Control SDRAM (64MB) SDRAM Interfaces Figure bit SDRAM Interface The following figure shows the SDRAM interfaces on the FF1152 development board. Virtex-II Pro FPGA Data[15:0] Addr[13:0] BA[1:0] DQM1 DQM0 CSn RASn CASn WEn CLKE CLK Data[31:16] 8M x 16 SDRAM DQM3 DQM2 8M x 16 SDRAM Figure 11 - SDRAM Interface Table 11 SDRAM1 Interface Pin Assignments Signal Name Description FPGA Pin # sdram1_addr[0] Address 0 AD6 sdram1_addr[1] Address 1 W5 sdram1_addr[2] Address 2 V5 October 27,

25 sdram1_addr[3] Address 3 AH6 sdram1_addr[4] Address 4 Y6 sdram1_addr[5] Address 5 V7 sdram1_addr[6] Address 6 W6 sdram1_addr[7] Address 7 W7 sdram1_addr[8] Address 8 Y7 sdram1_addr[9] Address 9 AA6 sdram1_addr[10] Address 10 AA5 sdram1_addr[11] Address 11 AB7 sdram1_addr[12] Address 12 AA7 sdram1_addr[13] Address 13 AD7 sdram1_dq[0] Data 0 AB3 sdram1_dq[1] Data 1 V4 sdram1_dq[2] Data 2 AB4 sdram1_dq[3] Data 3 W3 sdram1_dq[4] Data 4 AA4 sdram1_dq[5] Data 5 W4 sdram1_dq[6] Data 6 AA3 sdram1_dq[7] Data 7 Y4 sdram1_dq[8] Data 8 Y1 sdram1_dq[9] Data 9 AA1 sdram1_dq[10] Data 10 Y2 sdram1_dq[11] Data 11 AB1 sdram1_dq[12] Data 12 AA2 sdram1_dq[13] Data 13 AC1 sdram1_dq[14] Data 14 AB2 sdram1_dq[15] Data 15 AC2 sdram1_dq[16] Data 16 AE4 sdram1_dq[17] Data 17 AF4 sdram1_dq[18] Data 18 AF3 sdram1_dq[19] Data 19 AK4 sdram1_dq[20] Data 20 AK3 sdram1_dq[21] Data 21 AC4 sdram1_dq[22] Data 22 AC3 sdram1_dq[23] Data 23 AD4 sdram1_dq[24] Data 24 AD2 sdram1_dq[25] Data 25 AE2 sdram1_dq[26] Data 26 AE1 sdram1_dq[27] Data 27 AG1 sdram1_dq[28] Data 28 AF2 sdram1_dq[29] Data 29 AL1 sdram1_dq[30] Data 30 AG2 sdram1_dq[31] Data 31 AL2 sdram1_ba[0] Bank Select 0 V6 sdram1_ba[1] Bank Select 1 AD5 sdram1_dqm[0] Write Mask0 Y3 sdram1_dqm[1] Write Mask1 W2 sdram1_dqm[2] Write Mask2 AD3 sdram1_dqm[3] Write Mask3 AD1 sdram1_csn Chip Select AB5 sdram1_rasn Row Address Strobe AH5 sdram1_casn Column Address Strobe AC6 sdram1_wen Write Enable AE5 sdram1_clk Clock AC7 sdram1_clke Clock Enable AB6 October 27,

26 Table 12 SDRAM2 Interface Pin Assignments Signal Name Description FPGA Pin # sdram2_addr[0] Address 0 T6 sdram2_addr[1] Address 1 M6 sdram2_addr[2] Address 2 L5 sdram2_addr[3] Address 3 U6 sdram2_addr[4] Address 4 M7 sdram2_addr[5] Address 5 F7 sdram2_addr[6] Address 6 L6 sdram2_addr[7] Address 7 L7 sdram2_addr[8] Address 8 N7 sdram2_addr[9] Address 9 N6 sdram2_addr[10] Address 10 N5 sdram2_addr[11] Address 11 R9 sdram2_addr[12] Address 12 P7 sdram2_addr[13] Address 13 U7 sdram2_dq[0] Data 0 M3 sdram2_dq[1] Data 1 F5 sdram2_dq[2] Data 2 N4 sdram2_dq[3] Data 3 F4 sdram2_dq[4] Data 4 M4 sdram2_dq[5] Data 5 K5 sdram2_dq[6] Data 6 L3 sdram2_dq[7] Data 7 L4 sdram2_dq[8] Data 8 H1 sdram2_dq[9] Data 9 K2 sdram2_dq[10] Data 10 J2 sdram2_dq[11] Data 11 L2 sdram2_dq[12] Data 12 K1 sdram2_dq[13] Data 13 M2 sdram2_dq[14] Data 14 L1 sdram2_dq[15] Data 15 M1 sdram2_dq[16] Data 16 R3 sdram2_dq[17] Data 17 T3 sdram2_dq[18] Data 18 T4 sdram2_dq[19] Data 19 U3 sdram2_dq[20] Data 20 U4 sdram2_dq[21] Data 21 P4 sdram2_dq[22] Data 22 N3 sdram2_dq[23] Data 23 R4 sdram2_dq[24] Data 24 N1 sdram2_dq[25] Data 25 P1 sdram2_dq[26] Data 26 P2 sdram2_dq[27] Data 27 R1 sdram2_dq[28] Data 28 R2 sdram2_dq[29] Data 29 U2 sdram2_dq[30] Data 30 T2 sdram2_dq[31] Data 31 V2 sdram2_ba[0] Bank Select 0 J7 sdram2_ba[1] Bank Select 1 R6 sdram2_dqm[0] Write Mask0 K4 sdram2_dqm[1] Write Mask1 H2 sdram2_dqm[2] Write Mask2 P3 sdram2_dqm[3] Write Mask3 N2 sdram2_csn Chip Select P5 October 27,

27 sdram2_rasn Row Address Strobe U5 sdram2_casn Column Address Strobe R7 sdram2_wen Write Enable T5 sdram2_clk Clock T7 sdram2_clke Clock Enable P6 3.5 Clock Sources The Clock Generation section of the Virtex-II Pro system board provides all necessary clocks for the PowerPC processor and the RocketIO transceivers integrated into the Virtex-II Pro FPGA. In general, the clock sources on the board are grouped into two categories, differential and singleended clock sources. The differential clock sources are primarily used by the RocketIO transceivers, while the single-ended clock sources are used by the processor section. The differential clock sources consist of: A programmable LVDS clock source providing a reference clock input to the top MGTs A pair of SMA connectors to provide a clock input to the top MGTs A programmable LVDS clock source providing a reference clock input to the bottom MGTs A pair of SMA connectors to provide a clock input to the bottom MGTs A programmable LVDS clock source providing a reference clock input for the LVDS interface An on-board 100MHz oscillator provides the system clock input to the processor section. This 100Mhz clock will be used by the Virtex-II Pro Digital Clock Managers (DCMs) to generate various processor clocks. In addition to the above clock inputs, a socket is provided on the system board that can be used to provide single ended LVTTL clock input to the FPGA via an 8 or 4-pin oscillator. The following table shows the clock sources on the Virtex-II Pro system board. The following figure shows the clock resources on the FF1152 development board. It should be noted that all sixteen global clock inputs of the Virtex-II Pro FPGA are utilized in this design. October 27,

28 SMA Connectors Programmable LVDS Clock Source SPI-4.2 RDCLKP, N From P160 Module To FPGA I/O OSC Socket From SAM SPI-4.2 TSCLK SMA Connectors H18 J18 D18 E18 D17 E17 H17 J17 Bank 0 Clock Inputs Bank 1 Clock Inputs Virtex-II Pro XC2VP20/P30-FF1152 Bank 5 Clock Inputs Bank 4 Clock Inputs AK18 AL18 AH18 AJ18 AJ17 AH17 AK17 AL17 CLK_MGT_BOT_P CLK_MGT_BOT_N SYSCLK_P SYSCLK_N P160_CLK1 CLK_100 SMA_MGT_BOT_N SMA_MGT_BOT_P CLK_MGT_TOP_N CLK_MGT_TOP_P RDCLK_P RDCLK_N FPGA_GCLK0 TSCLK SMA_MGT_TOP_N SMA_MGT_TOP_P Programmable LVDS Clock Source Programmable LVDS Clock Source From P160 Module LVTTL SMA Connectors SMA Connectors Figure 12 - Clock Sources on the FF1152 Board October 27,

29 The following table provides a brief description of each clock input to the Virtex-II Pro FPGA. Signal Name SMA_MGT_TOP_P, SMA_MGT_TOP_N SMA_MGT_BOT_P, SMA_MGT_BOT_N CLK_MGT_TOP_P, CLK_MGT_TOP_N CLK_MGT_BOT_P, CLK_MGT_BOT_N RDCLK_P, RDCLK_N SYSCLK_P, SYSCLK_N Table 13 - Clock Sources FPGA Description Pin # J17, H17 Top MGT BREFCLK2 Clock Input These clock inputs are connected to a pair of SMA connectors. User can provide clock input to the top MGTs via these connectors. The user clock input must meet the MGT clock input requirements. Refer to the RocketIO user s guide for more information on the MGT clock input requirements. AL17, AK17 Bottom MGT BREFCLK2 Clock Input These clock inputs are connected to a pair of SMA connectors. User can provide clock input to the bottom MGTs via these connectors. The user clock input must meet the MGT clock input requirements. Refer to the RocketIO user s guide for more information on the MGT clock input requirements. J18, H18 Top MGT BREFCLK Clock Input These clock inputs are connected to the output of an LVDS clock synthesizer. This programmable clock source can generate a clock frequency of 25 to 700MHz. Refer to the Programmable LVDS Clock Source section for more information. AK18, AL18 Bottom MGT BREFCLK Clock Input These clock inputs are connected to the output of an LVDS clock synthesizer. This programmable clock source can generate a clock frequency of 25 to 700MHz. Refer to the Programmable LVDS Clock Source section for more information. D18, E18 Positive and Negative Differential SPI-4.2 Receive Clock Inputs These clock inputs are connected to the LVDS receive connector on the Virtex-II Pro board. For the SPI-4.2 applications, these clock inputs are the SPI-4.2 receive clock outputs. AH18, AJ18 Positive and Negative Differential System Clock Inputs These clock inputs are connected to the output of an LVDS clock synthesizer. This programmable clock source can generate a clock frequency of 25 to 700MHz. Refer to the Programmable LVDS Clock Source section for more information. P160_CLK1 AJ17 P160 Module Clock Input This clock input is connected to the P160 connector located on the Virtex-II Pro board. CLK_100 AH17 System Clock This clock input is connected to a 100MHz LVTTL oscillator. FPGA_GCLK0 D17 LVTTL Clock Input This clock input can be configured to be connected to the SystemACE Module (SAM) clock output, P160 clock output, or the LVTTL socket on the Virtex-II Pro board. This clock configuration is described in the following section. TSCLK E17 SPI-4.2 Transmit Status Clock Input This clock input is connected to the SPI-4.2 transmit status clock output. October 27,

30 3.5.1 FPGA_GCLK0 Clock Source SAM Clock JP OSC Socket 4 3 Virtex-II Pro FPGA 2 1 FPGA I/O Pin P160 Clock Figure 13 FPGA_GCLK0 Clock Source Jumper Settings Table 14 JP25 Jumper Settings Global Clock Installed Usage Input Source Jumpers OSC Socket 3-4 Any application needing a single ended clock 3-4 and 5-6 Using the MPU interface of the SAM in applications where this interface needs to be synchronized to the OSC socket rather than the SAM clock. In this case, SAM clock is input to the SAM. P160 Clock 1-3 P160 modules needing a clock connection to the FPGA global clock input SAM Clock 3-5 Using the MPU interface of the SAM The following table shows the jumper settings for routing the P160 clock to the FPGA I/O pin when the FPGA global clock input is used by SAM or, if a connection from the OSC socket to the global clock input is needed. Table 15 Jumper Settings for Routing the P160 Clock to FPGA I/O Pin Installed Usage Jumpers 1-2 P160 clock can be routed to the FPGA I/O pin for applications where the global clock input is used by the OSC socket or the SAM clock, and the P160 clock needs to be routed to the FPGA as well. 2-4 The OSC socket can be routed to the FPGA I/O pin for applications where the global clock input is used by the P160 clock or the SAM clock, and the OSC socket needs to be routed to the FPGA as well. October 27,

31 3.5.2 Programmable LVDS Clock Sources Three programmable LVDS clock synthesizers are used on the Virtex-II Pro development board to generate reference clock input to the top MGTs, bottom MGTs, and LVDS interface. The use of this variable clock source, allows designers to prototype various interconnect technologies with different clock source requirements ICS8442 Programmable LVDS Clock Synthesizer The Virtex-II Pro development board design uses the ICS8442 LVDS clock synthesizer for generating various clock frequencies. A list of features included in the ICS8442 device are shown below. Output frequency range: 25MHz to 700MHz RMS period jitter: 2.7ps (typical) Cycle-to-cycle jitter: 27ps (typical) Output rise and fall time: 650ps (maximum) Output duty cycle: 48/52 The following figure shows a high-level block diagram of the ICS8442 programmable LVDS clock synthesizer. M[0:8] N[0:1] np_load Parallel Load S_DATA S_CLOCK S_LOAD VCO_SEL XTAL_SEL TEST_CLK MR TEST Serial Load Control Inputs ICS8442 CLKOUT0 CLKOUT1 FOUT0 nfout0 FOUT1 nfout1 XTAL1 XTAL2 Clock Input Figure 14 ICS8442 Clock Synthesizer October 27,

32 Table 16 ICS8442 Clock Synthesizer Pin Description Signal Name Direction Pull up/pull down Description M[0:4], M[6:8] Input Pull down The M divider inputs, latched on the rising edge M[5] Input Pull up of the np_load signal. N[0:1] Input Pull down The N divider inputs, latched on the rising edge of the np_load signal. TEST Output The TEST output is active during the serial mode of operations. Please refer to the datasheet for more information. MR Input Pull down Active high reset signal. S_CLOCK Input Pull down Serial interface clock input. Data is shifted into the device on the rising edge of this clock. S_DATA Input Pull down Serial interface data input. S_LOAD Input Pull down Serial interface load signal. The contents of the serial data shift register is loaded into the internal dividers on the rising edge of this signal. TEST_CLK Input Pull down Test clock input. np_load Input Pull down The rising edge of this signal is used to load the M and N divider inputs into the device. XTAL1, XTAL2 Input Crystal clock input/output XTAL_SEL Input Pull up This signal is used to select between the crystal and the TEST_CLK input to the device. When this high, crystal is selected. VCO_SEL Input Pull up This signal is used to place the internal PLL in the bypass mode. When this signal is set to low, the PLL is placed in the bypass mode. For normal operations, this signal must be set to high. FOUT0, FOUT1 Output Positive LVDS clock outputs nfout0, nfout1 Output Negative LVDS clock outputs The Input Clock Select signals of the ICS8442 can be used to provide a reference clock input to the device other than the 25MHz crystal oscillator (for test purposes). The following table shows how these Input Clock Select signals are used to generate the output clock or to test the ICS8442 device. Please refer to the ICS8442 datasheet for more information on using the TEST_CLK clock input. Table 17 Input Clock Select Signal Description VCO_SEL XTAL_SEL Reference Clock Input FOUT[0:1] 0 0 TEST_CLK TEST_CLK/N (the TEST_CLK must be between 10 and 25MHz). This mode can be used to test the ICS8442 device by routing the input clock to the outputs MHz crystal 25MHz crystal/n (This mode can be used to test the ICS8442 device by routing the 25MHz crystal clock to the outputs). 1 0 TEST_CLK ICS8442 PLL Output/N (Normal Operation) MHz crystal ICS8442 PLL Output/N (Normal Operation) October 27,

33 3.5.4 ICS8442 Clock Generation The ICS8442 output clocks are generated based on the following formula (assuming the crystal clock input is set to 25MHz): FOUT[0:1] = 25 x M/N Where 8 < M < 28 and N can take a value of 1, 2, 4, or 8. The variable M is determined by setting the binary number M[0:8] while N is set according to the following table: N[1:0] N Table 18 ICS8442 N Settings Output Clock Frequency Range (MHz) Minimum Maximum For example, to generate a 62.5MHz clock, N[1:0] will be set to 10 (it can also be set to 11 since either one will be the correct frequency range for the 62.5MHz clock) and M will be set to (decimal 10). So, from the above formula: FOUT[0:1] = 25 x 10/4 = 62.5Mhz The following table shows how the M and N values can be set to generate a clock source for a few common applications. All the values for M and N are based on the 25MHz crystal clock input to the ICS8442 device. A complete list of frequencies generated by the ICS8442 (based on a 25MHz input clock) are provided in the following sections. Table 19 Examples of the ICS8442 M and N Settings Interconnect FOUT0 and ICS8442 M and N Settings Technology FOUT1 (MHz) M8 M7 M6 M5 M4 M3 M2 M1 M0 N1 N0 Gigabit Ethernet Fiber Channel Infiniband XAUI ICS8442 Programming Modes The ICS8442 provides two different methods of programming the M and N values into the device, a Parallel Mode and a Serial Mode. In parallel mode, M and N values are programmed into the device when the np_load signal pulses low. In the serial mode, the I2C pins (S_DATA and S_CLOCK) along with the S_LOAD signal are used to shift the M and N values into the device. Please refer to the ICS8442 datasheet for more information on programming modes of loading the M and N values into the device ICS8442 M and N Settings The following figure shows how the ICS8442 programmable LVDS clock synthesizer is used on the Virtex-II Pro board. DIP switches are provided on the board for manual setting of the M and N values for each ICS8442. October 27,

34 FOUT0 nfout0 CLKOUT0 CLKOUT1 FOUT1 nfout1 SMA Connectors DIP Switch M[0:8] N[0:1] np_load Parallel Load S_DATA Virtex-II Pro FPGA S_CLOCK S_LOAD Serial Load ICS8442 VCO_SEL XTAL_SEL TEST_CLK MR TEST Control Inputs 25Mhz Figure 15 ICS8442 Clock Synthesizer Interface to the FPGA As shown in the above figure, the ICS8442 device outputs two identical LVDS clock sources. One of these clock sources can be used to provide the reference clock input to the MGTs on the Virtex-II Pro development board, while the other clock output can be used to trigger a scope during testing of the gigabit link. The second output could also be used to provide an LVDS clock source to a user board. October 27,

35 CLK_MGT_BOT_P CLK_MGT_BOT_N CONTROL CLKOUT0 CLKOUT1 CLK_MGT_BOT_P CLK_MGT_BOT_N SMA Connectors SW1 M[8:0] ICS8442 Synth #1 SW9 N1:0] 25Mhz CLK_MGT_TOP_P CLK_MGT_TOP_N CONTROL CLKOUT0 CLKOUT1 CLK_MGT_TOP_P CLK_MGT_TOP_N SMA Connectors Virtex-II Pro FPGA SW10 M[8:0] ICS8442 Synth #2 SW11 N1:0] 25Mhz SYSCLK_P SYSCLK_N CONTROL CLKOUT0 CLKOUT1 SYSCLK_P SYSCLK_N SMA Connectors SW12 M[8:0] ICS8442 Synth #3 SW13 N1:0] 25Mhz Figure 16 ICS8442 Clock Synthesizer M and N DIP Switches The following tables show the DIP switch settings for M and N selections. Please refer to Table 20 for the information on pull-up and pull-down resistors provided internal to the ICS8442 device for the M and N input signals. October 27,

36 3.3V SW1, SW2, or SW10 ON OFF M0 M1 M2 M3 M4 M5 M6 M7 M8 Synthesizer #1, #2, or #3 SW9, SW11, or SW13 ON OFF 2 1 N0 N1 Figure 17 M and N DIP Switches for the Synthesizers Table 20 DIP Switch Setting for M[8:0] Switch Position SW1, SW10, and SW2 M[8:0] OFF ON DIP1 M8 0 1 DIP2 M7 0 1 DIP3 M6 0 1 DIP4 M5 1 0 Note (1) DIP5 M4 0 1 DIP6 M3 0 1 DIP7 M2 0 1 DIP8 M1 0 1 DIP9 M0 0 1 DIP10 Unused NA NA Note(1) The polarity of M5 (DIP4) is the opposite of all other DIP switch positions. Table 21 DIP Switch Setting for N[1:0] Switch Position SW9, SW11, and SW13 N[1:0] OFF ON DIP1 N1 0 1 DIP2 N0 0 1 The following table shows a complete list of frequencies generated by the ICS8442 device based on a 25MHz crystal reference clock input. October 27,

37 Table 22 Synthesizer Clock Outputs for M and N Values M[8:0] N[1:0] FOUT[1:0] (MHz) M[8:0] N[1:0] FOUT[1:0] (MHz) (Min) (Max) October 27,

38 Table 23 FPGA Pin Assignments for the Synthesizer Interface Signal Name Virtex-II Pro Pin # Comments Bottom MGT BREFCLK Clock Input (Synthesizer #1) SYNTH1_PLOAD AD18 This input is used to load the M and N values into the synthesizer using the parallel mode configuration along with the DIP switch settings for M and N. SYNTH1_RESET AE24 This input signal resets the synthesizer. SYNTH1_SCLK AE22 This clock input is used to load the M and N values into the synthesizer using serial mode configuration. SYNTH1_SDATA AE21 Serial data input to the synthesizer for loading the M and N values. SYNTH1_SLOAD AE20 This input signal is used to load the M and N values into the synthesizer using the serial mode configuration. SYNTH1_TEST AE18 A test clock input can be provided to the synthesizer using this clock input. SYNTH1_VCOSEL AD19 This input signal can be used to bypass the PLL for test purposes. SYNTH1_XTALSEL AE19 This input signal is used to select between the test clock input and the on-board crystal as clock source to the synthesizer. SYNTH1_DOUT AK21 This output signal is used as the test clock output. Top MGT BREFCLK Clock Input (Synthesizer #2) SYNTH2_PLOAD L19 This input is used to load the M and N values into the synthesizer using the parallel mode configuration along with the DIP switch settings for M and N. SYNTH2_RESET K24 This input signal resets the synthesizer. SYNTH2_SCLK K23 This clock input is used to load the M and N values into the synthesizer using serial mode configuration. SYNTH2_SDATA K21 Serial data input to the synthesizer for loading the M and N values. SYNTH2_SLOAD K20 This input signal is used to load the M and N values into the synthesizer using the serial mode configuration. SYNTH2_TEST K18 A test clock input can be provided to the synthesizer using this clock input. SYNTH2_VCOSEL L18 This input signal can be used to bypass the PLL for test purposes. SYNTH2_XTALSEL K19 This input signal is used to select between the test clock input and the on-board crystal as clock source to the synthesizer. SYNTH2_DOUT F8 This output signal is used as the test clock output. LVDS Interface Differential System Clock Input (Synthesizer #3) SYNTH3_PLOAD V25 This input is used to load the M and N values into the synthesizer using the parallel mode configuration along with the DIP switch settings for M and N. SYNTH3_RESET Y33 This input signal resets the synthesizer. SYNTH3_SCLK AG34 This clock input is used to load the M and N values into the synthesizer using serial mode configuration. SYNTH3_SDATA AG33 Serial data input to the synthesizer for loading the M and N values. SYNTH3_SLOAD AL34 This input signal is used to load the M and N values into the synthesizer using the serial mode configuration. SYNTH3_TEST AC25 A test clock input can be provided to the synthesizer using this clock input. SYNTH3_VCOSEL V24 This input signal can be used to bypass the PLL for test purposes. October 27,