CHAPTER 1 Introduction of the tnano Board CHAPTER 2 tnano Board Architecture CHAPTER 3 Using the tnano Board... 8

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2 CONTENTS CHAPTER 1 Introduction of the tnano Board Features About the KIT Getting Help...4 CHAPTER 2 tnano Board Architecture Layout and Components Block Diagram of the tnano Board Power-up the tnano Board...7 CHAPTER 3 Using the tnano Board Configuring the Cyclone III FPGA Using tnano as a USB Blaster Cable General User Input/Output SDRAM Memory I2C Serial EEPROM Using the Expansion Header Clock Circuitry Power Supply CHAPTER 4 tnano Demonstrations System Requirements LED Blinking Read-write SDRAM Read-write EEPROM LED Breath CHAPTER 5 Appendix Revision History Copyright Statement I

3 Chapter 1 Introduction of the tnano Board The tnano board introduces a pocket-sized FPGA development platform ideally suited for prototype circuit designs where users can easily access and control different external devices. The tnano s versatile circuit design is for anyone that wants to gain experience building real digital circuits. Targeting the Altera s Cyclone III FPGA device which offers 24,624 LEs, the tnano provides a comprehensive, ready-to-use hardware platform for multiple uses. The tnano has a collection of interfaces including an external 80-pin edge connector to extend designs beyond the tnano board, on-board memory devices such as SDRAM and EEPROM, as well as general user peripheral with LEDs and push-buttons. The tnano can be entirely powered either by a USB-Blaster connection or through the external on-board pins. The tnano includes software, reference designs, and accessories required to ensure the user simple access in evaluating their tnano. 1.1 Features Figure 1-1 shows a photograph of the tnano Board. 2

4 Figure 1-1 Layout of the tnano Board The key features of the board are listed below: Featured device o Altera Cyclone III EP3C25F324C6 FPGA o 215 maximum FPGA I/O pins Configuration status and set-up elements o On-board USB-Blaster circuit for programming o Altera serial configuration device - EPCS4 Expansion header o 80-pin expansion connector provides 68 I/O pins o Two 5V power pins, two 3.3V power pins and eight ground pins Memory devices o 32MB SDRAM o 2Kb I2C EEPROM General user input/output o 8 green LEDs o 2 push-buttons 3

5 Clock system o On-board 50MHz clock oscillator 1.2 About the KIT The kit will come with the following content: tnano board Figure 1-2 shows the photograph of the tnano kit content. Figure 1-2 tnano kit package contents 1.3 Getting Help Here is information of how to get help if you encounter any problem: Terasic Technologies Tel: support@terasic.com Website: tnano.terasic.com 4

6 Chapter 2 tnano Board Architecture This chapter describes the architecture of the tnano board including block diagram and components. 2.1 Layout and Components The picture of the tnano board is shown in Figure 2-1 and Figure 2-2. It depicts the layout of the board and indicates the locations of the connectors and key components. Figure 2-1 The tnano Board PCB and component diagram (top view) ` 5

7 Figure 2-2 The tnano Board PCB and component diagram (bottom view) 2.2 Block Diagram of the tnano Board Figure 2-3 shows the block diagram of the tnano board. To provide maximum flexibility for the user, all connections are made through the Cyclone III FPGA device. Thus, the user can configure the FPGA to implement any system design. Figure 2-3 Block diagram of tnano Board 6

8 2.3 Power-up the tnano Board The tnano board comes with a preloaded configuration bit stream to demonstrate the features of the board. This bit stream also allows users to see quickly if the board is working properly. To power-up the board two options are available that is described below: 1. Connect the USB type-a male connector from the tnano board to the PC. 2. Alternatively, users can power-up the tnano board by supplying 5V to the two DC +5 (VCC5) pins of the 80-pin expansion header. For communication between the host and the tnano board, it is necessary to install the Altera USB Blaster driver software. At this point you should observe the user LEDs flashing: 7

9 Chapter 3 Using the tnano Board This section describes the detailed information of the components, connectors, and pin assignments of the tnano board. 3.1 Configuring the Cyclone III FPGA The tnano board contains a serial configuration device that stores configuration data for the Cyclone III FPGA. This configuration data is automatically loaded from the configuration device into the FPGA every time while power is applied to the board. Using the Quartus II software, it is possible to reconfigure the FPGA at any time, and it is also possible to change the non-volatile data that is stored in the serial configuration device. Both types of programming methods are described below. 1. JTAG programming: In this method of programming, named after the IEEE standards Joint Test Action Group, the configuration bit stream is downloaded directly into the Cyclone III FPGA. The FPGA will retain this configuration as long as power is applied to the board; the configuration information will be lost when the power is turned off. 2. Programming the serial configuration device: In this method, the configuration bit stream is downloaded into the Altera EPCS4 serial configuration device. It provides non-volatile storage of the bit stream, so that the information is retained even when the power supply to the tnano board is turned off. When the board s power is turned on, the configuration data in the EPCS4 device is automatically loaded into the Cyclone III FPGA. JTAG Chain on tnano Board The USB-blaster is implemented on the tnano board to provide JTAG configuration through onboard USB-to-JTAG configuration logic using a type-a USB connector, a FTDI USB 2.0 Controller, and an Altera MAX II CPLD. Current configuration will be lost when power is turned off. Using the tnano as a USB Blaster cable with the 10-pin JTAG header connected to another FPGA-based board, the on-board Cyclone III FPGA of the tnano is automatically disabled. Figure 3-1 illustrates the JTAG configuration setup. 8

10 Figure 3-1 JTAG Chain To download a configuration bit stream file into the Cyclone III FPGA, perform the following steps: Insert the type-a USB connector on the tnano directly into the PC USB port The FPGA can now be programmed through the Quartus II Programmer by selecting a configuration bit stream file with the.sof filename extension. Configuring the EPCS4 The tnano board contains an EPCS4 serial configuration device that stores configuration data for the Cyclone III device. The Cyclone III device support in-system programming of a serial configuration device using the JTAG interface via the serial flash loader design. The serial flash loader is a bridge design for the Cyclone III device that uses its JTAG interface to access the EPCS.jic file and then uses the AS interface to program the EPCS device. Figure 3-2 illustrates the programming method when adopting a serial flash loader solution. Please refer to Appendix for the basic programming instruction on the serial configuration device. 9

11 Figure 3-2 Programming a serial configuration device with serial flash loader solution 3.2 Using tnano as a USB Blaster Cable The tnano board can be used as a USB Blaster cable by establishing a connection between the 10-pin JTAG header from the tnano to the FPGA-based board. The USB Blaster cable supports JTAG and AS programming modes. Figure 3-3 presents the overall connection setup. Note once the tnano is used as a USB Blaster cable, the Cyclone III FPGA located on the tnano is automatically disabled. Figure 3-3 tnano acting as a USB Blaster cable setup with another FPGA-based board 10

12 3.3 General User Input/Output Push-buttons The tnano board contains two push-buttons shown in Figure 3-4 that allow you to interact with the Cyclone III device. Each push-button provides a high logic level or a low logic level when it is not pressed or pressed, respectively. A CPU reset push-button (KEY0) is an input to the Cyclone III device. It is intended to be the master reset signal for FPGA designs loaded into the Cyclone III device. Figure 3-4 Connections between the push-button and Cyclone III FPGA LEDs The tnano board consists of 8 green user-controllable LEDs presented in Figure 3-5 to allow status and debugging signals to be driven to the LEDs from the designs loaded into the Cyclone III device. Each LED is driven directly by the Cyclone III FPGA. The LED is turn on and off when the associated pins are driven to a high and low logic level, respectively. 11

13 Figure 3-5 Connections between the LEDs and Cyclone III FPGA 3.4 SDRAM Memory The board features a Synchronous Dynamic Random Access Memory (SDRAM) device providing 32MB with a 16-bit data lines connected to the FPGA. The chip uses 3.3V LVCMOS signaling standard. All signals are registered on the positive edge of the clocks signal, CLK. Figure 3-6 depicts its connection between the Cyclone III FPGA. Figure 3-6 Connections between FPGA and SDRAM 12

14 3.5 I2C Serial EEPROM A 2Kbit Electrically Erasable PROM (EEPROM) is equipped on the tnano which is configured through a 2-wire serial interface. The device is organized as one block of 256 x 8-bit memory. The I2C write and read address are 0xA0 and 0xA1, respectively. Figure 3-7 illustrates its connection with the Cyclone III FPGA. Figure 3-7 Connections between FPGA and EEPROM 3.6 Using the Expansion Header The tnano board provides a single 80-pin expansion header shown in Figure 3-8 that offers additional connectivity and I/Os for general purpose applications. The header connects directly to 68 pins of the Cyclone III FPGA, and also provides two DC +5 (VCC5), two DC +3.3V (VCC3P3), and eight GND pins. 13

15 Figure pin Expansion Header Arrangement 3.7 Clock Circuitry The tnano board consists of a 50 MHz oscillator clock connected directly the dedicated clock input pin of the Cyclone III FPGA. The 50MHz clock input can be use as a source clock to drive the PLL circuit. The clock distribution on the tnano board is shown in Figure

16 Figure 3-9 Block diagram of the clock distribution 3.8 Power Supply The tnano board s power is provided through the USB 5V power or the 5V VCC pins on the 80-pin edge connector. The DC voltage is then stepped down to various regulators. Power Distribution System Figure 3-10 shows the power distribution system on the tnano board. 15

17 Figure 3-10 tnano Power Distribution System 16

18 Chapter 4 tnano Demonstrations 4.1 System Requirements Make sure Quartus II and NIOS II are installed on your PC. 4.2 LED Blinking In the demonstration we will show how to control the LEDs by using the Nios II processor. Figure 4-1 shows the hardware system block diagram of this demonstration. The System requires a 50MHz clock provided by the board. The PIO pins are connected to the LEDs. The Nios II processor controls the PIO ports by reading and writing to the register map. For the PIO, there are four registers: data, direction, interruptmask, and edgecapture. To turn the LED on and off, the application writes to the PIO data register. The Nios II program is running in the on-chip memory. Figure 4-1 Block diagram of the LED blinking demonstration Demonstration Source Code 17

19 Project directory: tnano_led Bit stream used: tnano_led.sof Nios II Workspace: tnano_led\software Demonstration Batch File Demo Batch File Folder: tnano_led \demo_batch The demo batch file includes the following files: Batch File: tnano_led.bat, tnano_led_bashrc FPGA Configure File: tnano_led.sof Nios II Program: tnano_led.elf Demonstration Setup Make sure Quartus II and Nios II are installed on your PC. Power on the tnano board by connecting the USB port to PC and install USB Blaster driver if necessary. Execute the demo batch file tnano_led.bat under the batch file folder, tnano_led\demo_batch. After Nios II program is downloaded and executed successfully, a prompt message will be displayed in nios2-terminal, as shown in Figure 4-2. You will see the LEDs blink. Figure 4-2 Display prompt message for the LED blinking demonstration 18

20 4.3 Read-write SDRAM Many applications use SDRAM as temporary storage. The tnano board provides the hardware and software designs for accessing SDRAM. In this demonstration, we show how to use Altera s SDRAM IP to build SDRAM controller, and how to use NIOS processor to read and write the SDRAM for hardware verification. Figure 4-3 shows the hardware system block diagram of this demonstration. The System requires a 50MHz clock provided by the board. The PLL generates a 100MHz clock for Nios II processor and the other controllers. The Nios II program is running in the on-chip memory. Figure 4-3 Block diagram of the Read-write SDRAM demonstration The system flow is controlled by a Nios program. First, the Nios program writes 10-Bytes data into the specified address of SDRAM by the pointer assignment. Then, it calls Nios system function, alt_dache_flush_all, to make sure all data has been written to SDRAM. Finally, it uses the pointer to read data from SDRAM. The program will show process in JTAG-Terminal when writing/reading data to/from the SDRAM. SDRAM Parameter settings Figure 4-4 shows memory settings for SDRAM Controller. 19

21 Figure 4-4 Memory settings in SDRAM Controller Demonstration Source Code Project directory: tnano_sdram Bit stream used: tnano_sdram.sof Nios II Workspace: tnano_sdram\software 20

22 Demonstration Batch File Demo Batch File Folder: tnano_sdram \demo_batch The demo batch file includes the following files: Batch File: tnano_sdram.bat, tnano_sdram _bashrc FPGA Configure File: tnano_sdram.sof Nios II Program: tnano_sdram.elf Demonstration Setup Make sure Quartus II and Nios II are installed on your PC. Power on the tnano board by connecting the USB port to PC and install USB Blaster driver if necessary. Execute the demo batch file tnano_sdram.bat under the batch file folder, tnano_sdram\demo_batch. After Nios II program is downloaded and executed successfully, a prompt message will be displayed in nios2-terminal. The program will display read-write progress, as shown in Figure 4-5. Figure 4-5 Display read-write progress for the Read-write SDRAM demonstration 4.4 Read-write EEPROM This demonstration shows how to read or write data from EEPROM by I 2 C serial interface. Figure 4-6 shows the hardware system block diagram of this demonstration. The System requires a 50MHz clock provided by the board. Two PIO pins are connected to the I 2 C bus, one of which is 21

23 used for serial clock and the other is used for serial address/data I/O. The I 2 C protocol is implemented by software. The Nios II program is running in the on-chip memory. Figure 4-6 Block diagram of the Read-write EEPROM demonstration Demonstration Source Code Project directory: tnano_eeprom Bit stream used: tnano_eeprom.sof Nios II Workspace: tnano_eeprom\software Demonstration Batch File Demo Batch File Folder: tnano_eeprom \demo_batch The demo batch file includes the following files: Batch File: tnano_eeprom.bat, tnano_eeprom _bashrc FPGA Configure File: tnano_eeprom.sof Nios II Program: tnano_eeprom.elf 22

24 Demonstration Setup Make sure Quartus II and Nios II are installed on your PC. Power on the tnano board by connecting the USB port to PC and install USB Blaster driver if necessary. Execute the demo batch file tnano_eeprom.bat under the batch file folder, tnano_eeprom\demo_batch. After Nios II program is downloaded and executed successfully, a prompt message will be displayed in nios2-terminal. The program will display read-write progress, as shown in Figure 4-7 Figure 4-7 Display read-write progress for the Read-write EEPROM demonstration 4.5 LED Breath The demonstration shows how to use FPGA for controlling the luminance of LEDs by means of PWM scheme.there are two groups of LEDs, while one group dims the other group light up, vice versa. The behavior of this action just like 'human breath'. Users could change the PWM wave's duty ratio and frequency to control the LED luminance and repetition rate. Figure 4-8 Shows a diagram of PWM signals to drive LED. 23

25 Figure 4-9 Pulse Width Modulation Figure 4-9 shows the relationship between duty cycle and LED luminance. Demonstration Source Code Project directory: tnano_default Bit stream used: tnano_ Default.sof Demonstration Batch File Demo Batch File Folder: tnano_ Default\demo_batch The demo batch file includes the following files: FPGA Configure File: tnano_ Default.sof Demonstration Setup Make sure Quartus II and Nios II are installed on your PC. Connect USB cable to the tnano board and install USB Blaster driver if necessary. Execute the demo batch file tnano_ Default.bat under the batch file folder, tnano_ Default \demo_batch. 24

26 Chapter 5 Appendix 5.1 Appendix A Programming the Serial Configuration Device This appendix describes how to program the serial configuration device with Serial Flash Loader (SFL) function via the JTAG interface. User can program serial configuration devices with a JTAG indirect configuration (.jic) file. To generate JIC programming files with the Quartus II software, users need to generate a user-specified SRAM object file (.sof), which is the input file first. Next, users need to convert the SOF to a JIC file. To convert a SOF to a JIC file in Quartus II software, follow these steps: Convert SOF to JIC 1. Choose Convert Programming Files (File menu). 2. In the Convert Programming Files dialog box, scroll to the JTAG Indirect Configuration File (.jic) from the Programming file type field. 3. In the Configuration device field, specify the targeted serial configuration device (please select EPCS4). 4. In the File name field, browse to the target directory and specify an output file name. 5. Highlight the SOF data in the Input files to convert section. See Figure A1. 6. Click Add File. 7. Select the SOF that you want to convert to a JIC file. 8. Click Open. 9. Highlight the Flash Loader and click Add Device. See Figure A2. 25

27 10. Click OK. The Select Devices page displays. Figure A1 Convert Programming Files Dialog Box 26

28 Figure A2 Highlight Flash Loader 11. Select the targeted FPGA that you are using to program the serial configuration device. See Figure A Click OK. The Convert Programming Files page displays. See Figure A Select the.sof file, and Click the Properties. Select Compression, click OK See Figure A Click Generate. 27

29 Figure A3 Select Devices Page 28

30 Figure A4. Convert Programming Files Page 29

31 Figure A5 Compression the sof file Write JIC File into Serial Configuration Device To program the serial configuration device with the JIC file that you just created, add the file to the Quartus II Programmer window and follow the steps: 1. When the SOF-to-JIC file conversion is complete, add the JIC file to the Quartus II Programmer window: i. Choose Programmer (Tools menu). The Chain1.cdf window displays. ii. Click Add File. From the Select Programming File page, browse to the JIC file. iii. Click Open. 30

32 2. Program the serial configuration device by checking the corresponding Program/Configure box, a Factory default SFL image will be load (See Figure A6). Figure A6. Quartus II programmer window with one JIC file 3. Click Start to program serial configuration device. Erase the Serial Configuration Device To erase the existed file in the serial configuration device, follow the steps listed below: 1. Choose Programmer (Tools menu). The Chain1.cdf window displays. 2. Click Add File. From the Select Programming File page, browse to a JIC file. 3. Click Open. 4. Erase the serial configuration device by checking the corresponding Erase box, a Factory default SFL image will be load (See Figure A7). 31

33 Figure A7 Erasing setting in Quartus II programmer window 5. Click Start to erase the serial configuration device. 5.2 Revision History Version V1.0.0 V1.1.0 Change Log Initial Version (Preliminary) Add appendix 5.3 Copyright Statement Copyright 2010 Terasic Technologies. All rights reserved. 32