Hardware NVMe implementation on cache and storage systems

Transcription

1 Hardware NVMe implementation on cache and storage systems Jerome Gaysse, IP-Maker Santa Clara, CA 1

2 Agenda Hardware architecture NVMe for storage NVMe for cache/application accelerator NVMe for new NVM Santa Clara, CA 2

3 Why NVMe for Data Center? Intensive applications Database Virtualization Big Data Analytics Data Center requirements More performances (latency, IOPS) Higher memory capacity Non-volatile capabilities Lower power consumption IP-Maker makes the bridge Emerging technologies NandFlash New memories (MRAM/RRAM) New interfaces (NVMe) PCIe SSD for Storage Application acceleration Santa Clara, CA 3

4 NVMe SSD controller architecture SSD Controller Flexibility support NVMe firmware Embedded processor Optional IPM-NVMe PCIe Interface Automatic Command Processing Nandflash Controller ECC BCH NandFlash IOPS acceleration Low latency Controller Santa Clara, CA 4

5 Hardware NVMe IP architecture Low latency with the automatic command processing IOPS acceleration with the multi-channel Configuration & System Automatic Command Processing AXI Configuration Registers Queue Context Manager Queue Arbiter AXI Embedded Processor PCIe Interface Async Event Error Logs Command Manager AXI Multi-Channel Read s Write s AXI Data Interface Santa Clara, CA 5

6 FPGA-Based reference design Gen2 x4 configuration performances: IOPS: 350k Latency: 12µs Host Device PCIe hard IP controller soft IP NVMe Linux driver IPM-NVMe CPU PCIe Interface Bridge Automatic Command Processing Bridge 3 Controller 3 7-series Xilinx FPGA 7-series Xilinx evaluation kit Santa Clara, CA 6

7 How many kiops for a Gen2 x4? Lane speed is 5 Gb/s => 20 Gb/s But, => 610kIOPS max? 8/10bit coding => 499kIOPS max of data PCIe overhead (CRC ): 24B for a 256B payload => 446kIOPS max of useful data 90% bus use => 400kIOPS max And other Santa Clara, CA 7

8 What is the latency for a Gen2 x4? 4µs for the host driver 8µs for all PCIe transactions Less than 0.1µs for the NVMe command processing 2- NVMe command ready CPU 1-Host driver Setup PCIe root complex 3- NVMe command submission fetch PCIe Phy + Ctrl NVMe IP 4- Data transfer 5- NVMe command executed Santa Clara, CA 8

9 NVMe for storage Hardware NVMe for high performance Firmware NVMe for command flexibility Host NVMe Linux driver SSD Controller NVMe firmware Embedded processor IPM-NVMe CPU PCIe Interface Automatic Command Processing Nandflash Controller ECC BCH NandFlash Controller Santa Clara, CA 9

10 NVMe for application acceleration Hardware NVMe for high performance No need of flexibility: just performance CPU for NandFlash management Host SSD Controller NVMe Linux driver Embedded processor IPM-NVMe CPU PCIe Interface Automatic Command Processing Nandflash Controller ECC BCH NandFlash Controller Santa Clara, CA 10

11 NVMe for new NVM (MRAM, RRAM) Simplified architecture Lower latency Host SSD Controller NVMe Linux driver IPM-NVMe CPU PCIe Interface Automatic Command Processing NVM Controller NVM Santa Clara, CA 11

12 Latency with different memories Flash Memory Summit 2013, Amber Hufflan, Intel Santa Clara, CA 12

13 Summary Benefits of a hardware NVMe architecture: Ultra low latency with hardware acceleration for NVMe command processing High IOPS with integrated multi-channel s High memory capacity with scalable design New NVM capabilities Low power consumption thanks to hardware acceleration Santa Clara, CA 13

14 Thanks! Visit IP-Maker booth #619 NVMe live demo! Jerome Gaysse Business Development Manager Santa Clara, CA 14