Versatile RRAM Technology and Applications

Transcription

1 Versatile RRAM Technology and Applications Hagop Nazarian Co-Founder and VP of Engineering, Crossbar Inc. Santa Clara, CA 1

2 Agenda Overview of RRAM Technology RRAM for Embedded Memory Mass Storage Memory Storage Class Memory FPGA Configuration, NVRAM, State Retainer Monolithic system integration Santa Clara, CA 2

3 Crossbar s RRAM Technology Simple device structure using fab friendly materials and process Information is stored in the form of metallic nano-filament in a non-conductive layer Filamentary-based switching by electric field Program/set Reading a programmed cell Reset Reading an erased cell LOW RESISTANCE (LRS or ON) HIGH RESISTANCE (HRS or OFF) Santa Clara, CA 3

4 Crossbar RRAM Cell Crossbar Technology Crossbar Selector Crossbar SR Cell Normalized Current R Normalized Current + = S Normalized Current R S Suited for low latency, high speed embedded memory Suited for high density high performance NAND or SCM memory Santa Clara, CA 4

5 Scaling Improves Crossbar RRAM Roff Ron Scaling RRAM device Roff increases by 1 CCCCCCCC AAAAAAAA Ron Stays nearly constant Roff/Ron ratio improves Sensing window improves Improves BER Provides additional margin for MLC/TLC r = 40nm Ioff=1uA Roff=1MΩ r = 20nm Ioff=0.25uA Roff=4MΩ r = 10nm Ioff=62nA Roff=16MΩ Santa Clara, CA 5

6 Benefits of Crossbar Embedded RRAM CMOS + RRAM No Change to Front-end CMOS CMOS + e-flash Major changes to Front-end Complex cell High voltage transistors Adds 6+ Masks & 40 steps Santa Clara, CA 6

7 Benefits of Crossbar Embedded RRAM Back-end process minimum impact RRAM located between metal layers Adds only 2 masks & 8 steps 32% lower cost Smaller die size 1T1R RRAM 1P9M Santa Clara, CA 7

8 Advantages of RRAM for Embedded Memory Scales with advanced nodes Reduced Manufacturing Complexity Cost Performance CMOS compatible material Back-end process - No change in front-end Reduced masking steps Byte/Page Alterability Write operation no need for block erase Santa Clara, CA 8

9 RRAM for Mass Storage Performance Latency reduction Byte/Page alterability Smaller page sizes Write - no need for block erase Superior endurance & retention Density and Scalability 3D crosspoint array stackable at advanced nodes Utilizes standard CMOS process Mass storage available to Fabless companies Santa Clara, CA 9

10 Crossbar Memory Byte/Page Alterability Demonstration CROSSBAR RRAM Byte Alteration (µs) CROSSBAR RRAM RRAM Based System byte alteration within µseconds RRAM Device NAND FLASH 2) Block Erase (ms) NAND or NOR FLASH device NAND FLASH 1) Copy to DRAM NAND FLASH 3) Byte Alteration NAND FLASH 4) Program to Flash ~100 of ms DRAM device NAND and NOR Flash Based System byte alteration within 100s of ms Santa Clara, CA

11 NAND-Based RRAM-Based Storage Card Services 150K transactions per second Responds to single transaction within 150us Nand Memories are Replaced with RRAM Services 20X More Transactions Memory Controller Bit-Error Rate Requirement Decreases Dramatically RRAM NANDBank Memory RRAM Memory Chip Responds to Transactions 30X Faster HOST HOST Interface CTRL Buffer ECC RRAM NAND I/F RRAM NANDBank Memory RRAM Memory Chip Performance Increases Substantially Configuration Command Status Small Buffer due to Very Fast Program and Read time CPU ROM RAM Small CPU due to Simplicity of Managing RRAMs NAND NANDBank Memory RRAM Memory Chip RRAM NAND NANDBank Memory RRAM Memory Chip RRAM Santa Clara, CA 11

12 Crossbar Patented IP Libraries FPGA Configuration Bit NVRAM Vdd WL WL BL D DN BLN Combinational Logic (MUX, LUT etc..) GND State Retainer Instant On Eliminates external non-volatile memory DFF D Q CLK RST W RRAM R RRAM IN OUT Combinational Logic DFF D Q CLK RST Santa Clara, CA Stores data at power down Recalls at power up Power saving 12

13 RRAM for FPGA Configuration Bits, NVRAM, State Retainer Major Advantages: NV Configuration bit Area reduction Performance improvement Power reduction Instant on No need for external non-volatile memory Embedded non-volatile memory for data/code/storage Santa Clara, CA 13

14 RRAM for Monolithic Integration Mass Storage NVRAM 45bit 40bit Data Memory-NOR DRAM Config Code Memory 17bit Mass Storage-NAND Power up/down Data Memory CPU + SRAM 6bit Code Memory-SPI Elimination of large number of I/Os, and simplification of the external interface Reduction of components Power reduction due to elimination of large number of I/O Breakthrough performance Direct wide bus connection between memory and CPU/peripheral devices Crossbar technology = True high performance integrated system Santa Clara, CA 14

15 Monolithic Integration of NVMemory with Crossbar RRAM Crossbar RRAM Technology Enables Monolithic integration of: Embedded memory with 1T1R SCM with 1T1R or 1TnR Mass storage with 1TnR FPGA configurable logic, CPU with 1T1R Code/Config/ NVRAM Memory Mass Storage Memory M4 Periphery M3 M2 M1 Periphery Santa Clara, CA

16 Crossbar Unique RRAM Versatile Technology Monolithic integration of Storage, Code, Data, FPGA configuration bit memories in one silicon Breakthrough system performance enabled with the monolithic integration of various memory architectures Fabless companies access IPs for a complete memory solution (storage, code, data, and FPGA configuration) from CMOS foundries Santa Clara, CA 16

17 Ready for Business Crossbar RRAM 300mm Wafer Crossbar RRAM Die Santa Clara, CA 17

18 Crossbar-inc.com Santa Clara, CA 18