IBM eserver pseries 690+: High-End Unix Server

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1 Ian Brown Product Report 6 August 2003 IBM eserver pseries 690+: High-End Unix Server Summary The p690+ is IBM s most powerful Unix server. It offers excellent performance and reliability, but POWER4 has limited longevity. Its successor, POWER5, which is slated for 2004, is not pin-compatible. Table of Contents Overview Analysis Pricing Competitors Strengths Limitations Recommended Gartner Research Insight List Of Tables Table 1: Capacities: IBM pseries 690 Table 2: Overview: IBM eserver pseries 690 Table 3: High-Availability Features: IBM eserver pseries 690 Table 4: Unix Clustering Software Table 5: Performance Comparisons: SAP SD Table 6: Price List: IBM eserver pseries 690 Table 7: Competitive Comparison: IBM eserver pseries 690 List Of Figures Figure 1: POWER4 Chip Structure Figure 2: Multichip Module (MCM) Gartner Reproduction of this publication in any form without prior written permission is forbidden. The information contained herein has been obtained from sources believed to be reliable. Gartner disclaims all warranties as to the accuracy, completeness or adequacy of such information. Gartner shall have no liability for errors, omissions or inadequacies in the information contained herein or for interpretations thereof. The reader assumes sole responsibility for the selection of these materials to achieve its intended results. The opinions expressed herein are subject to change without notice.

2 Corporate Headquarters IBM Old Orchard Road Armonk, NY 10504, U.S.A. Tel: Fax: Internet: Overview Announcement Summary The IBM eserver pseries 690 (p690) was announced in October In May 2003, IBM refreshed the product. The enhanced version is known as the p690+. The May 2003 improvements included: Faster 1.5GHz and 1.7GHz POWER4+ processors Maximum memory capacity doubled to 512GB and faster memory for the fastest processors New Capacity Upgrade On Demand and on/off Capacity On Demand options A faster remote I/O (RIO2) interconnect with 2.75x more bandwidth than the previous version New Peripheral Component Interconnect Extended (PCI-X) I/O planars for the I/O drawers Maximum number of logical partitions (LPARs) doubled to 32 Just prior to the announcement of the POWER4+-based models, IBM cut the prices of the p690 and p670 central electronic complexes (CEC) the chassis that house the main system electronics by around 35 percent. This and reductions in the price of memory, brought the overall list prices for typical 1.1- and 1.3GHz POWER4 configurations down by around 30 percent. At the same time, IBM also introduced upgrades enabling customers to convert their pseries 670 (p670) systems to p690 configurations. (The p670/p670+ is a midrange system that has a similar design to the p690/p690+, but is only available in up to 16-way configurations.) Overview Like the HP Superdome, Sun F15K and Fujitsu PRIMPOWER XA servers, the p690 is a large framebased multiprocessor Unix server. It differs from the other high-end Unix servers in a number of ways, however. Unlike the HP, Sun and Fujitsu machines, it is not based around CPU/memory modules or cells with discrete connections to a central switch. For a start, each of the POWER4/4+ microprocessors has a dual-processor core. IBM was the first vendor to offer a dual-core chip architecture for computers symmetric multiprocessing (SMP) on a chip. In addition to the microprocessor cores, each POWER4/4+ chip includes: Shared Level 2 (L2) cache memory. The microprocessor interface unit, which interfaces each microprocessor to the rest of the system. 6 August

3 The directory and cache controller for the off-chip Level 3 (L3) caches. The fabric bus controller, which is the basis of the system s internal interconnect. A GX bus controller that provides the interconnection between each POWER4 chip and the RIO hub and which can also be used as a cluster interconnect. The figure below illustrates the layout of the dual-core POWER4 chips. Figure 1: POWER4 Chip Structure Source: IBM Corp. This highly integrated architecture is claimed to offer greater reliability than traditional boards and interconnects. The single-core chips originally used for the high-performance HPC versions of the p690 have been dropped for POWER4+, but IBM now markets the pseries 655 (p655) nodes which are designed for use in high-performance clusters. The p655 supports four- or eight-way versions of the POWER4+ MultiChip 6 August

4 Modules (MCMs) and is intended for compute-intensive scientific and technical or business intelligence workloads. MultiChip Modules Groups of four POWER4 microprocessors are integrated into MCMs. Each of the MCMs measures just 4.5 square inches or 11.5 square centimeters. These eight-way SMP MCMs are the p690 s basic building block. They plug directly into the system s backplane. As well as including the buses that provide connections between the four microprocessors, the MCM also provides the bus interconnects to other MCMs, to the I/O subsystem and to a separate off-chip L3 cache memory for each of the four microprocessors on the MCM. Each L3 cache in turn connects to a memory controller and main memory (see the illustration of the MCM below). Up to four MCMs can be installed in a p690, giving a range of configurations from eight- to 32-way in increments of eight-way when MCMs are physically added to the system. Capacity Upgrade on Demand (see below) allows for smaller incremental two-way upgrades. Figure 2: Multichip Module (MCM) Source: IBM Corp. The number of MCMs installed determines the amount of memory and the number of I/O ports that can be supported. As the p690 s basic building block is the MCM, each additional MCM means additional memory books, and I/O drawers can be added, as the table below indicates. Table 1: Capacities: IBM pseries 690 Number of MCMs SMP (n-way) Memory Capacity Max. I/O Drawers Max. PCI Slots GB GB GB GB August

5 System and I/O bandwidth also scale with the microprocessor frequency: chip-to-chip, MCM-to-MCM buses, and the system backplane operate at half the frequency of the microprocessors. The I/O bus that connects the MCMs to the RIO/RIO2 hubs operates at one-third the microprocessor frequency, as does the L3 cache-to-main memory bus. This is unusual. With other high-end reduced instruction set computer (RISC)/Unix servers, such as the Sun, HP and Fujitsu servers already mentioned, the speed of the backplane and system interconnect is fixed independently of the speed of the processors. In the IBM design, however, the faster the microprocessors, the higher the overall throughput of the system. The intention is to provide balanced system scaling. IBM doesn t publish figures for the bandwidths of the chip-to-chip or MCM-to-MCM interconnects. There are six 16-byte chip-to-chip buses linking the POWER4 microprocessors on each module and two 8-byte MCM-to-MCM buses. These buses operate at half the processor frequency, so the chip-to-chip bus bandwidth on a single MCM ranges from 52.8GB/second for the 1.1GHz processors ((16 x (1.1/2)) x 6) to 81.6GB/second for the 1.7GHz processors ((16 x (1.7/2)) x 6). The MCM-to-MCM bus bandwidth ranges from 8.8GB/second for the 1.1GHz processors ((8 x (1.1/2)) x 2) to 13.6GB/second for the 1.7GHz processors ((8 x (1.7/2)) x 2). If we take the aggregate bandwidth for four MCM-to-MCM buses, one for each microprocessor in an MCM, that gives a system interconnect bandwidth ranging from to 54.4GB/second. Again, unlike other system designs, the MCM-to-MCM buses are arranged in a loop rather than based around a central switch with discrete point-to-point connections. NUMA or Not? The p690 s main memory modules (they re actually like books encased in steel covers) are separate from the MCMs. They re not mounted together with the microprocessors on cell boards as they are in the Sun F15K and HP Superdome, for example. The memory cards are directly linked to individual MCMs via integrated memory controllers, and so memory access is not completely uniform across the system interconnect. Technically, therefore, we d say the p690 has a nonuniform memory access (NUMA) architecture, albeit one with very little difference in memory latencies between local and remote memory accesses. According to IBM, differences in latency between accesses to local and remote caches and main memory on the p690 are typically between 15 percent and 26 percent, compared with differences of between 50 percent and 150 percent on more traditional cache-coherent NUMA (ccnuma) designs. This means that the p690 system design looks to all intents and purposes like a pure SMP system to the system software and to applications. Memory capacity has been doubled with the announcement of the POWER4+ models and the availability of 64GB memory cards. IBM is also offering faster memory, clocked at 567MHz (standard memory is 500MHz). The faster memory is supported on all p690 processors, but IBM specifically recommends its use with the 1.7GHz POWER4+ processors. The 567MHz memory modules are priced the same as 500MHz modules. Memory capacity now ranges from 8GB to 512GB for both the p690 and p690+. New I/O Drawers There are now two I/O planar options for the IBM D I/O drawers: a new high-performance RIO-2 to PCI-X I/O planar or the RIO to PCI I/O planar as used on the original p690. The minimum I/O configuration for the p690/p690+ includes a base I/O book, a single 1U-high (1U equals 1.75 inches) media drawer and one D 4U-high I/O drawer. The base I/O book contains the service processor and supports one or two D I/O drawers. Maximum I/O configuration is either seven or eight drawers depending on the RIO cabling, the number of MCMs and the number of RIO2 I/O books installed. The D drawers contain two PCI I/O planars each with ten 64-bit PCI-X slots and two integrated Ultra3 Small Computer Systems Interface (SCSI) controllers (for devices in the media drawer and disks in 6 August

6 the I/O drawers). All of the I/O adapter slots support both PCI and PCI-X. Each I/O planar has either two RIO or two RIO2 ports. The RIO2 interfaces double the connection speed for the I/O drawers by incorporating full duplex loops operating at up to 1GHz. One RIO or RIO2 port of each planar is always connected to a RIO2 port on an I/O book in the CEC. The other RIO or RIO2 port can also connect to an RIO2 port on an I/O book or can be connected to the other I/O planar for redundancy. Single or dual loops are supported for extra bandwidth and redundancy. The I/O bandwidth of the p690/p690+ scales with the number of drawers attached. The more MCMs supported, the more I/O books can be supported and the greater the aggregate bandwidth. The new RIO2 planars support high-performance adapters in every slot and provide nearly three times more I/O throughput per I/O drawer than the older RIO planars. Using the new RIO2 hubs and I/O drawer planars, the maximum aggregate I/O bandwidth for the (1.7GHz) p690+ Turbo servers is now 44GB/second, compared with 16GB/second for the (1.3GHz) POWER4-based p690 Turbo. High-Availability Features The p690 includes a number of features designed to improve reliability, availability and serviceability (RAS). They include mainframe-like power and cooling, extensive memory error detection, correction and avoidance, and a system infrastructure designed to monitor and log hardware and operating system errors or failures in real time and to initiate recovery and service actions in response to such events. First Failure Data Capture automatically logs and stores a record of internal error check states at the time of a system failure. This eliminates the need for the time-consuming re-creation of error states to replicate the failure. Other RAS features are indicated in the High-Availability Features table below. Capacity on Demand Also new with the POWER4+-based models, IBM has announced temporary or On/Off Capacity on Demand (OOCOD). This complements Capacity Upgrade on Demand (CUOD), which allows customers to permanently switch on additional processors and installed but inactive memory to meet increasing capacity demands. On/Off COD provides customers with the option of temporarily switching on additional processors to meet temporary increases in capacity requirements. The OOCOD feature allows customers to have 60 days of additional processor usage. They must activate processors in pairs, but they may activate as many processors as they like for a total usage of 60 processor days. Customers may also purchase multiple On/Off features. Planned availability for On/Off COD is set for 26 September All pseries servers now come with Trial Capacity on Demand, which enables customers to activate standby CUOD processors or memory on a one-off trial basis for 30 days the 30-day trial is separate for memory and processors. Customers receive the keys to unlock their inactive capacity, so the trial can be used for testing or to meet an increase in workload. This is designed to allow customers time to determine if they want to permanently or temporarily activate processors. In addition, IBM resets the processor 30- day trial after a customer permanently activates a pair of processors. Table 2: Overview: IBM eserver pseries 690 Product Type Enterprise-class Unix servers Form Factor 24-inch/61-cm wide system rack; 42U* high General Availability POWER4+ Models: 30 May 2003 System Architecture SMP/ lightweight NUMA Microprocessor POWER4 or POWER4+ dual-core RISC microprocessor Options 1.1/1.3/1.5/1.7GHz 6 August

7 Table 2: Overview: IBM eserver pseries 690 Caches Level 1: 32KB/64KB per microprocessor Level 2: 1.5MB (POWER4+) or 1.4MB (POWER4) per chip (1) Level 3: 128MB per MultiChip Module No.ofCPUs 8, 16, 24 or 32 Supported System Memory 8GB-512GB Available I/O Slots PCI (64-bit) or PCI-X Integrated/Bundled Four Ultra3 SCSI controllers per I/O drawer (two per planar) Controllers Removable Media 4/Up to128 Bays/Disk Bays Hard Disk Options 18.2GB, 36.4GB, 73.4GB and 146.8GB Max. Disk Capacity 18.7TB (integrated with I/O Drawers) Operating Systems Advanced Interactive Executive (AIX) 5L version (5.1); SuSE Linux Enterprise Supported (earliest Server 8 (runs in LPARs only) release) Max. No. of 32 (one per CPU) Partitions Capacity on Demand Yes (permanent); temporary activation will also be available from September 2003 (COD) (2) Transaction 763, US$8.31/tpmC (3) Processing Performance Council Benchmark C (TPC- C) v.5 Transaction per Minute Entry Price (US$) p690: $343,056 p690+: $489,386 (4) Standard Warranty One-year hardware; one-year of Software Maintenance for AIX Operating Systems (SWMA) also included *Rack unit (U) equal to 1.75 inches. (1) Shared between two microprocessor cores. (2) Temporary activation (OOCOD) will be available for processors only; permanent activation (CUOD) covers inactive processors and memory. CUOD processors and memory and OOCOD processors need to be specified at initial configuration. (3) Server configuration: 32 x 1.7GHz POWER4+ microprocessors with 128MB L3 cache memory per MCM; 512GB of main memory; AIX 5L V5.2 operating system; IBM DB2 UDB 8.1 database management system. Availability date: 8 November (4) See Pricing section below for configuration details. Table 3: High-Availability Features: IBM eserver pseries 690 Feature Supported/Not Supported Hot-Plug System No Boards Hot CPU Upgrades No Hot-Spare CPUs Yes (1) 6 August

8 Table 3: High-Availability Features: IBM eserver pseries 690 Feature Supported/Not Supported Memory Protection Chipkill error correction CODe (ECC) memory (see Additional Features entry and Recovery below), soft memory scrubbing, redundant bit steering Internal Hot- Yes Pluggable Disks Hot-Plug PCI I/O Yes (2) Redundant N+1 Yes Power Hot-Swap Power Yes Supplies Redundant N+1 Yes Cooling Hot-Swap Cooling Yes Redundant Array of Option available Independent Disks (RAID) Controller Mirrored System Yes Disks Redundant Network Yes Interface Controllers I/O Multipathing Yes Deconfiguration of Yes (CPU, caches, memory chips, I/O adapters) Failed Components at Boot Auto Reboot and OS Yes Restart System-Independent Yes, service processor provides surveillance of system operation Service Processor 6 August

9 Table 3: High-Availability Features: IBM eserver pseries 690 Feature Supported/Not Supported Additional Features First Failure Data Capture: Specialized hardware captures failure data automatically at time of failure. Service History Logs: Log 5,000 points on the system. Chipkill Memory: Distributes memory bits across separate memory chips so that if any chip fails, data can be reconstructed from the remaining chips, and the system can continue processing. Bit Steering: Allows memory lines from a spare memory chip to be dynamically reassigned to a memory module with a faulty line to keep the system running. Dynamic Processor Deallocation: Monitors CPUs against a threshold of recoverable errors; if the threshold is reached, the processor will be marked and AIX will attempt to deconfigure it from the system (customer-enabled option). Dynamic Processor Sparing: System can activate an inactive (CUOD) processor if a processor is sensed to be failing. The feature works in conjunction with Dynamic Processor Deallocation. PCI Bus Error Recovery: Allows transparent recovery of intermittent PCI bus parity errors and graceful transition of the faulty I/O device to an unavailable state. AIX device drivers must be written to the PCI Extended Error Handling (EEH) standard. Service Focal Point (SFP): Provides error filtering, extended error data gathering and call-home capabilities; runs on Hardware Management Console (HMC) and collects and logs data from the service processor (hardware) and from AIX. Service Agent: Consists of two parts one resides on AIX and monitors and analyzes all recoverable system failures; the other part is part of the SFP software and is part of the automatic call-home capability. Internal Battery Feature (IBF): Designed to maintain system operation during brown-out conditions. (1) Requires inactive CUOD processors to be installed and available, and requires AIX 5L v.5.2 and dynamic LPAR (DLPAR) functionality to be configured. An inactive processor is transparently activated if a failing processor reaches a pre-determined error threshold. If the failing processor is not detected prior to failure or if the system is not using DLPAR, then a re-boot of the system will activate an alternative processor from the inactive spares. (2) Replacement or new PCI cards must have the same field-replaceable unit (FRU) part number as an existing PCI card in the system. Table 4: Unix Clustering Software Name/Latest Version HACMP v.5 Number of Nodes 2-32 Supported for Failover Type(s) of Clustering Failover, workload distribution, concurrent processing (using Oracle Parallel Server); additional disaster recovery option (HACMP/XD) (1) Interconnects Ethernet, FDDI, Token Ring, Fibre Channel, X.25, RS-232 (heartbeat network) Supported Types of Nodes Supports a range of different SMP or uniprocessor AIX nodes from pseries, Cluster Supported 1600 and RS/6000 product lines 6 August

10 Table 4: Unix Clustering Software Clusterwide File System Single Event Manager Consolidated Management Station Disaster Recovery Support Option Optional (General Parallel File System) Yes Yes Yes: HACMP/XD (1) (1) Planned availability of HACMP/XD is 17 October Until then, the HAGEO option is available with HACMP v.4.x. Analysis The p690 has been a very successful product for IBM, with sales of over 2,000 units in What s the attraction? Performance it s very scalable. No one questions either IBM s or the POWER processor s viability. The pseries is No. 3 in the RISC/Unix market, but growing strongly. There are issues, of course: The p690 s LPARs offer good granularity, but they lack the electrical isolation of hard partitions. Does IBM intend to replace AIX with a Linux kernel that is, effectively turn it into Linux? POWER5 is not far off and will offer significantly better performance than POWER4, according to IBM s claims, but will not be pin-compatible with POWER4. Performance The p690 has a string of benchmark successes and most recently (2Q/3Q03) has been playing leapfrog with HP s Itanium 2-based Superdome for leadership of the Transaction Processing Council s TPC-C benchmark. Whether it s TPC, SAP R/3, System Performance Evaluation Council (SPEC), or whatever the benchmark, the key point is that the p690 can match the competition, but with fewer processors. Put aside the issue of the price/performance achieved by the benchmark configurations and look at what the ability to do more with less means in terms of database software license costs. For example, and, depending on the database, software licenses for the p690 can be anything up to two times less expensive for the equivalent capacity than for other high-end Unix servers. Another key point about the p690 s architecture is that system bandwidth scales with the processors. Because the p690 s system interconnect is clocked at half the speed of the processors, system bandwidth improves when faster processors are added. Other high-end Unix servers, such as the Sun Fire 15K (F15K), generally have a backplane clocked at a fixed speed in Sun s case 150MHz. This doesn t alter even when faster processors are added. With the p690+, IBM has also added the option of faster memory clocked at 567MHz rather than 500MHz. In this case, the faster memory is designed to reduce memory latencies and reduce the time processors spend waiting for data to be retrieved. Rounding off the performance enhancements for the p690+, the enhanced RIO-2 drawer interface has doubled the connection speed for the I/O drawers and doubled the 6 August

11 connections to the CECs. IBM has also increased the number of high-performance PCI-X and PCI adapters that can be supported, and maximum aggregate I/O bandwidth is increased by a factor of 2.75x. This is a big powerful server, so it s not surprising that customers include the European Centre for Medium-Range Weather Forecasts (ECMWF), which has a cluster of 60 p690s. Viability Viability is another key factor in evaluating any server that will require a significant investment such as the p690 and p690+. Other large Unix servers have come and gone, from Pyramid to Compaq AlphaServers. Clearly, IBM is safe in financial terms, and AIX is in no imminent danger of being absorbed by a competitor. Although the legal action instigated by SCO in 2Q03 has cast a cloud over AIX (ultimately we believe that IBM will do what is necessary to protect the AIX installed base). Despite convergence around processor architectures, with Intel gaining an ever larger slice of the server market, in Gartner s view, IBM s POWER is safe for the near future and will remain a high-end competitor to Itanium and Sun s SPARC architecture. POWER is used across two product lines pseries and IBM s profitable mid-market iseries systems which helps to amortize research and development costs. IBM also has a clear road map for POWER, through POWER5 and POWER6, and so far has delivered well on its promises, both in terms of timeliness and performance. Market Position In 2002, IBM had a 21.3 percent share of the total RISC/Unix server market by revenue. This puts IBM into third place, behind Sun with 38.7 percent and HP with 31.3 percent. However, the important thing is that IBM improved its position in the RISC/Unix segment of the market during the course of Although the overall market declined overall by nearly 11 percent compared with the previous year, IBM s RISC/Unix sales revenue declined by less than half that figure: 5.3 percent. Sales of the high-end p690, in particular, contributed to IBM s relative success. According to Gartner DataQuest, IBM sold 2,219 p690s worldwide in 2002, compared with HP s sales of 1,027 Superdomes, and 818 for Sun s F15K. Client Issues Inquiries from Gartner clients either using or interested in the p690 have focused on three main issues: LPAR technology and single points of failure (SPOF) Does the p690 have too much performance for my needs? What is the future of AIX? Will it become Linux? IBM s LPAR technology is elegant in its implementation compared with the hard partitioning that has characterized some other Unix systems. IBM s LPARs are granular with AIX 5L v.5.1 and 5.2 they support partitions as small as a single CPU. With AIX 5.3, partitioning at the sub-processor level is promised. With AIX 5L v.5.2, IBM introduced dynamic partitioning, the ability to reconfigure partitions without having to take them offline. Prior to the POWER4+ announcements, the p690 supported a maximum of 16 LPARs, but now both the p690 and p690+ support up to 32 partitions. But the p690 s LPARs are soft partitions. They don t offer the electrical isolation of hard partitions. Therefore it s not possible to electrically isolate an MCM, remove and replace it, for example, without shutting down the whole system. That s one of the reasons why IBM has included the option of CUOD, however, and why ChipKill memory is included as standard. With CUOD, a spare processor can be automatically activated to takeover from a failing processor, without having to take the system down and rebooting it (Dynamic Processor Sparing, see above). A fully configured p690 with all 32 CPUs active can t of course benefit in this way from hot sparing. The ChipKill bit-steering memory means that a 6 August

12 memory chip that s generating multiple memory errors, can be isolated and spare memory activated to take over from the faulty chip, without causing a system outage. All p690s have spare memory chips. The p690 has a very good record on reliability. According to the vendor, meantime-between-failure rates for critical components (processors, memory, backplane) for the p690 are 3x better than the original design target, and that was set at 5x higher than the Unix industry average. The p690 s LPARs are also based on essentially the same technology as that used for IBM s iseries servers. The iseries has an excellent record for reliability. Many customers use the LPAR capability, and many use it on single, nonclustered servers. In short, iseries customers don t see the lack of hard partitions as an issue, so why do pseries customers? Whatever the reason, pseries customers do feel unsure about consolidating too much of their workload onto a single server without the option of a failover cluster. IBM s HACMP clustering software is of course available the latest v.5 offers improved administration and the option of an integrated cluster file system but the cost can be high especially if the cluster nodes are all p690s. For some clients therefore, a better option may be to use a cluster of smaller midrange pseries servers, such as the p650 or p670. Both models support LPARs and AIX s Workload Management (WLM) software, and an active/active HACMP cluster is a way to provide consolidation with the extra degree of reassurance provided by a cluster. As yet, however, IBM s WLM software isn t cluster-aware, so it can t balance workloads across the cluster or ensure that high-service levels are maintained for a high-priority service in the event of its failing over to a backup node. Sun s Prioritized Service Manager in Sun Cluster 3.1 can do this, for example. p690 Too Much Power? As already indicated, the p690 is one of the most powerful Unix servers currently available. The number of customers who actually need that performance for a single, large database or software instance is small. Clearly, with the LPARs and WLM, the p690 can also serve as a consolidation platform, though as the comments above suggest, not all clients are happy about consolidating around one big server. With POWER4+ offering performance improvements and LPAR support across a range of pseries servers, many existing RS/6000 users and users of older pseries models will find that the p670+ or even a p650 can easily handle their workload requirements. For example, the RS/6000 S85, IBM s high-end Unix server prior to the p690 and POWER4-generation of servers achieved 8,550 SAPS on the SAP R/3 SD 2-tier benchmark a benchmark that we take as a good indicator of an all-around performance. That works out at SAPS per processor. Compare that with the POWER4+-based p650, however, which achieves more than twice the SAPS per processor: 6,130 SAPS for an eight-way configuration and SAPS per processor. Clients with six-, eight-, 12- or even 16-way configurations of the RS/6000 S70, S80 or S85, should thus consider whether smaller, less expensive pseries servers such as the p650 and p670+ can fulfill their requirements. They may find that relatively small configurations of the p650 and p670+ can easily handle existing workloads with capacity to spare (see SAP SD table below). Table 5: Performance Comparisons: SAP SD Model Processor Configuration SAPS SAPS/Processor p GHz POWER GHz POWER4+ 4, , August

13 Table 5: Performance Comparisons: SAP SD Model Processor Configuration SAPS SAPS/Processor p670 p690 p680 The Future of AIX 8 1.1GHz POWER GHz POWER MHz PowerPC RS64-III 4, , , Clients should consult Gartner s Web site for on-going comment and advice on the litigation brought by SCO over the alleged infringement of its intellectual property rights. At the time this report was written, the outcome is far from clear. In the meantime, Gartner believes no short-term threat exists to the continued operation and deployment of AIX-based systems. But we advise clients to request in writing IBM s assurance and indemnity from legal liability in all future AIX-based procurements as well as coverage for current installations. (Clients should consult the following Research Notes and look out for subsequent follow-on research: Management Update: The Effects of the SCO Lawsuit on IBM AIX Customers, IGG ; SCO s Threat to Sue Linux Users Serious but Remote, FT ) Independently of the SCO litigation, since IBM began to focus heavily on Linux and incorporated the Linux application programming interface (API) into AIX, a number of clients have questioned IBM s intentions with regard to AIX. Will it simply turn the AIX kernel over to Linux? While it is true that IBM has been very strong in its commitment to Linux, we don t believe that the adoption of a Linux kernel for AIX is in IBM s current plans. There are a number of reasons. Linux is still immature in its SMP support it does not scale to 32 processors, let alone the 64 processors of IBM s next generation POWER5-based servers. Similarly, Linux s multithreading capabilities are limited and will be hard pressed to support the levels of simultaneous multithreading proposed for future POWER processors. It also seems unlikely that IBM would want to share the intellectual property (IP) it s putting into AIX with regard to autonomic and ondemand computing. It is these features that IBM hopes will provide some of the key differentiators between the pseries and other Unix platforms from Sun and HP. AIX is a far more mature operating system (OS) than Linux. It is that close link between OS and hardware functionality that provides scalability, high levels of availability and manageability, and the ability to virtualize the server and its resources that will keep it separate from, and ahead of, Linux. That s not to say that IBM won t continue to support a Linux API and port AIX features to Linux it will. It ll do this because of the momentum behind Linux and because it wants to be a leading supplier of Linux hardware, software and services. So, we already have Linux-only versions of the low-end and midrange POWER4 servers. Linux is supported in AIX LPARs on the high-end machines (p670 and p690); and Linux clusters on IBM s xseries servers can now be managed alongside AIX clusters, controlled through a single AIX management point. IBM is doing everything it can to enable the coexistence of AIX and Linux, but that doesn t mean it wants to substitute one with the other at least not for a long while yet. Future Directions IBM is promising that its next generation of POWER processors, POWER5, will offer significant performance improvements over POWER4. At the system level, we would expect POWER5 to offer a percent performance improvement over POWER4+ for similar configurations, rising to a percent 6 August

14 improvement for the second generation POWER5+. Larger, 64-way POWER5+ systems will also be available and could offer almost double the performance of an existing 32-way p690+. IBM is suggesting that POWER5 be delivered within the first half of We understand that POWER5 will debut in midrange systems first somewhat differently to POWER4 which appeared first in the high-end p690. The high-end follow-on to the p690+, CODe-named Squadron, would then probably arrive around the fourth quarter of 2004, given that most high-end pseries and RS/6000 servers have been announced in the fourth quarter. IBM has delivered well on its POWER road map so far, keeping on schedule with POWER4 and POWER4+. But what does the arrival of POWER5 and the 64-way Squadron mean for clients who purchase POWER4 and POWER4+ models in the interim? POWER5 and Squadron will include new MCM and distributed switch technology, so existing POWER4/4+ servers will not be pin-compatible with the new technology clients won t be able to put POWER5 MCMs into existing POWER4/4+ servers. So are POWER4+ and the p690+ destined for a short shelf life? As we ve already mentioned, the p690+ performance is already best in class and exceeds the requirements of many existing RS/6000 and pseries customers. With their CUOD capabilities covering both processors and memory (provided AIX 5L v.5.2 or above is installed), and plenty of I/O expansion available, the p690 and p690+ should easily meet customers three- to four-year return-oninvestment (ROI) requirements. And as we ve also suggested, with dynamic LPARs supported in AIX 5L v.5.2 and Workload Management software integral to AIX, we believe all of the POWER4/4+ midrange and high-end pseries servers are good consolidation platforms for older AIX servers. Fewer servers and less expensive software licenses through the ability to use smaller processor configurations can also contribute to lower cost-of-ownership. We believe that IBM will face opposition from customers if it makes its current generation of servers obsolete too quickly. Customers don t like to buy hardware that they think may become obsolete within less than two-to-three years of purchase. IBM would be wise to retain the p690+ models on its price list for at least two years after the introduction of POWER5. Alternatively, it may offer financial incentives to upgrade, although many customers prefer to hang on to the proven stability of an existing platform to maximize ROI. After POWER5, IBM s road map has POWER5+ scheduled for 2005 and beyond that, POWER6, presumably in the 2006 time frame. POWER5 will be based on 0.13 micron technology, with the processor cores clocked in the 1.4- to 2.0GHz range. POWER5+ is a die shrink to 0.09 micron or 90 nanometer (nm) technology with the processor cores clocked in the 2- to 3GHz range. POWER5/5+ will feature even greater integration of the MCMs and the introduction of simultaneous multithreading the ability to run multiple software threads on each processor core, so that one core effectively seems like two or more processors. POWER6 is still at the design phase at the time this report was written. Pricing The prices in the table below are based on U.S. list prices as at the second quarter of Gartner only tracks U.S. list prices in its Product Reports. In doing so, we offer a simple comparison tool for comparing servers in a similar price range virtually every leading vendor sells its products in the U.S.A. In the RISC/Unix server market, it is usual for vendors to offer discounts on hardware. Prior to the CEC and memory price cuts announced by IBM in March 2003, Gartner client feedback from the U.S. and Europe indicated that clients were typically being offered discounts of between 30 and 40 percent on the p690. After the price cuts and the introduction of the p690+, client feedback indicates that much lower discounts of below 20 percent are now being offered. 6 August

15 Table 6: Price List: IBM eserver pseries 690 Configuration/Part No. Description Price (US$) Minimum p690 System Configuration Includes: CEC Enclosure, eight-way 1.1GHz POWER4 processor module, 8GB of main memory, one I/O drawer with two 36.4GB disks, system rack and IBM AIX user license Minimum p690 Turbo System Configuration As above, but with eightway1.3ghzpower4 processor module Minimum p690+ System Configuration Includes: CEC Enclosure, eight-way 1.5GHz POWER4 processor module, 8GB of main memory, one I/O drawer with two 36.4GB disks, system rack and IBM AIX user license Minimum p690 Turbo System Configuration As above, but with eightway1.7ghzpower4 processor module CEC Base CEC Enclosure including: 128MB Level 3 cache(4x32mb, 500MHz), backplane, processor clock card, service processor with remote I/O loop, media drawer, operator panel, CD-ROM and diskette drive, power converters and cables D I/O Drawer and Cables RIO2 I/O drawer: PCI Planar with two integrated Ultra3 SCSI ports, Ultra3 SCSI 4-pack hot-swap backplane, two 18.2GB boot disks, PCI SE SCSI adapter, power converters and cables Processor Options 5242 Eight-way POWER4 processor, 1.1GHz 343, , , , ,144 40, ,000 6 August

16 Table 6: Price List: IBM eserver pseries 690 Configuration/Part No. Description Price (US$) 5243 Eight-way POWER4+ processor, 1.5GHz 5244 Eight-way POWER4 Turbo Option, 1.3GHz 5246 Eight-way POWER4+ Turbo Option, 1.7GHz 5250 Four-way POWER4 HPC Processor, 1.3GHz Memory Options 275, , ,000 84, /4197 4GB memory card 14, /4182 8GB memory card 28, / GB memory card 57, / GB memory card 114, /4481 4GB Memory Card 14,336 (567MHz) 4482/4483 8GB Memory Card 28,672 (567MHz) 4484/ GB Memory Card 57,344 (567MHz) 4486/ GB Memory Card 114,688 (567MHz) 4488/ GB Memory Card 229,376 (567MHz) System Rack R Rack including front and 35,050 rear doors, redundant bulk power assembly, power controllers and fans, line cords and others Prices as at June Prices are provided only as a guide. Gartner accepts no responsibility for their accuracy. GSA Pricing Yes. Competitors Table 7: Competitive Comparison: IBM eserver pseries 690 System IBM p690 Fujitsu PRIMEPOWER 2500 HP Superdome Sun Fire (F15K) Processors POWER4+ (1.5GHz, 1.7GHz) SPARC64 V (1.3GHz) PA-8700 (750MHz), PA MHz) UltraSPARC III (1.05GHz, 1.2GHz) 6 August

17 Table 7: Competitive Comparison: IBM eserver pseries 690 System IBM p690 Fujitsu PRIMEPOWER 2500 HP Superdome Sun Fire (F15K) Processor 1,113 (1.7GHz) (1) 860 (2) Not available (3) Not available (4) Performance (SPECint2000) Max. Number of or (1) Processors Supported Max. Memory 512GB 256GB (64-way) or 256GB 576GB 512GB (128-way) Peak Interconnect 54.4GB/sec. 133GB/sec. Information not 43GB/sec. Bandwidth (remote accesses) available Maximum I/O Slots 160 PCI-X 160 (64-way) or 192 PCI 72 PCI 320 PCI (128-way) Peak Aggregate I/O 44GB/sec. 64GB/sec (64-way) 32GB/sec. 21.6GB/sec. Bandwidth or 128GB/sec (128- way) System Software Operating IBM AIX 5L, SuSE Sun Solaris 8 or 9 HP-UX 11i Sun Solaris 8 or 9 System(s) Supported Linux Enterprise Server (5) Type of Partitioning Soft Hard Hard (npars); soft Hard Supported (vpars) Maximum Number (hard); 64 (soft) 18 of Partitions Supported Partition Granularity 1 processor 2 processors 4 processors 4processors (hard); 1 processor (soft) Dynamic Yes (AIX v.5.2) Yes Hard no; soft Yes Reconfiguration of Partitions yes Workload Management Software Included Yes Yes (Solaris 9 and ARMTech Share Enterprise) No (6) Yes(Solaris9) 6 August

18 Table 7: Competitive Comparison: IBM eserver pseries 690 System IBM p690 Fujitsu PRIMEPOWER 2500 HP Superdome Sun Fire (F15K) High Availability Processor/System Board Dynamic (online) CPU de-allocation by OS; CPU deconfiguration at reboot; automatic capture of failure data Instruction retry; parity protection on execution units and registers; error log collection by H/W; CPU deconfiguration at reboot; concurrent Dynamic (online) CPU de-allocation by OS; online hotsparing of COD processors; CPU de-configuration at reboot; concurrent maintenance of CPU deconfiguration at reboot; concurrent maintenance of system boards; Dynamic Reconfiguration of system boards maintenance of system boards system boards Memory ECC on L2 caches and main memory; online de-allocation; ChipKill faulttolerance; soft memory scrubbing; ECC on L1 and L2 caches and main memory; automatic single-bit correction in L1 cache by hardware; dynamic ECC on L2 caches and main memory; online de-allocation; DRAM faulttolerance; soft memory scrubbing ECC on L2 caches and main memory; dynamic reconfiguration of memory/system board redundant bit steering random-access memory (DRAM) fault-tolerance I/O I/O Multipathing; PCI hot-plug; PCI bus error recovery I/O Multipathing; PCI hot-plug; Dynamic Reconfiguration of I/O error recovery; I/O Multipathing I/O Multipathing; Dynamic Reconfiguration of I/O boards PCI/disk boxes Memory Scrubbing Yes Yes Yes Yes Redundant Hardware Power supplies, cooling, service processor Crossbar, system clock, power supplies, cooling, Power supplies, cooling, service processor Backplane, system clock, power supply, cooling DC-DC converter, system control feature Performance TPC-C 763, tpmc Not available 541, tpmc Not US$8.31/tpmC US$10.69/tpmC (8) SPECint_rate_base 322 (32 1.7GHz) 127 ( GHz) 394 (64 875MHz) 430 (72 1.2GHz) 2000 SPECjbb ,484 (32 1.3GHz) 835,479 (64 1.3GHz) 614,358 (64 875MHz) 602,270 ( GHz) 6 August

19 Table 7: Competitive Comparison: IBM eserver pseries 690 System IBM p690 Fujitsu PRIMEPOWER 2500 HP Superdome Sun Fire (F15K) SAP R/3 SD 2-Tier 20,830 SAPS (32 37,900 SAPS (64 Not available 29,820 SAPS (72 Client/Server 1.3GHz) 1.3GHz); 65, GHz); 40,650 Release 4 SAPS (128 SAPS ( GHz) 1.2GHz) (1) Only one processor was enabled, however, to provide maximum (and atypical) L2 cache bandwidth. (2) Gartner s estimate: SPECint2000 benchmarks are only available for the 1.35GHz version of SPARC64 V in the PRIMEPOWER 900. (3) HP has not published SPECint2000 benchmarks for the 850MHz PA processors. (4) Sun has not published SPECint2000 benchmarks for the 1.2GHz UltraSPARC processors. (5) Linux is only supported in LPARs. (6) Optionally available or included as part of the HP-UX 11i Enterprise and Mission-critical system software bundles. (7) Server details: 32 x 1.7GHz processors, 512GB memory, AIX 5L v.5.2 operating system, IBM DB2 UDB 8.1 database software. Availability: 8 November (8) HP has achieved 824,165 US$8.28/tpmC, with the Itanium 2 (Madison) Superdome, running. Strengths Class-Leading 32-way The p690+ offers class-leading performance from a 32-way server. Other servers may beat the p690+ on individual benchmarks, such as TPC-C or SAP R/3 SD, but few can get near its performance in 16- to 32- way configurations. Key to the p690 s success is a design that scales with processor speed and capacity. As faster processors are added, so both system interconnect and I/O bandwidth increase. The significance of doing more with less is that software priced on a per-cpu basis will be less expensive if fewer processors are required for a given capacity. Good Record on Reliability Fast systems are all very well, but not much use if they break down. The p690 appears to be achieving very good levels of reliability. We have had no reports of significant (processor, memory or backplane) hardware problems from clients. The p690 has particularly good memory redundancy (about one seventh of the memory chips are redundant) a lot of hardware problems with high-capacity servers tend to stem from memory errors. We also like the First Failure Data Capture feature, which is designed to speed up recovery from failures by automatically recording error check states at the time of failure. Speedy recovery provides higher availability and, according to IBM, the system is proving invaluable in identifying the root causes of problems. Wide Range of Applications for AIX After some initial issues in ensuring that 64-bit versions of applications were available on AIX 5L (the main issue was with Oracle), the applications portfolio for IBM s Unix operating system continues to grow. AIX is well supported by independent software vendors (ISVs), due in part to IBM s success in promoting DB2 as an alternative to Oracle. While Oracle is still the database market leader by a large margin, IBM s success in cultivating ISVs to support its middleware has also had spin-offs for the IBM server platforms. WebSphere in particular has been a key contributor in encouraging ISVs to support the whole AIX software stack. 6 August

20 Dynamic and Granular Partitions With AIX v.5.2, IBM added dynamic reconfiguration capabilities to its pseries LPARs. The LPARs are also very granular for a Unix more granular than hard partitions and there s now support for up to 32 LPARs. The dynamic LPAR capability means that partition configurations can be changed without having to take the system offline or reboot either the system or the partitions. Again, this contributes to maintaining system availability. Clients are reminded that most downtime is caused through operator error, however, so the dynamic reconfiguration capability should be used sparingly. Hot Sparing of Processors via CUOD Capability Hot sparing of memory chips is provided as standard on the p690, but if clients want the reassurance of hot-spare processors, then they can get it, but only if they have CUOD processors installed. There s a 10 percent premium for CUOD processors, but no charge if a CUOD is activated by the operating system to take over from a processor that s generating too many errors. IBM now offers more flexible CUOD options in general, including temporary as well as permanent capacity on demand. Temporary COD will suit customers who have known seasonal peaks in their workload. Limitations POWER5 Will Not Be Pin-Compatible With POWER4 POWER5 will not be pin-compatible with POWER4/4+, meaning that the next-generation of high-end pseries servers will be a new generation in terms of system design. While IBM will undoubtedly provide upgrade programs for users of the current POWER4/4+ systems, it needs to provide reassurance that it will continue to actively support the p690 for a number of years after the introduction of the Squadron systems. Customers expect to maintain these high-end servers in place for at least four to five years, to achieve a good ROI and will expect them to be supported in new operating system and system software releases. Client Confidence in LPARs Although LPARs and soft partitioning in general offer advantages in terms of dynamic capabilities and granularity, and offer a better basis for automation and policy-based control in the future, they do not offer the electrical isolation of hard partitions. Although the p690 has a very good reputation for hardware reliability, the inability to isolate hardware faults and restrict them to the partitions in which they occur is seen by some clients as a drawback. Isolation and redundancy can be achieved through clustering, and we would expect most mission-critical servers to be clustered. But then, if you re going to spread your workload across clustered systems, do you need p690s in the first place? Or can you get by with smaller servers, such as IBM s p670 or p650? AIX System-Level Management Tools As we noted above, most downtime is caused by operator error. Most Unix system management relies on the expertise of skilled operators; the increasing complexity of the systems and applications they re dealing with means that tools to assist and automate software provisioning across multiple servers, provide advanced multisystem/multiversion inventory management and provide secure role-based access to system-level management are key. We believe that this is an area where AIX s System Management Interface Tool (SMIT) lags behind the best of the competition. HP and Sun both provide centralized system-level management tools that offer role-based access, depending on operators roles and integrate a number of different graphical tools to simplify routine system administration tasks. 6 August

21 Recommended Gartner Research Management Update: The Effects of the SCO Lawsuit on IBM AIX Customers, IGG SCO s Threat to Sue Linux Users Serious but Remote, FT Insight The p690 has been a very successful product for IBM. The p690+ versions offer yet more power and improved memory and I/O throughput. The LPAR technology offers good granularity and flexibility compared with other Unix platforms and Intel, and AIX 5L v.5.2 includes workload manager software as standard. However, the next generation of POWER5 will not be pin-compatible with POWER4/4+, so customers should seek assurances from IBM that the p690 CEC will remain fully supported for at least five years after the introduction of the next-generation Squadron servers. The p690+ already has more raw processing power than many mainframes. It doesn t yet approach mainframe technology in terms of partitioning, resource/workload management or I/O functionality, but these capabilities will come. Just as mainframe customers don t expect to throw out their existing CEC every time new functionality comes along, neither should Unix users. Longevity and long-term ROI are the best arguments in favor of RISC/Unix against the Intel onslaught. 6 August