DDR4 SDRAM RDIMM CT16G4RFD4### - 16GB. Features. 16GB (x72, ECC, DR x4) 288-Pin DDR4 RDIMM Features. Preliminary

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1 DDR4 SDRAM RDIMM CT16G4RFD4### - 16GB Preliminary Features Features DDR4 functionality and operations supported as defined in the component data sheet 288-pin, registered dual in-line, memory module (RDIMM) Fast data transfer rates: PC4-2400, PC4-2133, or PC GB (2 Gig x 72) V DD = 1.2V (typical) V PP = 2.5V (typical) V DDSPD = V Supports ECC error detection and correction Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Low-power auto self refresh (LPASR) Data bus inversion (DBI) for data bus On-die V REF generation Dual-rank On-board I 2 C temperature sensor with integrated serial presence-detect (SPD) EEPROM 16 internal banks; 4 groups of 4 banks each Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) Selectable BC4 or BL8 on-the-fly (OTF) Gold edge contacts Halogen-free Fly-by topology Terminated control, command and address bus Figure 1: 288-Pin RDIMM (MO-309 R/C-B) Module height: 31.25mm (1.23in) Table 1: Key Timing Parameters Speed Grade Industry Nomenclature Data Rate (MT/s) CL = 18 CL = 16 CL = 15 CL = 14 CL = 13 CL = 12 CL = 11 CL = PC PC PC t RCD (ns) t RP (ns) t RC (ns). CTL0205.fm - Rev. 06/25/ Micron Technology Inc. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Crucial without notice.

2 Features Table 2: Addressing Parameter Row address Column address Device bank group address Device bank address per group Device configuration Module rank address 8GB 64K A[14:0] 1K A[9:0] 4 BG[1:0] 4 BA[1:0] 4Gb (1 Gig x 4), 16 banks 2 CS_n[1:0] Table 3: Part Numbers and Timing Parameters - 8GB Modules Base device:mt40a1g4, 1 4Gb DDR4 SDRAM Part Number 2 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL- t RCD- t RP) CT16G4RFD4240.z36xy 16GB 1 Gig x GB/s 0.83ns/2400 MT/s CT16G4RFD4213.z36xy 16GB 1 Gig x GB/s 0.93ns/2133 MT/s CT16G4RFD4186.z36xy 16GB 1 Gig x GB/s 1.07ns/1866 MT/s Notes: 1. The data sheet for the base device can be found on by contacting your Micron Consumer Products Group Sales Representative. 2. All part numbers end with a code (not shown) that designates component revisions. Consult factory for current revision codes. Example: CT16G4RFD4213.z36xy, where z is the mark on the DRAM (not present or M is Micron, and C is CPG) and x and y are for component revisions and traceability. CTL0205.fm - Rev. 06/25/ Micron Technolog Inc

3 Pin Assignments Pin Assignments Table 4: Pin Assignments 288-Pin DDR4 RDIMM Front 288-Pin DDR4 RDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 NC V DD NC V DD CK0_t 110 S14_t/ 146 V REFCA CK1_t 254 TS14_ t CK0_c 111 S14_c/ CK1_c 255 S5_c TS14_ c 4 40 S12_t/ 76 V DD V DD 256 S5_t TS12_ t S12_c/ 77 V TT S3_c 221 V TT 257 TS12_ c EVENT_n S3_t 222 PARITY S9_t/ A V DD 259 TS9_t 8 S09_c/ V DD S0_c BA TS9_c BA S0_t A10/AP RAS_n/ V DD A CB4 83 V DD NC CS0_n CB5 228 WE_n/ A CB0 85 V DD 121 S15_t/ V DD 265 TS15_ t CAS_n/ 122 S15_c/ CB1 230 NC 266 S6_c A15 TS15_ c S17_t/ 87 ODT V DD 267 S6_t TS17_ t S17_c/ 88 V DD S8_c 232 A TS17_ c CS1_n/NC S8_t 233 V DD S10_t/ 54 CB6 90 V DD A TS10_ t 19 S10_c/ ODT1/NC S1_c 199 CB7 235 NC/C TS10_ c CB2 92 V DD S1_t V DD CS2_n/C CB3 237 CS3_n/ C1,NC RESET_n SA V DD CKE CTL0205.fm - Rev. 06/25/ Micron Technolog Inc

4 Pin Assignments Pin Assignments Table 4: Pin Assignments (Continued) 288-Pin DDR4 RDIMM Front 288-Pin DDR4 RDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol CKE S16_t/ V DD TS16_ t V DD S16_c/ NC S7_c TS16_ c ACT_n V DD S7_t BG0 99 S13_t/ BG T13_t V DD 100 S13_c/ ALERT_n 244 S4_c TS13_ c 29 S11_t/ 65 A12/BC_n V DD 245 S4_t 281 TS11_ t 30 S11_c/ 66 A S2_c 210 A TS11_ c V DD SA0 175 S2_t 211 A A SA V DD V DDSPD A SCL A SDA V DD V PP A V PP A V PP V DD V PP A NC A V PP CTL0205.fm - Rev. 06/25/ Micron Technolog Inc

5 Pin Descriptions Pin Descriptions The pin description table below is a comprehensive list of all possible pins for DDR4 UDIMM, RDIMM, SODIMM and LRDIMM modules. All pins listed may not be supported on the module defined in this data sheet. See functional block diagram specific to this module to review all pins utilized on this module. Table 5: Pin Descriptions Symbol Type Description Ax Input Address inputs: Provide the row address for ACTIVATE commands and the column address for READ/WRITE commands to select one location out of the memory array in the respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, and RAS_n/A16 have additional functions; see individual entries in this table). The address inputs also provide the op-code during the MODE REGISTER SET command. A17 is only defined for x4 SDRAM configuration. A10/AP Input Auto precharge: A10 is sampled during READ and WRITE commands to determine whether auto precharge should be performed to the accessed bank after a READ or WRITE operation (HIGH = Auto precharge; LOW = No auto precharge). A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by the bank group and bank addresses. A12/BC_n Input Burst Chop: A12/BC_n is sampled during READ and WRITE commands to determine if burst chop (on-the-fly) will be performed. (HIGH = No burst chop; LOW = Burst-chopped). See the Command Truth Table in DDR4 component data sheet for more information. ACT_n Input Command input: ACT_n defines the activation command being entered along with CS_n. The input into RAS_n/A16, CAS_n/A15, and WE_n/A14 will be considered as row address A16, A15, and A14. See the Command Truth Table in DDR4 component data sheet for more information. BAx Input Bank address inputs: Define to which bank an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. Also determines which mode register is to be accessed during a MODE REGISTER SET command. BGx Input Bank group address inputs: Define which bank group a REFRESH, ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. Also determines which mode register is to be accessed during a MODE REGISTER SET command. BG[1:0] are used in the x4 and x8 configurations. x16 based SDRAMs only have BG0. C0, C1, C2 (RDIMM/ LRDIMM Only) CKx_t CKx_c Input Input Chip ID: These inputs are used only when devices are stacked, that is, 2H, 4H, and 8H stacks for x4 and x8 configurations using though-silicon vias (TSVs). These pins are not used in the x16 configuration. Some DDR4 modules support a traditional DDP package, which use CS1_n, CKE1, and ODT1 to control the second die. For all other stack configurations, such as a 4H or 8H, it is assumed to be a single-load (master/slave)- type configuration where C0, C1, and C2 are used as chip ID selects in conjunction with a single CS_n, CKE, and ODT. Chip ID is considered part of the command code.. Clock: Differential clock inputs. All address, command, and control input signals are sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c. CTL0205.fm - Rev. 06/25/ Micron Technolog Inc

6 Pin Descriptions Table 5: Pin Descriptions (Continued) Symbol Type Description CKEx Input Clock enable: CKE HIGH activates, and CKE LOW deactivates, the internal clock signals, device input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is asynchronous for self refresh exit. After V REFCA has become stable during the power-on and initialization sequence, it must be maintained during all operations (including SELF REFRESH). CKE must be held HIGH throughout read and write accesses. Input buffers (excluding CK_t, CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE and RESET#) are disabled during self refresh. CSx_n Input Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides external rank selection on systems with multiple ranks. CS_n is considered part of the command code. CS2_n and CS3_n are not used on UDIMMs. ODTx Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR4 SDRAM. When ODT is enabled, on-die termination (R TT ) is applied only to each, S_t, S_c, DM_n/DBI_n/TS_t, and TS_c signal for x4 and x8 configurations (when the TS function is enabled via the mode register). For the x16 configuration, R TT is applied to each, SU_t, SU_c, SL_t, SL_c, UDM_n, and LDM_n signal. The ODT pin will be ignored if the mode registers are programmed to disable R TT. PARITY Input Parity for command and address: This function can be enabled or disabled via the mode register. When enabled in MR5, then DRAM calculates Parity with ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG[1:0], BA[1:0], A[16:0]. Input parity should be maintained at the rising edge of the clock and at the same time with command and address with CS_n LOW. RAS_n/A16 CAS_n/A15 WE_n/A14 Input Command inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n) define the command and/or address being entered. Those pins have multifunction. For example, for activation with ACT_n LOW, these are addresses like A16, A15, and A14, but for a non-activation command with ACT_n HIGH, these are command pins for READ, WRITE, and other commands defined in the command truth table. RESET_n CMOS Input Active LOW asynchronous reset: Reset is active when RESET_n is LOW; inactive when RESET_n is HIGH. RESET_n must be HIGH during normal operation. SAx Input Serial address inputs: Used to configure the temperature sensor/spd EEPROM address range on the I 2 C bus. SCL Input Serial clock for temperature sensor/spd EEPROM: Used to synchronize communication to and from the temperature sensor/spd EEPROM on the I 2 C bus. x, CBx I/O Data input/output and Check Bit input/output : Bidirectional data bus. represents [3:0], [7:0], and [15:0] for the x4, x8, and x16 configurations, respectively. If cyclic redundancy checksum (CRC) is enabled via the mode register, then CRC code is added at the end of the data burst. Either one or all of 0, 1, 2, or 3 is/are used for monitoring of internal V REF level during test via mode register setting MR[4] A[4] = HIGH; training times change when enabled. V DDSPD Supply Serial EEPROM positive power supply: +3.0V to +3.6V. CTL0205.fm - Rev. 06/25/ Micron Technolog Inc

7 Pin Descriptions Table 5: Pin Descriptions (Continued) Symbol Type Description DM_n/DBI_n/ TS_t(DMU_n,DBI U_n),(DML_n/ DBIl_n) S_t S_c SU_t SU_c SL_t SL_c I/O I/O Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data. Input data is masked when DM_n is sampled LOW coincident with that input data during a write access. DM_n is sampled on both edges of S. DM is mux ed with DBI function by mode register A10, A11, A12 setting in MR5. For x8 device, the function of DM or TS is enabled by mode register A11 setting in MR1. DBI_n is an input/ output identifying whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/output after inversion inside the DDR4 SDRAM and not inverted if DBI_n is HIGH. TS is only supported in x8 SDRAM configurations. TS is not valid for UDIMMs. Data strobe: Output with read data, input with write data. Edge-aligned with read data, centered-aligned with WRITE data. For x16 configurations, SL corresponds to the data on [7:0]; SU corresponds to the data on [15:8]. For the x4 and x8 configurations, S corresponds to the data on [3:0] and [7:0] respectively. DDR4 SDRAM support a differential data strobe only and do not support a singleended data strobe. ALERT_n Output Alert output: Possesses multifunctions such as CRC error flag and command and address parity error flag as output signal. If there is a CRC error, then ALERT_n goes LOW for the period time interval and returns HIGH. If there is error in command address parity check, then ALERT_n goes LOW until on-going DRAM internal recovery transaction is complete. During connectivity test mode this pin functions as an input. Using this signal or not is dependent on the system. If not connected as signal, ALERT_n pin must be connected to V DD on DIMM. EVENT_n Output Temperature event: The EVENT_n pin is asserted by the temperature sensor when critical temperature thresholds have been exceeded. This pin has no function (NF) on modules without temperature sensors. TS_t TS_c (x8 DRAM based RDIMM only) Output Termination data strobe: TS_t and TS_c are not valid for UDIMMs. When enabled via the mode register, the SDRAM enable the same RTT termination resistance on TS_t and TS_c that is applied to S_t and S_c. When the TS function is disabled via the mode register, the DM/TS_t pin provides the data mask (DM) function, and the TS_c pin is not used. The TS function must be disabled in the mode register for both the x4 and x16 configurations. The DM function is supported only in x8 and x16 configurations. DM, DBI, and TS are a shared pin and are enabled/ disabled by mode register settings. For further information about TS, refer to DDR4 DRAM data sheet. V DD Supply Module Power supply: 1.2V (typical) V PP Supply DRAM activating power supply: 2.5V V / V V REFCA Supply Reference voltage for control, command, and address pins. Supply Ground. V TT Supply Power supply for termination of address, command, and control, V DD /2. V DDSPD Supply Power supply used to power the I 2 C bus used for SPD. RFU Reserved for future use. NC No connect: No internal electrical connection is present. NF No function: Internal connection may be present but has no function CTL0205.fm - Rev. 06/25/ Micron Technolog Inc

8 Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram A/ B-CS0_n A/ B-CS1_n S0_t S0_c VSS S1_t S1_c S2_t S2_c S3_t S3_c S8_t S8_c CB0 CB1 CB2 CB3 S4_t S4_c S5_t S5_c S6_t S6_c VSS S7_t S7_c CS_n S_t S_c U1 CS_n S_t S_c U12 CS_n S_t S_c U13 CS_n S_t S_c U14 CS_n S_t S_c U5 CS_n S_t S_c U17 CS_n S_t S_c U8 CS_n S_t S_c U19 CS_n S_t S_c U20 CS_n S_t S_c U29 CS_n S_t S_c U37 CS_n S_t S_c U36 VSS CS_n S_t S_c U35 CS_n S_t S_c U25 CS_n S_t S_c U33 CS_n S_t S_c U23 CS_n S_t S_c U31 CS_n S_t S_c U30 S9_t S9_c S10_t S10_c VSS S11_t S11_c S12_t S12_c S17_t S17_c CB4 CB5 CB6 CB7 S13_t S13_c S14_t S14_c S15_t S15_c S16_t S16_c CS_n S_t S_c U11 CS_n S_t S_c U2 CS_n S_t S_c U3 CS_n S_t S_c U4 CS_n S_t S_c U15 CS_n S_t S_c U7 CS_n S_t S_c U18 CS_n S_t S_c U9 CS_n S_t S_c U10 CS_n S_t S_c U38 VSS CS_n S_t S_c U28 CS_n S_t S_c U27 VSS VSS CS_n S_t S_c U26 CS_n S_t S_c U34 CS_n S_t S_c U24 CS_n S_t S_c U32 CS_n S_t S_c U22 CS_n S_t S_c U21 CS0_n CS1_n BA[1:0] BG[1:0] ACT_n A[17, 13:0] RAS_n/A16 CAS_n/A15 WE_n/A14 CKE0 CKE1 ODT0 ODT1 PARITY ALERT_CONN RESET_CONN CK0_t CK0_c V DDSPD V DD V TT V REFCA V PP U16 Rank 0: U1 U5, U7 U15, U17 U20 Rank 1: U21 38 Command, control, address, and clock line terminations: A/B-CS_n[1:0], A/B-BA[1:0]A/B-BG[1:0], A/B-ACT_n, A/B-A[17, 13:0], A/B-RAS_n/A16, A/ B-CAS_n/A15, A/B-WE_n/A14, A/B-PAR, /AB-CKE1[:0], A/B-ODT 1[ :0] SCL CK1_t CK1_c R E G I S T E R & P L L CK[3:0]_t CK[3:0]_c VSS CK[3:0]_t CK[3:0]_c U6 SPDEEPROM/ Temp sensor EVT A0 A1 A2 SA0 SA1 SA2 EVENT_n A/B-CS0_n: Rank 0 A/B-CS1_n: Rank 1 A/B-BA[1:0]: DDR4 SDRAM A/B-BG[1:0]: DDR4 SDRAM A/B-ACT_n: DDR4 SDRAM A/B-A[17,13:0]: DDR4 SDRAM A/B-RAS_n/A16: DDR4 SDRAM A/B-CAS_n/A15: DDR4 SDRAM A/B-WE_n/A14: DDR4 SDRAM A/B C- KE0R: ank 0 A/B C- KE1R: ank 1 A/B-ODT0: Rank 0 A/B-ODT1: Rank 1 A/B P- AR:DDR4 SDRAM AL RE T_DRAM:DDR4SDRAM DDR4 SDRAM DDR4 SDRAM DDR4 SDRAM SDA DDR4 SDRAM SPD EEPROM/ Temp Sensor DDR4 SDRAM Control, command and add ress termination DDR4 SDRAM DDR4 SDRAM DDR4 SDRAM V TT V DD Notes: 1. The ball on each DDR4 component is connected to an external 240Ω ±1% resistor that is tied to ground. It is used for the calibration of the component s ODT and outpu driver. CTL0205.fm - Rev. 06/25/ Micron Technolog Inc

9 General Description General Description High-speed DDR4 SDRAM modules use DDR4 SDRAM devices with 2 or 4 internal memory bank groups. DDR4 SDRAM modules utilizing 4- and 8-bit-wide DDR4 SDRAM have 4 internal bank groups consisting of 4 memory banks each, providing a total of 16 banks. Sixteen-bit-wide DDR4 SDRAM has 2 internal bank groups consisting of 4 memory banks each, providing a total of 8 banks. DDR4 SDRAM modules benefit from DDR4 SDRAM's use of an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n-bit-wide, four-clock data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle dat transfers at the I/O pins. DDR4 modules use two sets of differential signals: S_t, S_c to capture data and CK_t and CK_c to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. FLy-By Topology DDR4 modules use faster clock speeds than earlier DDR technologies, making signa quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the connector). Inherent to fly-by topology, the timing skew between the clock and S signals can be easily accounted for by using the write-leveling feature of DDR4.. Registering Clock Driver Operation Registered DDR4 SDRAM modules use a registering clock driver device consisting of a register and a phase-lock loop (PLL). The device complies with the JEDEC DDR4 RCD01 Specification. To reduce the electrical load on the host memory controller's command, address, and control bus, Micron RDIMMs utilize a DDR4 registering clock driver (RCD). The RCD presents a single load to the controller while re-driving the signals to the DRAM helping to enable higher densities, and increased signal integrity. The RCD also provides a lowjitter and low-skew PLL that redistributes a differential clock pair to multiple differential pairs of clock outputs. Parity Operations The registering clock driver includes a parity-checking function that can be enabled or disabled in control word RC0E. The RCD receives a parity bit at the DPAR input from the memory controller and compares it with the data received on the qualified command and address inputs and indicates on its open-drain ALERT_n pin whether a parity error has occurred. If parity checking is enabled, the RCD forwards commands to the SDRAM only when no parity error has occurred. If the parity error function has been disabled, the RCD forwards sampled commands to the DRAM regardless of whether a parity error has occurred. Parity is also checked during control word WRITE operations unless parity checking is disabled. CTL0205.fm - Rev. 06/25/ Micron Technolog Inc

10 General Description Rank Addressing The chip select pins (CS_n) on Micron modules are used to select a specific rank of DRAM on a module. The RDIMM is capable of selecting ranks in 1 of 3 different ope ating modes dependant on setting DA[1:0] bits in the DIMM configuration control wor located within the RCD. Direct DualCS mode will be utilized for single or dual rank modules. For quad rank modules, either direct or encoded QuadCS mode can be used. CTL0205.fm - Rev. 06/25/ Micron Technolog Inc

11 Temperature Sensor with Serial Presence-Detect EEPROM Temperature Sensor with Serial Presence-Detect EEPROM Thermal Sensor Operations The integrated thermal sensor continuously monitors the temperature of the DIMM PCB directly below the device and updates the temperature data register. Temperature data may be read from the bus host at any time providing the host real time feedback of module temperature. System designers may utilize the multiple programmable and read-only temperature registers to create a custom temperature sensing solution based on system requirements and JEDEC JC EVENT_n Pin The temperature sensor also adds the EVENT_n pin. This is an open-drain output that requires a pull-up to V DD SPD. Not used by the SPD EEPROM, EVENT_n is a temperature sensor output used to flag critical events that can be set up in the sensor s configuration registers. EVENT_n has three defined modes of operation: interrupt mode, comparator mode, and TCRIT only. In interrupt mode the EVENT_n pin will remain asserted until it is released by writing a "1" to the clear event bit in the status register. In comparator mode the EVENT_n pin will clear itself when the error condition is removed. This mode is always used when the temperature is compared against the TCRIT limit. In TCRIT only mode the EVENT_n pin will only be asserted if the measured temperature exceeds the TCRIT limit. It will remain asserted until the temperature drops below the TCRIT limits minus the TCRIT hysteresis. Serial Presence-Detect EEPROM Operation DDR4 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 512-byte JEDEC JC-42.4 compliant EEPROM that is segregated into 4, 128-byte, write protectable blocks. The SPD content is aligned with these blocks as follows. Block Range Discription x000-0x07F Configuration and DRAM Parameters x080-0x0FF Module Parameters x100-0x13F Reserved - All bytes coded as 0x x140-0x17F Manufacturing Information x180-0x1FF End User Programmable The first 384 bytes are programmed by Micron to comply with JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR4 SDRAM Modules." The remaining 128 bytes of storage are available for use by the customer. The EEPROM resides on a two-wire I 2 C serial interface and is not integrated with the memory bus in any manner. It operates as a slave device in the I 2 C bus protocol, with all operations synchronized by the serial clock. Transfer rates of up to 1 MHz are achievable at V. CTL0205.fm - Rev. 06/25/ Micron Technolog Inc

12 Temperature Sensor with Serial Presence-Detect EEPROM Micron implements reversible software write protection on DDR4 SDRAM-based modules. This prevents the lower 384 bytes (bytes 0 383) from being inadvertently programmed or corrupted. The upper 128 bytes remain available for customer use and unprotected. CTL0205.fm - Rev. 06/25/ Micron Technolog Inc

13 Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device s data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 6: Absolute Maximum Ratings Symbol Parameter Min Max Units Notes V DD V DD supply voltage relative to V 1 V D V D supply voltage relative to V 1 V PP Voltage on V PP pin relative to V 2 V IN, V OUT Voltage on any pin relative to V Table 7: Operating Conditions Symbol Parameter Min Nom Max Units Notes V DD V DD supply voltage V 1 V PP DRAM activating power supply V 2 V REFCA(DC) Input reference voltage command/address bus 0.49 x V DD 0.5 x V DD 0.51 x V DD V 3 IV TT Termination reference current from V TT ma V TT Termination reference voltage (DC)?command/ 0.49 x V DD x V DD 0.51?x V DD V 4 address bus 20mV +20mV I I Input leakage current; Any input excluding ; 0V < μa 5 V IN < 1.1V I I Input leakage current; 3 +3 μa 6,7 I I/O leakage; 0V < V IN < V DD 4 +4 μa I OZpd Output leakage current; V OUT = V DD ; are 5 μa disabled I OZpu Output leakage current; V OUT = ; and ODT 50 µa are disabled; ODT is disabled with ODT input HIGH I VREFCA V REFCA leakage; V REFCA = V DD /2 (After DRAM is initialized) 2 +2 μa 7 Notes: 1. V D balls on DRAM are tied to V DD. 2. V PP must be greater than or equal to V DD at all times. 3. V REFCA must not be greater than 0.6 V DD. When V DD is less than 500mV, V REF may be less than or equal to 300mV. 4. V TT termination voltages in excess of specification limit will adversely affect command and address signals' voltage margins, and reduce timing margins. 5. Command and address inputs are terminated to V DD /2 in the registering clock driver. Input current is dependent on termination resistance set in the registering clock driver. 6. Tied to ground. Not connected to edge connector. 7. Multiply by number of DRAM die on module. CTL0205.fm - Rev. 06/25/ Micron Technolog Inc

14 Electrical Specifications Table 8: Thermal Characteristics Parameter/Condition Value Units Symbol Notes Operating case temperature 0 to +85 C T C 1, 2, 3 Commercial >85 to +95 C T C 1, 2, 3, 4 Normal operating temperature range 0 to +85 C T OPER 5, 6 Extended temperature operating range (optional) >85 to 95 C T OPER 5, 6 Notes: 1. MAX operating case temperature. T C is measured in the center of the package. 2. A thermal solution must be designed to ensure the DRAM device does not exceed the maximum T C during operation. 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T C during operation. 4. If T C exceeds 85 C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9µs interval refresh rate. 5. The refresh rate is required to double when 85 C < T OPER 95 C. 6. For additional information, refer to technical note TN-00-08: "Thermal Applications" available on Micron's web site. CTL0205.fm - Rev. 06/25/ Micron Technolog Inc

15 Electrical Specifications DRAM Operating Conditions Recommended AC operating conditions are given in the DDR4 component data sheets. Component specifications are available on Micron s web site. Module speed grades correlate with component speed grades, as shown below. Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the edge connector of the module, not the DRAM. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. CTL0205.fm - Rev. 06/25/ Micron Technolog Inc

16 Electrical Specifications I DD Specifications Table 9: DDR4 I DD Specifications and Conditions - 4GB Values are for the MT40A1G4 DDR4 SDRAM only and are computed from values specified in the 4Gb (1 Gig x 4) component data sheet Parameter Symbol Units One bank ACTIVATE-PRECHARGE current I 1 DD ma One bank ACTIVATE-PRECHARGE, Word Line Boost,I PP current I 1 PP ma One bank ACTIVATE-READ-PRECHARGE current I 1 DD ma Precharge standby current 2 I DD2N ma Precharge standby ODT current I 1 DD2NT ma Precharge power-down current I 2 DD2P ma Precharge quiet standby current 2 I DD2Q ma Active standby current I 2 DD3N ma Active standby I PP current I 2 PP3N ma Active power-down current I 2 DD3P ma Burst read current 1 I DD4R ma Burst read ID current I 1 D4R ma Burst write current I 1 DD4W ma Burst refresh current (1x REF) 1 I DD5B ma Burst refresh I PP current (1 x REF) I 1 PP5B ma Self refresh current: Normal temperature range (0 C to +85 C) I 2 DD6N ma Self refresh current: Extended temperature range (0 C to +95 C) 2 I DD6E ma Self refresh current: Reduced temperature range (0 C to +45 C) I 2 DD6R ma Auto self refresh current (25 C) I 2 DD6A ma Auto self refresh current (45 C) 2 I DD6A ma Auto self refresh current (75 C) I 2 DD6A ma Bank interleave read current I 1 DD ma Bank interleave read I PP current 1 I PP ma Maximum power-down current I 2 DD ma Notes: 1. One module rank in the active I DD/PP, the other rank in I DD2P/PP3N. 2. All ranks in this I DD/PP condition. CTL0205.fm - Rev. 06/25/ Micron Technolog Inc

17 Registering Clock Driver Specifications Registering Clock Driver Specifications Table 10: Registering Clock Driver Electrical Characteristics DDR4 RCD01 devices or equivalent Parameter Symbol Pins Min Nom Max Units DC supply voltage V DD V DC reference voltage V REF V REFCA 0.49 x V DD 0.5 x V DD 0.51 x V DD V DC termination V TT V REF -40mV V REF V REF + 40mV V voltage High-level input V IH. CMOS DRST_n 0.65 x V DD V DD V voltage Low-level input V IL. CMOS x V DD V voltage DRST_n pulse width t INIT_Power_sta ble 1.0 μs AC high-level output voltage AC low-level output voltage AC differential output high measurement level (for output slew rate) AC differential output low measurement level (for output slew rate) V OH(AC) All outputs except ALERT_n V TT + (0.15 x V DD ) V V OL(AC) VTT + (0.15 x V DD ) V V OHdiff(AC) Yn_t - Yn_c, BCK_t - BCK_c +0.3 x V DD mv V OLdiff(AC) -0.3 x V DD mv Notes: 1. Timing and switching specifications for the register listed are critical for proper operation of the DDR4 SDRAM RDIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Please refer to JEDEC RCD01 specification for complete operating electrical characteristics. RCD parametric values are specified for device default control word settings, unless otherwise stated. The RC0A control word setting does not affect parametric values. CTL0205.fm - Rev. 06/25/ Micron Technolog Inc

18 Temperature Sensor with Serial Presence-Detect EEPROM Temperature Sensor with Serial Presence-Detect EEPROM Serial Presence-Detect Data The temperature sensor continuously monitors the module's temperature and can be read back at any time over the I 2 C bus shared with the SPD EEPROM. Refer to JEDEC JC EE1004 and TSE2004 device specification for complete details. For the latest SPD data contact your Micron Consumer Products Group Sales Representative. Table 11: Serial Presence-Detect EEPROM Operating Conditions Parameter/Condition Symbol Min Max Units Supply voltage V DDSPD V Input low voltage: Logic 0; All inputs V IL 0.5 V DDSPD V Input high voltage: Logic 1; All inputs V IH V DDSPD V DDSPD V Output low voltage: 3 ma sink current V DDSPD >2V V OL 0.4 V Input leakage current: (SCL, SDA) V IN = V DDSPD or SPD I LI ±5 µa Output leakage current: V OUT = V DDSPD or SPD, SDA in High-Z I LO ±5 µa Table 12: Serial Presence-Detect EEPROM Serial Interface Timing Parameter/Condition Symbol Min Max Units Clock frequency t SCL khz Clock pulse width high time t HIGH 260 ns Clock pulse width low time t LOW 500 ns Detect Clock Low Timeout t TIMEOUT ms SDA rise time t R 120 ns SDA fall time t F 120 ns Data-in setup time t SU:DAT 50 ns Data-in hold time t HD:DI 0 ns Data-out hold time t HD:DAT ns Start condition setup time t SU:STA 260 ns Start condition hold time t HD:STA 260 ns Stop condition setup time t SU:STO 260 ns Time the bus must be free before a new transition can start t BUF 500 ns WRITE time t W 5 ms Warm power cycle time off t POFF 1 ms Time from power on to first command t INIT 10 ms CTL0205.fm - Rev. 06/25/ Micron Technolog Inc

19 Module Dimensions Module Dimensions Figure 3: 288-Pin DDR4 RDIMM FRONT VIEW (5.256) (5.244) 3.9 (0.153) MAX U1 U2 U3 U4 U5 U6 U7 U8 U9 U (0.03) R (8X) 2.50 (0.098) D (2X) 4.8 (0.189) U11 U13 U15 U12 U14 U16 U17 U18 U19 U (0.374) 16.1 (0.63) (1.236) (1.224) 2.20 (0.087) 3.35 (0.132) (2X) PIN (2.84) 0.85 (0.033) 0.60 (0.0236) 0.75 (0.030) R PIN (0.055) 1.39 (0.054) (4.99) BACK VIEW 1.25 (0.049) x 45 (2X) U21 U22 U23 U24 U25 U26 U27 U28 U (0.57) 8.0 (0.315) 3.15 (0.124) U30 U31 U32 U33 U34 U36 U38 U35 U (0.118) (4X) 0.5 (0.0197) PIN (0.4) 5.95 (0.234) 10.2 (0.4) PIN (0.90) (0.9) 25.5 (1.0) 28.9 (1.14) Notes: (2.21) 64.6 (2.54) 1..All dimensions are in millimeters (inches); MAX/MIN or typical () where noted. 2. The dimensional diagram is for reference only and showing one possible configuration E. Commercial Ct., Meridian, ID 83642, Tel: , Internet: Micron Technology, Inc. All rights reserved. Micron and the Crucial logo are registered trademarks of Micron Technology, Inc. TwinDie is a trademark of Micron Technology, Inc. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. All other brands and names used herein are the property of their respective owners. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.. CTL0205.fm - Rev. 06/25/ Micron Technology Inc.