isppac-powr607 Evaluation Board User s Guide

Transcription

1 isppac-powr0 Evaluation Board User s Guide May 00 Revision: EB8_0.0

2 isppac-powr0 Introduction Lattice Semiconductor s Power Manager II isppac -POWR0 device simplifies power supply design by integrating the analog and digital functions of power supply management (sequencing, monitoring, reset generation into a single device). This device provides designers with a rich set of features: precision comparators with a built-in voltage reference, MOSFET drivers and a programmable logic device (PLD) for sequencing and supervisory logic functions or reset control. Configuration for all subsystems in the isppac-powr0 device is stored in non-volatile E CMOS memory. Programming is performed via the industry-standard JTAG IEEE 9. interface. PAC-POWR0-EV Evaluation Board The PAC-POWR0-EV evaluation board (Figure ) allows the designer to quickly configure and evaluate the isp- PAC-POWR0 device on a fully assembled printed-circuit board. The board supports a -pin QFN package, pads for user I/O, a JTAG programming cable connector, LEDs and switches. JTAG programming signals can be generated by using an ispdownload programming cable connected between the evaluation board and a PC s parallel (printer) port. Both analog and digital features of the isppacpowr0device can be easily configured using PAC-Designer software. Figure. PAC-POWR0-EV Evaluation Board Programming Interface Lattice Semiconductor s ispdownload cable can be used to program the isppac-powr0 device on the evaluation board. This cable plugs into a PC-compatible s parallel port connector, and includes active buffer circuitry inside its DB- connector housing. The other end of the ispdownload cable terminates in an 8-pin 0.00 pitch header connector, which plugs directly into a mating connector, (J) provided on the PAC-POWR0-EV evaluation board. Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispdown- LOAD Cable. Always connect the ispdownload Cable's GND pin (black wire), before connecting any other JTAG pins. Failure to follow these procedures can in result in damage to the isppac-powr0 device and render the board inoperable.

3 isppac-powr0 Power Supply Considerations The isppac-powr0 device operates with analog and digital core power supplies of.v, To simplify evaluation work, the evaluation board was designed to operate from a single.v to 9V power supply, which may be brought in through a standard mm power plug (J - center tip positive). The evaluation board provides a linear regulator to provide the appropriate operating voltages for the isppacpowr0 device, as well as reverse polarity protection. The kit comes with a battery and cable that plugs into the connector at J and provides power with a 9V battery, see Figure. If it is desired to test the current in the power down mode of the isppac-powr0, the link between pins and of J should be cut (please refer to Appendix A). Otherwise, approximately ma will be drawn when the device is in power down mode. Figure. 9V Battery Power Interface Input/Output Connections Connectors are provided for key functions and test points on this evaluation board, as shown In Figure. The JTAG programming cable is connected to a header (J) in the lower right corner of the board. Access to the isppac-powr0 device s I/O pins is available along the left edge of the assembly, where a x block of pads (J)supports the attachment of test probes or a ribbon-cable connector. In addition, there is an array of 0 proto-type holes for interfacing. Two momentary switches, S and S, are provided on the evaluation board. They are connected to IN_PWRDN and IN respectively. Several LEDs are also provided on the evaluation board to indicate proper function and as aids to debugging. LED D indicates that the on-board.v supply is powered up. LED D is connected to the isppacpowr0 device s line, and will briefly flash when downloading, indicating that download data has made it to the device. Five LEDs are also provided on digital outputs OUT through OUT so that a user may easily view the progress of Sequence, Monitor, Reset programs run on the evaluation board. Demo Sequence and Reprogramming This evaluation board is shipped from the factory pre-programmed with the isppac_powr0_led_blinker.pac sequence from PAC-Designer s library. The IN_PWRDN button must be depressed in order t bring the isppac- POWR0 device out of its power down mode. The programmed sequence will cause the LEDs to flash for about six seconds, and then the device will revert to the power down mode. In order to reprogram the isppac-powr0, it must be brought out of power down mode. Thus, the IN_PWRDN button must be depressed immediately before beginning a download to the device from PAC-Designer or ispvm.

4 isppac-powr0 Bill of Materials for the isppac-powr0 Evaluation Board Qty. Ref Des Description Dig-Key # or Equivalent C, C 0µF 0V Tant. SMD capacitor 8---ND C, C,C,C,C8 0.µF SMD00 ceramic capacitor PCCCT-ND D Diode Schottky 0V A SODFl MBR0VLSFT0SCT-ND R k resistor SMD KACT-ND D GREEN LED SMD ND D,,,,, 8 RED LED SMD ND J.mm power connector CP-0B-ND RN Res Net k -pin SOIC 8--RK-ND R, R 0k resistor SMD 080-0KACT-ND R, R.k resistor SMD KACT-ND J Header pos.00 vert Gold Break into 8-pin used for JTAG WM-ND SW, SW Momentary push-button switches P088SCT-ND U isppac-powr0 Lattice Semiconductor U IC.V LDO REG SOIC 9-8--ND N/A PCB by. isppac-powr0 Rev- Ordering Information Part Number: PAC-POWR0-EV References isppac-powr0 Data Sheet Technical Support Assistance Hotline: -800-LATTICE (North America) (Outside North America) isppacs@latticesemi.com Internet: Revision History Date Version Change Summary May Initial release. 00 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

5 isppac-powr0 Appendix A. Schematics The following figures comprise the schematics for the isppac-powr0 evaluation board. Figure shows the device schematic and JTAG interface, while Figure shows the on-board power-supply circuitry and the LED display. Figure. isppac-powr0 Device Schematic VCC is jumpered to.v at pins and of J on the backside of the board. To measure the device power down current, cut the jumper trace on the backside of the board and connect an ammenter between pins and. In addition, cut the jumper on the backside betweeen pins and of J to disconnect VCCJ. Replace with jumper blocks for normal operation..v J VCC VCCJ D U D VCC VCCJ IN_OUT IN_OUT IN_OUT IN_OUT IN_OUT IN IN_PWRDN VMON VMON VMON VMON VMON VMON 0 HVOUT HVOUT IN_PWRDN 9 isppac-powr00 IN VMON IN 8 IN IN/OUT IN_OUT VMON TDI IN/OUT IN_OUT 8 IN_OUT 8 VMON R 00 TDI IN/OUT IN_OUT 0 VMON TMS IN/OUT 9 IN_OUT VMON TCK TMS IN/OUT 0 C VMON R 00 TCK C GNDD GNDA VMON VMON VMON VMON VMON VMON VCCD VCCA VCCJ HVOUT HVOUT 0 HVOUT HVOUT HEADER X VCC C 0pF TDI R.k 8 J VCC VCCJ TMS B B TCK C 00n C 00n C8 00n R.k JTAG Interface A A Title isppac-powr00 Size A Document Number isppac-powr00 Evaluation Board Rev D ate: Sheet of

6 isppac-powr0 Figure. Power Supply and LEDs J PWR JACK Regulator D TPS R D D IN OUT MBR0p IN OUT k C 00n U.V GND Enb C 0u 0V C 00n C 0u 0V D PWR (GREEN).V RN C C LEDs D9 OUT D0 OUT D OUT k X D OUT D OUT D IN_OUT IN_OUT IN_OUT B IN_OUT B IN_OUT IN_PWRDN IN R 0k SW IN_PWRDN R 0k SW IN A A Title Power Supply and LEDs Size A Document Number isppac-powr00 Evaluation Board Rev D ate: Sheet of