MachXO Starter Evaluation Board User s Guide

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Candace Dean
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1 MachXO Starter Evaluation Board April 00 Revision: ebug_0.

2 Introduction The Lattice provides a convenient platform to evaluate, test and debug user designs. The board features a Lattice MachXO cross-over programmable logic device in a 0-pin TQFP package, power input jacks, a MHz clock oscillator and I/O connections. The Lattice MachXO I/Os are connected to a rich variety of interfaces, including switches (momentary and ON/OFF), s, 0. headers and PCB test points. Features Lattice MachXO device Prototyping area Access to user I/Os Independent voltage control for core and I/O MHz on-board oscillator Status s Input switches Pads for optional board expansion. AC adapter Lattice ispdownload cable, to download programming files to the MachXO device. Software Support Lattice isplever design tools (release.0 SP or later) for HDL design targeting the MachXO device. The MachXO device is supported in the isplever-starter software, available from ispvm System, for device programming. Available for download from Electrical, Mechanical and Environmental Specifications The nominal board dimensions are. inches by. inches. The environmental specifications are as follows: Operating temperature: 0ºC to ºC Storage temperature: -0ºC to ºC Humidity: < % without condensation VDC input (+/- %) up to A Figure shows the board outline.

Figure. MachXO Starter Outline MachXO I/O Access Prototype Area MachXO I/O Access Expansion Header Bank Expansion Header MachXO I/O Access.V LDO DIP Switch DC Input.

3 Figure. MachXO Starter Outline MachXO I/O Access Prototype Area MachXO I/O Access Expansion Header Bank Expansion Header MachXO I/O Access.V LDO DIP Switch DC Input.V LDO Adjustable LDO MHz Oscillator Switches JTAG Interface Resources relating to the Lattice, including user documentation updates and sample programs, can be found at Click on the appropriate link for the Lattice. Lattice MachXO Device The features a Lattice MachXO device with a.v DC core. The board is populated with a MachXO device in a plastic 0-pin TQFP package. The allows for density migration to other Lattice MachXO densities in the 0 TQFP package, with either.v or.v cores. A complete description of this device can be found in the Lattice MachXO Family Data Sheet on the Lattice web site at Device Core and I/O Voltage Core Voltage The MachXO is available with either.v or.v core voltage devices. Boards populated with a.v DC core device will allow operation of the core between.v and.v DC. The core voltage is fixed at.v during manufacturing. The core voltage may be changed from the fixed.v rail to the adjustable voltage rail by changing the 0 ohm resistor at R to R. Boards populated with a.v core device operate at.v only, with the core voltage supply fixed at.v during manufacturing. Refer to the board silkscreen outline in the appendix for component location.

4 I/O Voltage The Lattice MachXO device has two sysio banks; each is capable of supporting multiple I/O standards. Each sysio bank has its own I/O supply voltage (V CCIO ), which allows each I/O bank to be completely independent. Refer to the Lattice MachXO Family Data Sheet for additional information about supported I/O standards. This data sheet can be downloaded from The allows individual control of each I/O bank capable of supporting V CCIO between.v and.v. The board includes 0 ohm resistors which allow the user to select.v or an adjustable voltage between.v and.v. During manufacturing, the V CCIO banks are set to.v. The adjustable voltage rail (ADJ) is fixed at.v during manufacturing. Table shows the required resistor population to set the appropriate core and I/O voltages. Table. Voltage Jumpers/Settings for V CCIO and VCC_CORE Device Clocks The provides a variety of ways to supply clock signals to the MachXO device. These include a MHz on-board crystal oscillator, expansion connectors and 0. header pins. The on-board oscillator is connected to MachXO pin, which is a dedicated clock input. The oscillator can be enabled/disabled via pull up (R) /down (R), or through pin of the MachXO. Dedicated clock inputs are also available on the following pins:, and. These pins are brought out to test points on the PCB, and to the expansion headers. Device I/O Banks MachXO I/O banks 0 and are general purpose I/O banks connected to a combination of test pads, switches, s and two board expansion headers. The switches consist of two user defined push-button switches and an - position DIP switch. Both types of switches are pulled up to the associated V CCIO voltage with K Ω resistors (when in the up position) and connected to when activated (in the down position). s are active (lit) when the device I/O is low. Table details the I/O banks 0 and connections. I/Os listed as GPIO (General Purpose I/O) are connected to 0. centered plated through hole, with an associated hole and pads for a pull-up or pull-down resistor. The pull-up pads are located on the component side of the PCB, and the pull-down pads on the solder side. These pads are sized for 00 components. Each device I/O is connected to a test point on the PCB. The PCB silkscreen is marked with the corresponding MachXO 0-TQFP I/O pin. Table. Device I/O Connections.V ADJ.V VCC_CORE R (default ) R R(default*) V CCIO0 R (default) R N/A V CCIO R (default) R N/A. Default resistor is based on device core I/O voltage,.v for C devices, and.v for E devices. Pin # Pin Name Expansion Connect Function/PCB Connect PLA J- GPIO PLB J- GPIO PLA J- GPIO PLB J- GPIO PLC J- GPIO PLD J- GPIO PLA J- GPIO PLB J- GPIO PLA J- GPIO

5 Table. Device I/O Connections (Continued) Pin # Pin Name Expansion Connect Function/PCB Connect PLB J- GPIO PLC J- GPIO PLD/GSR_N J- GPIO PLA J- GPIO PLB/TSALL J- GPIO PLA J- GPIO PLB J-0 GPIO PLC J- GPIO 0 PLD J- GPIO PLA J- GPIO PLB J- GPIO PLA J- GPIO PLB J- GPIO PBA J- GPIO 0 PBB J- GPIO PBC J- GPIO PBD J-0 GPIO PCLKT_/PBA J- Y PBB J- GPIO PCLKT_0/PBC J- GPIO PBD J- GPIO PBA J- GPIO PBB J- OSC_EN PBC J- SW PBD J- SW PBA J- GPIO SLEEPN J- GPIO/SW PBC J- GPIO 0 PBD J-0 GPIO PRB J- GPIO PRA J- GPIO PRB J- GPIO PRA J- GPIO PRD J- SW- PRC J- SW- PRB J-0 SW- PRA J- SW- PRB J- SW- PRA J- SW- PRD J- SW- PRC J- SW- PRB J- D PRA J- D PRB J- D

6 Table. Device I/O Connections (Continued) Pin # Pin Name Expansion Connect Function/PCB Connect Expansion Header PRA J- D PRD J-0 D 0 PRC J- D PRB J- D PRA J- D PRB J- D PRA J- GPIO PTC J- GPIO PTB J- GPIO PTA J- GPIO 0 PTF J- GPIO PTE J- GPIO PTD J- GPIO PTC J- GPIO PCLKT0_/PTB J- GPIO PCLKT0_0/PTA J- GPIO PTD J- GPIO PTC J- GPIO PTB J- GPIO PTA J- GPIO PTF J- GPIO PTE J- GPIO PTD J-0 GPIO PTC J- GPIO PTB J- GPIO 0 PTA J- GPIO. By shorting R0 with a 0 ohm resistor. The MachXO Starter board includes two Samtec board-to-board connector footprints (connectors not included) for expansion purposes. All MachXO I/O pins, JTAG signals and board voltages are connected to these pads. Refer to Table for MachXO connections to the expansion headers. Programming pins can be referenced in the Programming Headers sections of this guide. Power connections are listed in Table. Table. Expansion Connector Power Connections Power Supply Expansion Connector Pin.V J-,J-,J-,J-, J-,J-,J-, J-,J-,J-0 ADJ J-,J-,J-,J-.V J-,J-,J-, J-,J-0 J-,J-,J-, J-,J-,J-, J-,J-0, J-, J-,J-,J-0, J-,J-,J-, J-,J-,J-, J and J Center The connectors are Samtec part number QTH-00-0-F-D-A. Mating connectors are Samtec part number QSH A mechanical drawing with placement dimensions is available from Lattice.

7 Prototype Area The contains a 0. x.0 plated through hole prototype area. The holes are spaced on 0. centers and are not connected to any MachXO device pins. Programming Headers A x programming header is provided on the, providing access to the MachXO JTAG port. The header is compatible with all Lattice ispdownload cables. The pinout for the header is provided in Table. Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispdown- LOAD Cable. Always connect the ispdownload Cable's pin (black wire), before connecting any other JTAG pins. Failure to follow these procedures can in result in damage to the MachXO device and render the board inoperable. An ispdownload cable is included with purchase of the isplever design tools. Cables may also be purchased separately from Lattice. Visit the Lattice web store to learn more at: Table. JTAG Programming Header Connections JTAG Programming Function JP Pin Number (x) Mach XO Device Pin Expansion Connector Pin Power Setup +.V N/A N/A J- J- N/C N/A N/A N/C N/A N/A J- N/A N/A J- N/C N/A N/A N/C N/A N/A. Please note that some versions of the may have an incorrect silkscreen marking for these pins on the printed circuit board. Please follow the connections guidelines in Table, and not the silkscreen markings on the board. Power is supplied to the PCB via the supplied V AC/DC transformer. The DC input jack is a.mm, positive tip size connector. Input voltage should not exceed V DC. 00mA low dropout regulators provide V CC core and V CCIO voltages. The adjustable voltage regulator output can be modified by changing the value of resistor R. The equation for calculating V ADJ is as follows: V ADJ =. * ( + R/) Table shows some common voltages, and the appropriate resistor value for setting each voltage. Resistance given is for the closest standard value. Resistor pads are 00 component size.

8 Table. Adjustable Voltage Resistor Values Ordering Information Description ADJ Voltage R Resistor Value.V 00 Ω.V Ω.V Ω.V Ω.V Ω Ordering Part Number China RoHS Environment-Friendly Use Period (EFUP) MachXO C Evaluation Board - Starter LCMXOC-S-EV Technical Support Assistance Hotline: -00-LATTICE (North America) (Outside North America) techsupport@latticesemi.com Internet: Revision History Date Version Change Summary Previous Lattice releases. March Added Ordering Information section. April Added important information for proper connection of ispdownload (Programming) Cables. 00 Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

9 Appendix A. PCB Schematics Figure. Expansion Port D D C C B B A A 0 SW SW SW SW SW SW SW SW0 IO IO IO IO IO IO IO IO IO IO IO0 IO IO IO IO IO0 IO IO IO IO0 IO IO IO IO IO0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO0 IO IO IO IO [..0] SW[..0] IO[..0] [..0] SW[..0] IO[..0] +.V +.V VCC_ADJ +.V Title Size Document Number Rev Date: Sheet of XO-STR-SCH B MachXO Starter PCB - Expansion Port A Wednesday, June, 00 AB AB CB DB BB DB BB CB AB CB DB BB AB DB AB BB CB AB CB DB BB CB AB DB AB BB BB DB AB CB BB0 CB DB DB BB CB AB AB0 BB BB CB DB AB CB DB AB CB0 BB BB DB AB BB CB CB DB DB BB AB CB AB BB DB0 BB CB DB AB DB CB CB AB DB BB AB CB BB AB CB J QTH-00-0-F-D-TR BB DB DB J QTH-00-0-F-D-TR

10 Figure. D D C C B B A A IO SW SW SW SW SW SW IO IO IO IO IO IO IO0 IO IO0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO0 IO IO IO IO IO IO IO IO IO 0 SW SW SW SW SW SW SW SW0 IO IO0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO0 IO IO IO IO IO IO IO IO IO0 IO IO IO IO0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO0 IO IO IO IO IO IO IO IO0 IO IO IO IO IO IO IO IO IO0 IO IO IO IO IO IO IO 0 SW SW0 IO IO0 IO IO IO IO IO0 IO IO IO IO IO IO IO IO IO [..0] SW [..0] IO[..0] IO IO [..0] SW [..0] IO[..0] +.V +.V +.V +.V VCCIO VCCIO VCCIO VCCIO VCCIO VCC_CORE VCC_CORE Title Size Document Number Rev Date: Sheet of B MachXO Starter PCB B W ednesday, June, 00 R _ R R IO IO _ IO R 0 R IO IO R D R R R K R R _ R R C 0.uF _ R R R IO IO D R _ R _ R IO R 0 SW IO IO R IO R R D R R IO R R IO R R IO0 _ R _ IO IO _ IO R R K IO _ R SW SW DIP- CTS 0- R R D _ SW EVQ-QWP0W _ R0 IO IO R0 R R R R _ R R _ R _0 R IO R IO _ R 0 IO R R R R R R _ IO R IO R R R K _0 R R K _ R0 IO _ R IO _ R R 0 _ R R R K IO R R IO IO IO _ R R IO R 0 IO _ IO R0 _ R R R R R R R R R IO R0 R R R TQFP 0 U MACHXO PRD PLB PBA PBB 0 PBC PBD VCC PBA/PCLKT_ PBB PBC/PCLKT_0 PBD 0 VCCIO IO PBA PBB PBC PBD PBA SLEEPN PBC PBD 0 PRB PRA PRB PRA PRD PRC PRB PRA PRB PLD PLA PLB PLA PRA PRB PRA PRB PRC PRD IO0 PRA 0 VCCIO PLB PLC PLA PLA PLA IO PLC PLA PLB PLB PLD 0 PLD/GSR_N PLB PLA PLC VCCIO PLB/TSALL PLA IO PLB PTA PTB PTC PRA IO0 PRB PRA PRB PRC 0 PTB PTA 0 PCLKT0_/PTB PTC PTD PTE PTF 0 PTC PTD PTE PTF PTA IO0 PTB VCC 0 PTC VCCAUX PTD PCLKT0_0/PTA D _ R R R R0 IO _ IO0 _ IO R 0 R _ R R R D _ R R R IO0 IO R IO _ R R K R K R R IO _ IO R IO0 _ R IO R Y.MHz EN OUT VCC R IO R _ R0 R K _0 R IO R IO D R R R R R _ IO R K R _ R R K R 0 IO D R0 R IO R IO0 R R R R _ IO R R IO _0 IO R 0 R IO R0 _0 R R IO R0 IO IO D _ R R 0 R K IO _ IO _ R _ R R JP HEADERX R R IO R XO-STR-SCH

11 Figure. Power Section +. V D D PW R JACK J +. V V I N V I N VI N VO UT +. V + C uf C C V I N U RCX /S OT VI N VO UT TA B V CC_ AD J +. V V CC_ AD J V CCI O0 R 0 R GN D + C uf V CCI O 0 R U RC X/ SOT C + + C uf U RC X/ SOT VI N VO UT 0uF R 0 R 0 B R B D +. V R * 0 R* R00 VC C_ CORE RE D 0 R RE D GN D D 0 TA B TA B GN D + C uf R TP 0 + C 0uF R *NOTE: Silkscreen markings are reversed for R and R on boards marked as Rev. B. +. V VC C_ CORE V CCI O V CCI O0 C C C 0 C C C C C C C A 0. uf 0. uf 0. uf 0. uf 0. uf 0. uf 0. uf 0. uf 0. uf 0. uf A Ti tl e MachXO Starter PCB Power Section Si ze Do cument Number Re v A XO-STR-SCH B Date : We dn esday, June, 00 Sheet of

12 Appendix B. PCB Layout Diagrams Figure. Layout Diagrams Figure. Top Silkscreen Figure. Component Side Layout Figure. Solder Side Layout Figure. Bottom Silkscreen

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