MMCFPGA1200 FIELD PROGRAMMABLE GATE ARRAY I/O PERIPHERAL BOARD (FPGA IPB) USER S MANUAL

Transcription

1 nc. MMCFPGA1200UM/D Rev 1 JANUARY 1999 MMCFPGA1200 FIELD PROGRAMMABLE GATE ARRAY I/O PERIPHERAL BOARD (FPGA IPB) USER S MANUAL MOTOROLA Inc., 1998, 1999; All Rights Reserved

2 nc. Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the Motorola logo are registered trademarks of Motorola Inc. M CORE is a trademark of Motorola, Inc. Other trademarks belong to their respective owners. Motorola Inc. is an Equal Opportunity/Affirmative Action Employer. Caution: ESD Protection M CORE development systems include open-construction printed circuit boards that contain static-sensitive components. These boards are subject to damage from electrostatic discharge (ESD). To prevent such damage, you must use static-safe work surfaces and grounding straps, as defined in ANSI/EOS/ESD S6.1 and ANSI/EOS/ESD S4.1. All handling of these boards must be in accordance with ANSI/EAI 625.

3 nc. CONTENTS CONTENTS CHAPTER 1 INTRODUCTION 1.1 FPGA IPB Features System and User Requirements FPGA IPB Layout Foot Placement CHAPTER 2 CONFIGURATION AND SETUP 2.1 Configuring and Using Your FPGA IPB Downloading Directly to the FPGA Device Downloading Via FLASH Memory Using the Breadboard Area Using the Spare Pads Connecting the FPGA and CMB Boards Configuring Your Software CHAPTER 3 DEVELOPING APPLICATIONS 3.1 Application Development Steps Using the FPGA Programmer CHAPTER 4 MAPI CONNECTOR INFORMATION 4.1 MAPI Connectors (P1/J1, P2/J2, P3/J3, P4/J4) Reference Tables INDEX...index-1 MMCFPGA1200UM/D Rev 1 iii

4 nc. CONTENTS FIGURES 1-1 FPGA IPB Foot Locations (on Board Bottom) FPGA Programmer Main Screen Protocol Selection FPGA Board Flash Contents Display MAPI Connector P1/J1 Pin Assignments MAPI Connector P2/J2 Pin Assignments MAPI Connector P3/J3 Pin Assignments MAPI Connector P4/J4 Pin Assignments TABLES 1-1 FPGA IPB Design Specifications Setting FPGA IPB Components MAPI Connector P1/J1 Signal Descriptions MAPI Connector P2/J2 Signal Descriptions MAPI Connector P3/J3 Signal Descriptions MAPI Connector P4/J4 Signal Descriptions Pin Mapping: MAPI Connector J1, FPGA Device, CMB Pin Mapping: MAPI Connector J2, FPGA Device, CMB Pin Mapping: MAPI Connector J3, FPGA Device, CMB Pin Mapping: MAPI Connector J4, FPGA Device, CMB FPGA Pins/Signals, MAPI Pins, CMB1200 Signals/Pins CMB1200 Signals/Pins, MAPI Pins, FPGA Signals/Pins Available MAPI Pins Record of Changes...last page iv Rev 1 MMCFPGA1200UM/D

5 nc. INTRODUCTION CHAPTER 1 INTRODUCTION This user s manual explains connection, configuration, and operation information for the Motorola s Field Programmable Gate Array I/O Peripheral Board (FPGA IPB). The FPGA IPB lets you easily develop peripheral applications to be embedded in an M CORE MCU. The board includes an Altera Flex resident FPGA device and comes with Altera MAX+plusII development software, so that you can use Verilog, VHDL, or schematics to develop your applications. Your designs can equate to as many as 100,000 Altera logic gates. The FPGA IPB works with Motorola s MMCCMB1200 Controller and Memory Board (CMB). As all power and data connections are through the MAPI connectors of the two boards, there are no cable connections to the FPGA IPB. 1.1 FPGA IPB FEATURES NOTE The silk-screen marking of your board identifies it as an FPGA01. This is correct for the FPGA IPB. Your FPGA IPB: Lets you easily design peripherals to be used inside an M CORE microcontroller unit. Lets you prototype your designs quickly. Lets you try different design ideas in a real-world environment. Lets you develop applications in any of three methods: Verilog, VHDL, or schematic. Uses an Altera FPGA device and Altera MAX+plusII development software. Derives power and data from a Motorola CMB, via MAPI 400 connector interface rings. Has simple hardware controls: two switches and one jumper header. MMCFPGA1200UM/D Rev 1 1-1

6 nc. INTRODUCTION Has LED indicators for 3.3-volt power, 5-volt power, configuration errors, and configuration done. Has a 3.25-square-inch, through-hole breadboard area, so that you easily can add custom components to your designs. This breadboard area has convenient connection points for ground, 3.3-volt power, and 5-volt power. Immediately adjacent to the breadboard area are connection points for key signals of the FPGA device. The breadboard area accommodates prototype components that need through-hole mounting. Adjacent pads accommodate surface-mount components of 25mm or 50mm pitch. 1.2 SYSTEM AND USER REQUIREMENTS To use the FPGA IPB, you need an IBM PC or compatible computer, running the Windows 95 or WindowsNT (version 4.0) operating system. The computer requires a Pentium (or equivalent) microprocessor, 32 megabytes of RAM, 50 megabytes of free hard-disk space, a CD-ROM drive, an SVGA color monitor, and an RS232 serial-communications port. The FPGA kit includes a Motorola MMCCMB1200 Computer and Memory Board (CMB), which plugs onto the FPGA IPB. Your FPGA IPB obtains its 5- volt (± 0.25 volt) input power from the CMB1200, which also provides data connections for the FPGA IPB. The CMB1200 also must provide an 8- to 64- megahertz clock signal to the FPGA, on the CLKOUT pin (pin A14). (To have the CMB1200 provide this signal, you must configure the reset source/chip configuration register appropriately, as the MMC2001 reference manual explains.) To get the most from your FPGA IPB, you should be an experienced MCU applications developer, with some experience using the Verilog development language, the VHDL development language, or the schematic development method. 1.3 FPGA IPB LAYOUT Figure 1-1 shows the layout of the FPGA IPB. Connectors P1 through P4, on the top of the board, are the MAPI I/O and interrupt connectors (the corresponding MAPI connectors on the bottom of the FPGA IPB are J1 through J4). Switch S1 is the mode switch. Switch S2 is the reset/load switch, important for downloading from Flash memory to the FPGA device. Jumper header J5 configures the chip select used for programming the FPGA device. 1-2 Rev 1 MMCFPGA1200UM/D

7 nc. INTRODUCTION Breadboard area P1 P4 P5 S1 S2 DS4 DS3 Spare pad Spare pad Spare pad Spare pads P2 U8 Figure 1-1. FPGA IPB P3 Connection points Green LED DS4 lights to confirm successful configuration. Amber LED DS3 lights to indicate that configuration is incomplete or in error. Green LED DS2 lights to confirm that the board s voltage regulator (location U10) is producing 3.3 volts. And green LED DS1 lights to confirm that the board is receiving 5-volt power from the CMB. Just to the left of connector P1 is a row of special connection through-holes: F3, M3, G23, AB22, AD22, AB23, AC26, J25, K26, and F26. For a direct connection to the corresponding FPGA device pin, merely solder a line to the through-hole. The main breadboard area is at the left edge of the board. The through-holes of the top row are 5-volt connection points. The through-holes of the bottom row are 3.3-volt connection points. The through-holes of the right column are ground connection points. Additional breadboard areas, labeled spare pads, are at the lower left corner of the board. These areas are for surface-mount components; three for 25mm-pitch components, and one for 50mm-pitch components. J5 DS1 DS2 The Altera Flex FPGA device is at location U8, inside the MAPI ring. MMCFPGA1200UM/D Rev 1 1-3

8 nc. INTRODUCTION Table 1-1 lists FPGA IPB specifications. Table 1-1. FPGA IPB Design Specifications Characteristic Specifications (1) Operating temperature Storage temperature Relative humidity 0 to 40 C -40 to +85 C 0 to 90% (non-condensing) Power requirements Clock Dimensions 5 volts dc, at 250 milliamperes, provided from the connected CMB 32 MHz 6.9 x 6.4 inches (175 x 163 mm) Weight 5.0 ounces (142 g) (1) These specifications conform to the product design; they have not been tested with actual boards. 1.4 FOOT PLACEMENT During use, your FPGA IPB forms a stack with your CMB: the two boards MAPI rings connect. The FPGA IPB should be the bottom board of the two, so you should protect board components from direct contact with your work surface by attaching the four rubber feet shipped in the CMB box. Carefully turn the FPGA IPB upside down, than attach the feet at each corner, as Figure 1-2 shows. J4 J3 J1 Foot locations J2 Foot locations Figure 1-2. Foot Locations (on Board Bottom) 1-4 Rev 1 MMCFPGA1200UM/D

9 nc. CONFIGURATION AND SETUP CHAPTER 2 CONFIGURATION AND SETUP This chapter explains how to configure your FPGA IPB and how to connect it to a CMB. This chapter also gives suggestions for setting up your Altera development software. 2.1 CONFIGURING AND USING YOUR FPGA IPB Table 2-1 lists the board components that you must set or change to use the FPGA IPB. Paragraphs through give additional information about some of these components. Table 2-1. Setting FPGA IPB Components Component Position Effect Mode Switch, S1 Reset/Load Switch, S2 USER MODE S1 PROGRAM MODE USER MODE S1 PROGRAM MODE RESET/ LOAD S2 Downloads code to IPB Flash memory or directly to the FPGA device. Connects a user FPGA design to the MCU s address, data, and control bus. Press to load code from IPB Flash memory to the FPGA device (if S1 is set to user mode). Press to reset the FPGA IPB (if S1 is set to program mode). MMCFPGA1200UM/D Rev 1 2-1

10 CONFIGURATION AND SETUP nc. Table 2-1. Setting FPGA IPB Components (continued) Component Position Effect Chip Select, Jumper Header, J5 (Only 1 jumper in this header.) Configuration Done LED, DS4 (green) Configuration Error LED, DS3 (amber) 5-volt LED, DS1 (green) CS10 CS9 CS8 CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 CONFIG DONE DS4 CONFIG DONE DS4 CONFIG ERROR DS3 CONFIG ERROR DS3 DS1 J5 Configures the FPGA IPB for programming. This is the only valid programming configuration. Factory setting. (Positions for CS0, CS1, or CS3 may be valid for non-programming operation. Positions for remaining chips selects are not implemented.) Lights to confirm successful code loading. A clock signal will start code running. Stays out to indicate an unsuccessful loading attempt. Lights to indicate bad code, a bad address, or any other problem that prevents loading. Stays out if code loads correctly. +5V Lights to confirm that the board is receiving 5 volts from the CMB, through MAPI connectors. +5V Goes out to indicate that the board is not receiving 5 volts. DS1 2-2 Rev 1 MMCFPGA1200UM/D

11 nc. CONFIGURATION AND SETUP Table 2-1. Setting FPGA IPB Components (continued) Component Position Effect 3.3-volt LED, DS2 (green) +3.3V Lights to confirm that the U10 voltage regulator is producing 3.3 volts. DS2 +3.3V Goes out to indicate the the U10 voltage regulator is not producing 3.3 volts. DS2 F3 Connection Point M3 Connection Point G23 Connection Point AB22 Connection Point AD22 Connection Point F3 M3 G23 AB22 AD22 Connects a signal line directly to the F3 pin of the U8 FPGA device. (Poke the wire through the hole and solder in place. Also requires a ground connection.). Connects a signal line directly to the M3 pin of the U8 FPGA device. (Also requires a ground connection.). Connects a signal line directly to the G23 pin of the U8 FPGA device. (Poke the wire through the hole and solder in place. Also requires a ground connection.). Connects a signal line directly to the AB22 pin of the U8 FPGA device. (Poke the wire through the hole and solder in place. Also requires a ground connection.). Connects a signal line directly to the AD22 pin of the U8 FPGA device. (Poke the wire through the hole and solder in place. Also requires a ground connection.). MMCFPGA1200UM/D Rev 1 2-3

12 CONFIGURATION AND SETUP nc. Table 2-1. Setting FPGA IPB Components (continued) Component Position Effect AB23 Connection Point AB23 Connects a signal line directly to the AB23 pin of the U8 FPGA device. (Poke the wire through the hole and solder in place. Also requires a ground connection.). AC26 Connection Point AC26 Connects a signal line directly to the AC26 pin of the U8 FPGA device. (Poke the wire through the hole and solder in place. Also requires a ground connection.). J25 Connection Point K26 Connection Point F26 Connection Point J25 K26 F26 Connects a signal line directly to the J25 pin of the U8 FPGA device. (Poke the wire through the hole and solder in place. Also requires a ground connection.). Connects a signal line directly to the K26 pin of the U8 FPGA device. (Poke the wire through the hole and solder in place. Also requires a ground connection.). Connects a signal line directly to the F26 pin of the U8 FPGA device. (Poke the wire through the hole and solder in place. Also requires a ground connection.). 2-4 Rev 1 MMCFPGA1200UM/D

13 nc. CONFIGURATION AND SETUP Downloading Directly to the FPGA Device Once you have developed your application code, you can download it directly to the FPGA device, or download it via FLASH memory. (Chapter 3 gives an overview for developing the application code.) To download code directly to the FPGA device: 1. Start your FPGA programmer software (per the instructions of paragraph 3.2). 2. Set switch S1 to program mode. 3. Press switch S2, to reset the FPGA device. 4. Click on the Program FPGA button, then follow the corresponding instructions of paragraph When the success message appears, set switch S1 to user mode. Downloading begins. 6. When the amber LED (DS3) goes out, and green LED DS4 remains on, downloading is done Downloading Via FLASH Memory To download code to IPB FLASH memory: 1. Start your FPGA programmer software (per the instructions of paragraph 3.2). 2. Set switch S1 to program mode. 3. Press switch S2, to reset the FPGA IPB. 4. Click on the Program Flash button, then follow the corresponding instructions of paragraph When the success message appears, downloading to FLASH memory is complete. Once code is in IPB FLASH memory, you can download it to the FPGA device. To do so: 6. Set switch S1 to user mode. 7. Press switch S2. Downloading begins. 8. When the amber LED (DS3) goes out, and green LED DS4 remains on, downloading is done. MMCFPGA1200UM/D Rev 1 2-5

14 CONFIGURATION AND SETUP nc Using the Breadboard Area The FPGA IPB s breadboard area lets you add your own components to the board. Merely insert the component s feet through holes in the board; solder the feet in place to hold the component in position. Run appropriate wires from the new component to board power and ground locations. Note that the top row of breadboard-area holes are +5-volt sources, the bottom row of holes are +3.3-volt sources, and the right column of holes are ground connections Using the Spare Pads The FPGA IPB s spare pads let you add your own surface-mount components to the board. The three small pads are for 25mm-pitch components; the large pad is for 50mm-pitch components. Solder the component s feet to the appropriate solder bars to hold the component in position. Run appropriate wires from the small adjacent through-holes to board power, ground, and signal locations Connecting the FPGA and CMB Boards When you have configured FPGA IPB jumper header J5 and installed any optional components, you are ready to connect the FPGA IPB and the CMB. Place the FPGA IPB on your work surface. Note the position of the silk-screen right-triangle marking, at the ends of MAPI connectors P1 and P2. Hold the CMB directly above the FPGA IPB. Orient the CMB so that the MAPI connectors and right-triangle marking are directly above their FPGA IPB counterparts. Press the CMB down onto the FPGA IPB, so that CMB MAPI connectors J1 through J4 (on the bottom of the board) connect to the FPGA IPB s corresponding MAPI connectors, P1 through P4. Make CMB cable connections per instructions of the CMB user s manual. 2-6 Rev 1 MMCFPGA1200UM/D

15 nc. CONFIGURATION AND SETUP 2.2 CONFIGURING YOUR SOFTWARE NOTE The steps below are guidance for starting to use Altera MAX+plusII software, revision Should you have difficulty preparing your MAX+plusII software, or should your software have a different revision, phone Altera customer service for assistance. Follow the steps below to prepare your Altera development software for use with your FPGA IPB. After you complete these steps, you will be ready to develop an application, per the guidance of Chapter 3 (and of the Altera documentation). Step 1. Install the Altera development software, per the instructions of the FPGA IPB product release guide or of the Altera software itself. Step 2. Obtain your Verilog authorization code, by following the instructions of the FPGA IPB product release guide or of the Altera software. (If you FAX registration information, this takes only a few hours; Altera customer service can provide the FAX number.) Step 3. Start the Altera software. From the Windows desktop, click on Start, select Programs, select MAX+plusII, and select MAX+plusII again. Step 4. Open the Options menu and select Authorization Code. This brings up the Authorization Code dialog box. Enter your authorization code in the appropriate field. NOTE Your authorization code is case sensitive. Make sure to use the correct capital or lower-case letters as you enter the code. Step 5. Click on the Validate button. The software verifies your authorization code, then displays your software guard ID number. Click on the OK button to close the dialog box. Step 6. The MAX+plusII main screen appears. If you are new to Altera software, you should go through the Altera tutorial. Step 7. This completes software preparation. You are ready to develop applications, per Chapter 3. MMCFPGA1200UM/D Rev 1 2-7

16 CONFIGURATION AND SETUP nc. 2-8 Rev 1 MMCFPGA1200UM/D

17 nc. DEVELOPING APPLICATIONS CHAPTER 3 DEVELOPING APPLICATIONS This chapter is an overview of application development. The transmittal CD-ROM that contains this manual also contains example application files: a symbol counter, a Verilog counter, and a Verilog port. 3.1 APPLICATION DEVELOPMENT STEPS Step 1. Step 2. Step 3. Step 4. Step 5. Steps 1 through 23, below, are typical for developing a new application project. These steps are not rigid instructions; instead, you should consider them to be suggestions. In case of difficulty using the MAX+plusII software, you should call Altera customer service for assistance. Use Windows Explorer to create and name a new folder for the project Start the MAX+plusII software. Open the File menu and select Project. From the subordinate menu, select Name. This brings up the Project Name dialog box. Use the Project Name dialog box to select the newly created project folder, and to enter a name for the project. (The project name should not contain any spaces; usually it is most convenient to give the project the same name as the folder.) Click on the OK button to close the dialog box. Open the File menu and select New. This brings up the New dialog box. Select text editor file, then click on the OK button. This closes the dialog box and opens the text editor window. Step 6. Step 7. Step 8. Write the Verilog code for your application. (Consult the Altera Verilog manuals for instructions.) When your code is done, leave the text editor window open. Click on the Open Compiler Window toolbar button. The software immediately compiles your code. If the compiler finds errors, correct them in the text editor window, then compile again. When compilation succeeds, you are ready to create a default symbol. MMCFPGA1200UM/D Rev 1 3-1

18 nc. CONTENTS Step 9. Step 10. Step 11. Step 12. Step 13. Step 14. Step 15. Step 16. Step 17. Still leaving the text editor window open, open the File menu and select Create Default Symbol. The software automatically creates a graphic representation of the compiled code, a symbol that you later can use in a schematic design. Open the File menu and select Project. From the subordinate menu, select Name. This brings up the Project Name dialog box. Use the Project Name dialog box to select the same folder you selected in Step 4. Enter a new project name: as this project will be for a.hex file, Motorola suggests that you append the letter h to the name you used in Step 4. Click on the OK button to close the dialog box. Open the File menu and select New. This brings up the New dialog box. Select graphic editor file, then click on the OK button. This closes the dialog box and opens the graphic editor window. Open the Symbol menu and select Enter. This brings up the Enter Symbol dialog box. Select the symbol you created in Step 9. The symbol appears in the graphic editor window. Add all the inputs and outputs to the symbol, then compile again. (The only errors likely at this point are mismatched signal names or a forgotten signal. Correct any errors and recompile.) When compilation succeeds, you are ready to assign a device. Open the Assign menu and select Device. This brings up the Device dialog box. In the Device Family area, select FLEX10KA. In the Devices area, select EPF10K100ABC Click on the Device Options button, to bring up the FLEX 10K Individual Device Options dialog box. In the FLEX 10K Individual Device Options dialog box, notice the selections of the Device Options area. Click to check three and only three items: Release Clears Before Tri-States, Enable Chip-Wide Output Enable (DEV_OE), and Enable INIT_DONE output.(make sure that there are no grey check marks for any other items of the Device Options area.) Click on the OK button to return to the Device dialog box. Click on the OK button of the Device dialog box to return to the main screen. This completes device assignment; you are ready to assign signals to pins. 2 Rev 1 MMCFPGA1200UM/D

19 nc. DEVELOPING APPLICATIONS Step 18. Step 19. Step 20. Step 21. Step 22. Step 23. Note that it is best to give signals (wires) the same names as their corresponding pins. Open the Assign menu and select Pin/Location/Chip. This brings up the Pin/Location/Chip dialog box. Click on the Search button, to bring up a subordinate dialog box that lists the pins. (Click on the LIST button to see the list. The listed pin names are the inputs and outputs you created as part of Step 14.) Select (highlight) a pin, then click on the OK button. This returns you to the Pin/Location/Chip dialog box; the selected pin name will be in the Node Name field. Go to the Chip Resource area of the dialog box. In the Pin field, enter the name of the FPGA pin. (This is the value in the FPGA Pin column of mapping tables 4-5 through 4-10.) NOTE An alternative to using the Search button is to select Pin, activating the Pin Type field. Select the appropriate type from the small pull-down menu, then enter the pin name in the appropriate field, and enter the signal name in the Node Name field. This completes assignment for the first pin. Repeat Step 18 for all other signals. When you are done, close the Pin/Location/Chip dialog box. NOTE For each finished design, the Altera software creates a.acf file: a text file you can edit. For your first design, you must do Step 18 for each signal. But for subsequent designs, you can copy and edit a.acf file. Compile the file again. When compilation succeeds, you are ready to create a.hex file. Open the MAX+plusII menu and select Programmer. This brings up the Programming dialog box. Disregard (that is, click OK for) any error message that may appear. (You will not do anything in the Programming dialog box, but this open dialog box adds to the File menu the selection you need in the next step.) Open the File menu and select Convert SRAM Object File. This brings up the Convert SRAM Object File dialog box. Select Hex, Single Device. Make sure that the value in the Address field is 0. Click on the OK button for the Altera software to make a.hex version of the application file. This completes application development. You may close the MAX+plusII software. MMCFPGA1200UM/D Rev 1 3-3

20 nc. CONTENTS 3.2 USING THE FPGA PROGRAMMER Motorola FPGA programmer software lets you program a.hex file to the FPGA device, or to Flash memory. Follow typical steps 1 through 11, below. Step 1. Run file FPGAProg.exe. The programmer main screen (Figure 3-1) appears. Step 2. Figure 3-1. FPGA Programmer Main Screen In the Communications area of the main screen, use the Port field to specify the PC serial port; use the Speed field to specify the communications rate. Use the Protocol field to specify the communications protocol: If your computer connects to the OnCE connector of a CMB through an EBDI box, specify ESL. Figure 3-2 illustrates this selection. If your computer connects to a CMB through a serial port, and the CMB system software is intact, specify RS232 (Picobug monitor). If your computer connects to a CMB through a serial port, but the CMB system software has been deleted, specify RS232 (Mbug monitor). (For this selection to be valid, you subsequently must remove the CMB s W9 jumper, then reset the CMB.) Figure 3-2. Protocol Selection 4 Rev 1 MMCFPGA1200UM/D

21 nc. DEVELOPING APPLICATIONS Step 3. Step 4. Step 5. Step 6. Go to the CMB field, near the lower center of the main screen. Make sure that the field specifies CMB1200. Make sure that the Download Algorithm box is checked. Go to the Chip Select Base Address Field, near the left center of the main screen. Enter the base address corresponding to your jumper-header J5 chipselect configuration: If you have configured chip select 0, enter base address 0x2d If you have configured chip select 1, enter base address 0x2f If you have configured chip select 2, enter base address 0x2e If you have configured chip select 3, enter base address 0x2c Go to the Download File field, at the upper left of the main screen. If you know the full pathname of the.hex file, enter the pathname in this field. If you do not know the full pathname of the.hex file, click on the Browse button. This brings up a standard file-select dialog box: select the.hex file and click on the OK button. This returns you to the main screen, entering the pathname in the Download File field. You are ready for either main programming action: programming the FPGA or programming Flash. To program the FPGA, click on the Program FPGA button. The software first downloads the algorithm file (FPGA1200.rec) to the target, displaying a progress message. Then the software downloads the.hex file, displaying another progress message. A Download successful message appears at the end of downloading: you are ready to test the code in your FPGA IPB. If the software cannot find the algorithm file, an appropriate error message appears. Click on the message s OK button to bring up a fileselect dialog box, then use this dialog box to specify the location of file FPGA1200.rec. If necessary, recopy the file from the CD-ROM. Click again on the Program FPGA button. The error message Unable to Validate Flash configuration indicates some problem with the programming. The most likely cause of such problems is that mode switch S1 was in the user mode position, or that the chip select base address does not correspond to the chip select that header J5 configures. Correct the problem, then click again on the Program FPGA button. MMCFPGA1200UM/D Rev 1 3-5

22 nc. CONTENTS Step 7. Step 8. Step 9. To program Flash memory, click on the Program Flash button. The software downloads the.hex file, displaying a progress message. A Download successful message appears at the end of programming: you are ready to use the code in Flash memory. The error message Unable to Validate Flash configuration indicates some problem with the programming. The most likely cause of such problems is that mode switch S1 was in the user mode position, or that the chip select base address does not correspond to the chip select that header J5 configures. Correct the problem, then click again on the Program Flash button. The error message Flash is not blank indicates that you must erase the Flash. To do so, click on the message s OK button. Erasure takes 20 to 30 seconds, then Flash programming resumes. To verify that the contents of Flash memory match the selected download file, click on the Verify Flash button. A progress message appears as verification begins. A Verify successful message appears at the end of verification. If verification fails, an error message specifies the location that did not have the expected contents. To recover from a verification failure, try programming Flash again, to replace Flash contents with the selected download file. To view the contents of Flash memory, click on the Display Flash button. This brings up the FPGA Board Flash Contents display (Figure 3-3). Figure 3-3. FPGA Board Flash Contents Display The Address field shows the first address of the value display. One way to change the display is to enter a different address in this field. 6 Rev 1 MMCFPGA1200UM/D

23 nc. DEVELOPING APPLICATIONS Another way to change the value display is to use the vertical or horizontal scroll bars. When you are done viewing the display, click on the Close button to return to the main screen. Step 10. Step 11. To see version information about the FPGA programmer, click on the Version button. The information appears in a temporary window. At the end of your programming session, click on the Exit button. NOTE Two requirements, if ignored, can block your development activities: The FPGA IPB requires an 8- to 64-megahertz clock signal from the CMB1200, on the CLKOUT pin (pin A14). You must turn this clock signal on after each CMB1200 reset. (To do so, you must configure the reset source/chip configuration register appropriately, per instructions of the MMC2001 reference manual.) Any time that the data bus accesses a user circuit, that circuit must bring low the FPGAOUT* pin (pin G5). MMCFPGA1200UM/D Rev 1 3-7

24 nc. CONTENTS 8 Rev 1 MMCFPGA1200UM/D

25 nc. MAPI CONNECTOR INFORMATION CHAPTER 4 MAPI CONNECTOR INFORMATION This chapter consists of pin assignments and signal descriptions for the FPGA IPB MAPI connectors. This chapter includes cross-reference tables, for correlating signals of the FPGA and CMB MAPI rings. 4.1 MAPI CONNECTORS (P1/J1, P2/J2, P3/J3, P4/J4) Connectors P1 through P4, all 2-by-50-pin connectors, are the FPGAIPB MAPI connectors. (Connectors J1 through J4, on the bottom of the board, have the same pin assignments.) The diagram below shows the orientation of these connectors. Figures 4-1 through 4-4, and tables 4-1 through 4-4, give the pin assignments and signal descriptions for these connectors P1 1 1 P4 P P MMCFPGA1200UM/D Rev 1 4-1

26 MAPI CONNECTOR INFORMATION nc. P1/J1 VPP VDD CS8* CS4* NC NC CS9* CS5* GFLCS* SRSIZ2* CS10* CS6* GND SRSIZ1* GND CS7* GALB1* SRSIZ0* ATVDD(VCC) GND GALB0* GND RS RS27 GND NC RS RS25 INT NC RS RS23 INT INT7 RS RS21 GND INT5 RS RS19 INT INT3 RS RS17 INT INT1 RS RS15 GND NC GND RS13 GND NC RS GND NC NC RS RS11 NC NC RS RS9 NC NC RS RS7 NC NC RS RS5 NC GND RS RS3 NC NC RS RS1 GND NC GND NC GND COL7 NC NC COL6 8 7 COL5 NC NC COL4 6 5 COL3 GND NC COL2 4 3 COL1 GND2 2 1 COL0 Figure 4-1. MAPI Connector P1/J1 Pin Assignments 4-2 Rev 1 MMCFPGA1200UM/D

27 nc. MAPI CONNECTOR INFORMATION Table 4-1. MAPI Connector P1/J1 Signal Descriptions Pin Mnemonic Signal 100 VPP1 No connection 99 VDD No connection 98 93, 91 CS8*, CS4*, CS9*, CS5*, CS10*, CS6*, CS7* 92, 89, 74, 71, 58, 52, 46, 41, 40, 34, 28, 15 GND RESERVED CHIP SELECTS Reserved chip-select lines 8, 4, 9, 5, 10, 6, and 7 Do Not Use. GROUND 90 ATVDD (VCC) OPERATING VOLTAGE Transmission line for +5-volt CMB input power , 73, 72, , 51 49, 39, 37, 27, 25 16, 14, 13, 11 RS27 RS0 NC RESERVED Do Not Use. No connection 48 GFLCS* GAL FLASH CHIP SELECT If low, this signal indicates address-decoded chip selection of FLASH. 47 SRSIZ2* SRAM SIZE If low, this signal indicates that the CMB has a 64K-by-16 SRAM. 45 SRSIZ1* SRAM SIZE If low, this signal indicates that the CMB has a 128K-by-16 SRAM. 44 GALB1* GAL BANK CHIP SELECT If low, this signal indicates addressdecoded chip selection of SRAM bank SRSIZ0* SRAM SIZE If low, this signal indicates that the CMB has a 256K-by-16 SRAM. 42 GALB0* GAL BANK CHIP SELECT If low, this signal indicates addressdecoded chip selection of SRAM bank 0. 38, 36, 35, INT 6, INT 4, INT 7, INT 5, INT 2, INT 3, INT 0, INT 1 26, 12 GND1 GROUND 9 3, 1 COL 7, COL 6 COL 1, COL 0 2 GND2 GROUND EXTRNAL INTERRUPTS (lines 6, 4, 7, 5, 2, 3, 0, 1) Bidirectional interrupt lines that form the external interface to the general-purpose I/O module. COLUMN STROBES (lines 7 0) Keypad column strobe lines, open-drain selectable via software. (Default state upon reset is general-purpose input.) MMCFPGA1200UM/D Rev 1 4-3

28 MAPI CONNECTOR INFORMATION nc. P2/J2 (GND) GND3 (GND) PWM5 RS RS47 (GND) PWM4 RS RS45 (GND) PWM3 GND RS43 (GND) PWM2 RS GND (GND) PWM1 RS RS41 (GND) PWM0 RS RS39 (GND) GND3 RS RS37 GND GND GND RS35 VDD VPP3 RS GND NC ATVDD (VCC) RS RS31 NC NC RS RS29 NC NC NC SPI_GP NC NC SPI_CLK SPI_EN NC NC SPI_MOSI SPI_MISO RXD TXD1 NC NC CTS0* RTS0* VDD VPP2 RXD TXD0 GND GND GND GND NC GND2 RS NC NC NC RS RS57 NC NC RS RS55 ROW ROW7 RS RS53 ROW4 8 7 ROW5 RS RS51 ROW2 6 5 ROW3 RS RS49 ROW0 4 3 ROW1 NC 2 1 GND2 Figure 4-2. MAPI Connector P2/J2 Pin Assignments 4-4 Rev 1 MMCFPGA1200UM/D

29 nc. MAPI CONNECTOR INFORMATION Table 4-2. MAPI Connector P2/J2 Signal Descriptions Pin Mnemonic Signal 100, 98, 96, 94, 92, 90, 88, 86, 84, 83, 64, 63, 46, 43, 36, 33, 18, 17 GND GROUND 99, 85 GND3 GROUND 97, 95, 93, 91, 89, 87 PWM 5 PWM 0 PULSE WIDTH MODULATOR (lines 5 0) External interface lines for the pulse width modulator block. (Default state upon reset is general-purpose input.) 82 VDD No connection 81 VPP3 No connection 80, 78 71, 61, 28, 22, 21, 16, 14 11, 2 NC No connection 79 ATVDD (VCC) OPERATING VOLTAGE Transmission line for +5-volt CMB input power. 70, 66 RXD1, RXD0 RECEIVE DATA (lines 1, 0) Input data receive lines for UART channels 1 and 0. 69, 65 TXD1, TXD0 TRANSMIT DATA (lines 1, 0) Output data transmission lines for UART channels 1 and CTS0* CLEAR TO SEND 0 Active-low output that can be programmed as the UART-channel-0 clear-to-send signal. 67 RTS0* REQUEST TO SEND 0 Active-low input that can be programmed as the UART-channel-0 request-to-send signal. 62, 60 47, 45, 44, 42 37, 35, 34, RS58 RS28 RESERVED Do Not Use. 27 SPI_GP SPI GENERAL PURPOSE OUTPUT Serial peripheral interface module output line: a control line for external logic or devices. 26 SPI_CLK SPI SERIAL CLOCK Serial shift clock line for the serial peripheral interface module. 25 SPI_EN SPI ENABLE In master mode, the peripheral chip-select line. In slave mode, the slave enable line. MMCFPGA1200UM/D Rev 1 4-5

30 MAPI CONNECTOR INFORMATION nc. Table 4-2. MAPI Connector P2/J2 Signal Descriptions (continued) Pin Mnemonic Signal 24 SPI_MOSI SPI DATA MASTER OUT/SLAVE IN In master mode, serial data output line from the serial peripheral interface module of the MCU. In slave mode, serial data input line to the serial peripheral interface. 23 SPI_MISO SPI DATA MASTER IN/SLAVE OUT In master mode, serial data input line to the serial peripheral interface of the MCU. In slave mode, serial data output line from the serial peripheral interface. 15, 1 GND2 GROUND 10 3 ROW6, ROW7, ROW4, ROW5, ROW2, ROW3, ROW0, ROW4 ROW SENSES (lines 6, 7, 4, 5, 2, 3, 0, 1) Keypad row sense lines. (On-chip 47KΩ pullup resistors are connected to these lines; the default state upon reset is generalpurpose input.) 4-6 Rev 1 MMCFPGA1200UM/D

31 nc. MAPI CONNECTOR INFORMATION P3/J3 VDD VDD VPP GND NC GND CLKCTL GND NC NC FREEZE* EXTAL NC OSCIN (EXOSC) TSC (GND) GND NC GND GPIO/SI GPIO/SO NC MOD* SIZ1* TRST* NC LVRSTIN* SIZ0* TCK NC MID6 (GND) DE* TMS NC PGND TDI GND NC NC TDO RSTOUT* NC MID7 (GND) VBATT RSTIN* NC NC IDVDD SHS NC NC ATVDD (VCC) RS71 NC GND RS RS69 NC GND4 RS RS67 NC GPSOUT GND RS65 NC NC RS GND NC NC RS RS63 NC NC RS RS61 NC NC RS RS59 NC NC TEST NC NC 10 9 GND4 NC MID4 (GND) NC 8 7 GND3 (VSS_OSC) NC NC NC 6 5 VDD_OSC NC NC VDD_IO 4 3 VDD_CORE VDD_LOGIC 2 1 GND3 (VSS_CORE) Figure 4-3. MAPI Connector P3/J3 Pin Assignments MMCFPGA1200UM/D Rev 1 4-7

32 MAPI CONNECTOR INFORMATION nc. Table 4-3. MAPI Connector P3/J3 Signal Descriptions Pin Mnemonic Signal 100, 99 VDD No connection 98 VPP4 No connection 97, 95, 91, 81, 68, 65, 55, 49, 43, 25 GND GROUND 96 CLKCTL No connection 94 FREEZE* No connection 93 EXTAL CRYSTAL INPUT Input signal from a user-supplied crystal. 92 TSC (GND) GROUND 90, 89 GPIO/SI, GPIO/SO 88, 86 SIZ1*, SIZ0* No connection GENERAL PURPOSE I/O SERIAL IN, OUT General purpose input and output lines. 87 TRST* TEST RESET Active-low input signal to the Schmitt trigger, asynchronously initializing the test controller. The TRST* pin has an internal 47k pullup resistor. 85 TCK TEST CLOCK Input signal that synchronizes the JTAG test logic. The TCK pin has an internal 47k pullup resistor. 84 DE* DEBUG EVENT Open-drain, active-low debug signal. If an input signal from an external command controller, causes the EVB to enter debug mode. If an output signal, acknowledges that the RCE(?) is in debug mode. 83 TMS TEST MODE SELECT Input signal that sequences the test controller s state machine, sampled on the rising edge of the TCK signal. The TMS pin has an internal 47k pullup resistor. 82 TDI TEST DATA INPUT Serial input signal for test instructions and data, sampled on the rising edge of the TCK signal. The TDI pin has an internal 47k pullup resistor. 80 TDO TEST DATA OUTPUT Serial output signal tfor test instructions and data. Three-stateable and actively driven in the Shift-IR and Shift-DR controller states, this signal changes on the falling edge of the TCK signal. 79 RSTOUT* RESET OUT Active-low output signal that resets external components. Activation of any internal reset sources asserts this line. 78 VBATT STANDBY BATTERY POWER 4-8 Rev 1 MMCFPGA1200UM/D

33 nc. MAPI CONNECTOR INFORMATION Table 4-3. MAPI Connector P3/J3 Signal Descriptions (continued) Pin Mnemonic Signal 77 RSTIN* RESET IN Active-low input signal that resets the FPGA IPB. 76 IDVDD IDENTIFICATION POWER Power line to FPGA identification bits. 75 SHS No connection 74 ATVDD (VCC) 73 69, RS71 RS59 OPERATING VOLTAGE Transmission line for +5-volt CMB input power; passed to the FPGA IPB RESERVED Do Not Use. 58 TEST FACTORY TEST MODE Input signal that selects factory test mode. The TEST pin has an internal 100k pulldown resistor. 57, 56, 54 50, 48 46, 44, 42, 40, 38, 36, 34 32, 30 26, 24, 20 10, 8, 6 NC No connection 55 MID4 (GND) IDENTIFICATION BITS Signal that identifies the CMB to a smart platform board. 45 OSCIN (EXOSC) OSCILLATOR INPPUT Input oscillator signal, also known as External Oscillator. 41 MOD* INITIAL VECTOR SELECT If high, selects the initial reset vector from the lowest address of internal ROM. If low, selects the initial reset vector from the lowest address of chip select 0, then jumps to that address. 39 LVRSTIN* LOW VOLTAGE RESET IN Active-low input signal that starts a system reset: a reset of the PowerStrike chip and most peripherals. This signal also selects the backup power supply souce for the RAM array and for the OSC/time-of-day timer. This signal does not affect the debug module (which the system provides via the TRST* line). 37 MID6 (GND) IDENTIFICATION BITS Signal that identifies the CMB to a smart platform board. 35 PGND GROUND 31 MID7 (GND) IDENTIFICATION BITS Signal that identifies the CMB to a smart platform board. MMCFPGA1200UM/D Rev 1 4-9

34 MAPI CONNECTOR INFORMATION nc. Table 4-3. MAPI Connector P3/J3 Signal Descriptions (continued) Pin Mnemonic Signal 23, 9 GND4 GROUND 7 GND3 (VSS_OSC) OSCILLATOR GROUND Ground line for the MCU oscillator. 5 VDD_OSC OSCILLATOR VOLTAGE Transmission line for +3.3-volt MCU oscillator operating power. 4 VDD_IO I/O VOLTAGE Transmission line for +3.3-volt MCU I/O operating power. 3 VDD_CORE CORE VOLTAGE Transmission line for +3.3-volt (or alternate volt) MCU core operating power. 2 VDD_LOGIC LOGIC VOLTAGE Transmission line for +3.3-volt CMB logic operating power. 1 GND3 (VSS_CORE) CORE GROUND Ground line for the MCU core Rev 1 MMCFPGA1200UM/D

35 nc. MAPI CONNECTOR INFORMATION P4/J4 RS VDD RS GND A A9 GND CLKOUT A A7 RS GND A A5 RS CS3 A A3 RS72 (GND) CS2* A A1 OE* CS1* GND GND EB3* CS0* D D31 EB2* GND D D29 EB1* R/W* D D27 EB0* TREQ* D D25 TEA* TA* D D23 GND GND GND GND A A31 D D21 A A29 D D19 A A27 D D17 A A25 D D15 A A23 D D13 A A21 GND GND A A19 D D11 A A17 D D9 GND GND D D7 A A15 D4 8 7 D5 A A13 D2 6 5 D3 A A11 D0 4 3 D1 VDD 2 1 VDD Figure 4-4. MAPI Connector P4/J4 Pin Assignments MMCFPGA1200UM/D Rev

36 MAPI CONNECTOR INFORMATION nc. Table 4-4. MAPI Connector P4/J4 Signal Descriptions Pin Mnemonic Signal 100, 98, 94, 92 RS76 RS73 RESERVED Do Not Use. 99, 2, 1 VDD No connection 97, 96, 93, 83, 76, 75, 58, 57, 40, 39, 28, 27, 16, 15 GND GROUND 95 CLKOUT CLOCK OUTPUT An external clock source: LO_REFCLK or HI_REFCLK. 91, 89, 87, 85 CS3 CS0* CHIP SELECTS (lines 3 0) Output lines that provide chip selects to external devices. Note that CS3 is active high, but the others are active low. 90 RS72 (GND) GROUND 88 OE* OUTPUT ENABLE Active-low signal that indicates that a bus access is a read access; enables slave devices to drive the data bus. 86, 84, 82, 80 EB3* EB0* ENABLE BYTES 3, 2, 1, 0 Active-low outputs active during an operation coresponding to specific data bits: D15 D8 for enable byte 0, D7 D0 for enable byte 1, D16 D23 for enable byte 2, D24 D31 for enable byte 3. You can configure these bytes to assert for write cycles or for both read and write cycles. 81 R/W* READ/WRITE ENABLE Active-low signal that indicates whether the current bus access is a read access or write access. 79 TREQ* TRANSMIT REQUEST (No connection) 78 TEA* TRANSMIT ERROR ACKNOWLEDGE (No connection) 77 TA* TRANSMIT ACKNOWLEDGE (No connection) 74 59, , 26 17, 14 3 A31 A0 (not in exact sequence) D31 D0 (not in exact sequence) ADDRESS BUS (lines 31 0) Output lines for addresing external devices. These lines change state only during external-memory accesses. DATA BUS (lines 31 0) Bi-directional data lines for accessing external memory. A hardware reset or no external-bus activity hods these lines in their previous logic state Rev 1 MMCFPGA1200UM/D

37 nc. MAPI CONNECTOR INFORMATION 4.2 REFERENCE TABLES Although signal pin assignments for the MAPI connectors of your FPGA IPB are similar to assignments for CMB MAPI connectors, there are many differences. As you develop your application, you will need to find corresponding signals of the two boards. The remaining tables of this chapter help you do this: Tables 4-5 through 4-8 are references for FPGA IPB connector P1 through P4. These tables show how the pins relate to signals and pins of the board s resident MCU, as well as to signals and pins of the CMB1200 s resident MCU. Table 4-9 lists pins and signals of the FPGA device, showing how the signals relate to MAPI connectors and the CMB1200 s resident MCU. Table 4-10 lists signals and pins of the CMB1200 s resident MCU, showing how the signals relate to MAPI connectors and the resident FPGA device. Table 4-11 lists FPGA IPB MAPI pins available for use in your own designs. For some of these pins, note that your use is restricted. Note these conventions for Tables 4-5 through 4-11: NC means no connection. PL means plane: this identifies connections to a ground-plane layer or power-plane layer. Provisional means that you may use the pin your design now, but you might need to change the pin use in the future. PT means pass through: only connected between the J and P pins of the MAPI connector. Reserved means that you may not use the pin in your design, or that you must use the pin for a particular purpose. Unrestricted means that you may use the pin for any purpose in your design. NOTES The FPGA IPB requires an 8- to 64-megahertz clock signal from the CMB120, on the CLKOUT pin (pin A14). This means that you must configure the reset/source/chip configuration register appropriately after each CMB reset. (The MMC2001 reference manual explains how to configure this register.) Any time that the data bus accesses a user circuit, that circuit must bring low the FPGAOUT* pin (pin G5). MMCFPGA1200UM/D Rev

38 MAPI CONNECTOR INFORMATION nc. Table 4-5. Pin Mapping: MAPI Connector J1, FPGA Device, CMB1200 J1 Pin MMCFPGA1200 Signal FPGA Pin CMB1200 Signal MMC2001 Pin J1-1 PT NC COL0 112 J1-2 GND2 NC GND J1-3 PT NC COL1 109 J1-4 PT NC COL2 108 J1-5 PT NC COL3 107 J1-6 PT NC COL4 106 J1-7 PT NC COL5 105 J1-8 PT NC COL6 104 J1-9 PT NC COL7 103 J1-10 GND2 NC GND J1-11 PT NC NC J1-12 GND1 NC GND J1-13 PT NC NC J1-14 PT NC NC J1-15 PT NC GND J1-16 PT NC NC J1-17 PT NC NC J1-18 PT NC NC J1-19 PT NC NC J1-20 PT NC NC J1-21 PT NC NC J1-22 PT NC NC J1-23 PT NC NC J1-24 PT NC NC J1-25 PT NC NC J1-26 GND1 NC GND J1-27 IO0 AF13 NC J1-28 GND PL GND J1-29 IO1 AB2 INT1 (CMB) 101 J1-30 IO11 Y26 INT0 (CMB) Rev 1 MMCFPGA1200UM/D

39 nc. MAPI CONNECTOR INFORMATION Table 4-5. Pin Mapping: MAPI Connector J1, FPGA Device, CMB1200 (continued) J1 Pin MMCFPGA1200 Signal FPGA Pin CMB1200 Signal MMC2001 Pin J1-31 IO2 AC1 INT3 (CMB) 97 J1-32 IO12 W23 INT2 (CMB) 100 J1-33 IO3 AB5 INT5 (CMB) 95 J1-34 MID3 G26 GND J1-35 IO4 AA22 INT7 (CMB) 93 J1-36 IO13 W26 INT4 (CMB) 96 J1-37 IO5 AA25 NC J1-38 IO14 V25 INT6 (CMB) 94 J1-39 IO6 AA26 NC J1-40 MID2 J23 GND J1-41 GND PL GND J1-42 IO15 U3 GALB0* NC J1-43 IO7 Y23 SRSIZ0* NC J1-44 IO16 U4 GALB1* NC J1-45 IO8 AA5 SRSIZ1* NC J1-46 GND PL GND J1-47 IO9 Y24 SRSIZ2* NC J1-48 IO17 V26 GFLCS* NC J1-49 IO10 Y25 NC J1-50 IO18 U24 NC J1-51 INPUT1 B14 NC J1-52 MID1 H3 GND J1-53 INPUT2 A13 NC J1-54 IO19 T22 NC J1-55 INPUT3 AE13 NC J1-56 IO20 T2 NC J1-57 INPUT4 AF14 NC J1-58 MID0 H25 GND J1-59 VDD3V PL NC J1-60 VDD3V PL NC MMCFPGA1200UM/D Rev

40 MAPI CONNECTOR INFORMATION nc. Table 4-5. Pin Mapping: MAPI Connector J1, FPGA Device, CMB1200 (continued) J1 Pin MMCFPGA1200 Signal FPGA Pin CMB1200 Signal MMC2001 Pin J1-61 INT1 (MAPI) T4 NC J1-62 INT0 (MAPI) T5 NC J1-63 INT3 (MAPI) P22 NC J1-64 INT2 (MAPI) R3 NC J1-65 INT5 (MAPI) R4 NC J1-66 INT4 (MAPI) P25 NC J1-67 INT7 (MAPI) P1 NC J1-68 INT6 (MAPI) R5 NC J1-69 RS11 AD1 NC J1-70 RS10 AB24 NC J1-71 GND PL GND J1-72 RS12 AC4 NC J1-73 DVSP0* T23 NC J1-74 GND PL GND J1-75 DVSP1* U25 NC J1-76 DVSP2* E3 NC J1-77 TARGET* R22 NC J1-78 RS16 AB3 NC J1-79 RS19 AB26 NC J1-80 RS18 AB25 NC J1-81 RS21 Y5 NC J1-82 RS20 AA2 NC J1-83 RS23 AA4 NC J1-84 RS22 AA3 NC J1-85 RS25 Y4 NC J1-86 RS24 AA23 NC J1-87 RS27 W25 NC J1-88 RS26 Y22 NC J1-89 GND PL GND J1-90 VDD5V NC VDD5V NC 4-16 Rev 1 MMCFPGA1200UM/D

41 nc. MAPI CONNECTOR INFORMATION Table 4-5. Pin Mapping: MAPI Connector J1, FPGA Device, CMB1200 (continued) J1 Pin MMCFPGA1200 Signal FPGA Pin CMB1200 Signal MMC2001 Pin J1-91 CS7 M5 NC J1-92 GND PL GND J1-93 CS6 N22 NC J1-94 CS10 K2 NC J1-95 CS5 P26 NC J1-96 CS9 M24 NC J1-97 CS4 M2 NC J1-98 CS8 M25 NC J1-99 VDD3V PL NC J1-100 PT NC NC MMCFPGA1200UM/D Rev

42 MAPI CONNECTOR INFORMATION nc. Table 4-6. Pin Mapping: MAPI Connector J2, FPGA Device, CMB1200 J2 Pin MMCFPGA1200 Signal FPGA Pin CMB1200 Signal MMC2001 Pin J2-1 GND2 NC GND J2-2 PT NC NC J2-3 PT NC ROW1 119 J2-4 PT NC ROW0 120 J2-5 PT NC ROW3 117 J2-6 PT NC ROW2 118 J2-7 PT NC ROW5 115 J2-8 PT NC ROW4 116 J2-9 PT NC ROW7 113 J2-10 PT NC ROW6 114 J2-11 PT NC NC J2-12 PT NC NC J2-13 PT NC NC J2-14 PT NC NC J2-15 GND2 NC GND J2-16 PT NC NC J2-17 GND PL GND J2-18 GND PL GND J2-19 VPP2 NC NC J2-20 VDD3V PL NC J2-21 IO21 R23 NC J2-22 IO33 J22 NC J2-23 IO22 R25 SPI_MISO 121 J2-24 IO34 H26 SPI_MOSI 124 J2-25 IO23 P23 SPI_EN 125 J2-26 IO35 G25 SPI_CLK 126 J2-27 IO24 N25 SPI_GP 128 J2-28 IO36 G22 NC J2-29 VDD5V NC NC J2-30 RS28 W2 NC 4-18 Rev 1 MMCFPGA1200UM/D