SPI Serial EEPROMs 8K (1024 x 8) 16K (2048 x 8) AT25080B AT25160B. Preliminary

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Features Serial Peripheral Interface (SPI) Compatible Supports SPI Modes (,) and 3 (,) Datasheet Describes Mode Operation Low-voltage and Standard-voltage Operation.8 (V CC =.8V to.

1 Features Serial Peripheral Interface (SPI) Compatible Supports SPI Modes (,) and 3 (,) Datasheet Describes Mode Operation Low-voltage and Standard-voltage Operation.8 (V CC =.8V to.v) MHz Clock Rate (V) 3-byte Page Mode Block Write Protection Protect /4, /, or Entire Array Write Protect (WP) Pin and Write Disable Itructio for Both Hardware and Software Data Protection Self-timed Write Cycle ( ms max) High Reliability Endurance: One Million Write Cycles Data Retention: Years 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP x3), 8-lead TSSOP and 8-ball dbga Packages Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers Description The AT8B/6B provides 89/6384 bits of serial electrically-erasable programmable read-only memory (EEPROM) organized as 4/48 words of 8 bits each. The device is optimized for use in many industrial and commercial applicatio where low-power and low-voltage operation are essential. The AT8B/6B is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP x3) and 8-lead TSSOP packages. The AT8B/6B is enabled through the Chip Select pin (CS) and accessed via a three-wire interface coisting of Serial Data Input (), Serial Data Output (SO), and Serial Clock (). All programming cycles are completely self-timed, and no separate erase cycle is required before write. Table -. Pin Configuration Pin Name CS SO GND VCC WP HOLD Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Write Protect Suspends Serial Input CS SO WP GND CS SO WP GND 8-lead PDIP lead TSSOP VCC HOLD VCC HOLD SPI Serial EEPROMs 8K (4 x 8) 6K (48 x 8) AT8B AT6B Preliminary

2 CS SO WP GND 8-lead SOIC VCC HOLD 8-lead Ultra Thin Mini-MAP (MLP x3) VCC HOLD 8 6 Bottom View 3 4 CS SO WP GND VCC HOLD 8-ball dbga Block write protection is enabled by programming the status register with one of four blocks of write protection. Separate program enable and program disable itructio are provided for additional data protection. Hardware data protection is provided via the WP pin to protect agait inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. 8 6 Bottom View 3 4 CS SO WP Absolute Maximum Ratings* Operating Temperature... C to + C Storage Temperature... 6 C to + C Voltage on Any Pin with Respect to Ground....V to +.V Maximum Operating Voltage... 6.V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. DC Output Current.... ma AT8B/6B [Preliminary]

3 AT8B/6B [Preliminary] Figure -. Block Diagram Table -. Pin Capacitance () Applicable over recommended operating range from T A = C, f =. MHz, V CC = +.V (unless otherwise noted) Symbol Test Conditio Max Units Conditio C OUT Output Capacitance (SO) 8 pf V OUT = V C IN Input Capacitance (CS,,, WP, HOLD) 6 pf V IN = V Note:. This parameter is characterized and is not % tested. Table -3. DC Characteristics Applicable over recommended operating range from: T AI = 4 C to +8 C, V CC = +.8V to +.V (unless otherwise noted) Symbol Parameter Test Condition Min Typ Max Units V CC Supply Voltage.8. V V CC Supply Voltage.. V V CC3 Supply Voltage 4.. V I CC Supply Current V CC =.V at MHz, SO = Open, Read.. ma I CC Supply Current V CC =.V at MHz, SO = Open, Read, Write 4.. ma 3

4 Applicable over recommended operating range from: T AI = 4 C to +8 C, V CC = +.8V to +.V (unless otherwise noted) Symbol Parameter Test Condition Min Typ Max Units V I CC3 Supply Current CC =.V at MHz, SO = Open, ma Read, Write I SB Standby Current V CC =.8V, CS = V CC <. 6. () µa I SB Standby Current V CC =.V, CS = V CC.3. () µa I SB3 Standby Current V CC =.V, CS = V CC.. () µa I IL Input Leakage V IN = V to V CC µa I OL Output Leakage V IN = V to V CC, T AC = C to C µa V IL () V IH () Input Low-voltage.6 V CC x.3 V Input High-voltage V CC x. V CC +. V V OL Output Low-voltage I OL = 3. ma.4 V 4.V V CC.V V OH Output High-voltage I OH =.6 ma V CC -.8 V V OL Output Low-voltage I OL =. ma. V.8V V CC 3.6V V OH Output High-voltage I OH = µa V CC -. V Notes:. V IL min and V IH max are reference only and are not tested.. Worst case measured at 8 C 4 AT8B/6B [Preliminary]

5 AT8B/6B [Preliminary] Table -4. AC Characteristics Applicable over recommended operating range from T AI = 4 C to +8 C, V CC = As Specified, CL = TTL Gate and 3 pf (unless otherwise noted) Symbol Parameter Voltage Min Max Units f Clock Frequency MHz t RI Input Rise Time µs t FI Input Fall Time µs t WH High Time t WL Low Time t CS CS High Time t CSS CS Setup Time t CSH CS Hold Time t SU Data In Setup Time t H Data In Hold Time t HD HOLD Setup Time t CD HOLD Hold Time t V Output Valid t HO Output Hold Time 4....

6 Table -4. AC Characteristics (Continued) Applicable over recommended operating range from T AI = 4 C to +8 C, V CC = As Specified, CL = TTL Gate and 3 pf (unless otherwise noted) Symbol Parameter Voltage Min Max Units t LZ HOLD to Output Low Z t HZ HOLD to Output High Z t DIS Output Disable Time t WC Write Cycle Time ms Endurance () 3.3V, C, Page Mode M Write Cycles Note:. This parameter is characterized and is not % tested.. Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin () is always an input, the AT8B/6B always operates as a slave. TRANSMITTER/RECEIVER: The AT8B/6B has separate pi designated for data tramission (SO) and reception (). MSB: The Most Significant Bit (MSB) is the first bit tramitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contai the op-code that defines the operatio to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT8B/6B, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT8B/6B is selected when the CS pin is low. When the device is not selected, data will not be accepted via the pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT8B/6B. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the pin is low. To resume serial communication, the HOLD pin is brought high while the pin is low ( may still toggle during HOLD). Inputs to the pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operatio when held high. When the WP pin is brought low and WPEN bit is, all write operatio to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write 6 AT8B/6B [Preliminary]

7 AT8B/6B [Preliminary] operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is. This will allow the user to itall the AT8B/6B in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functio are enabled when the WPEN bit is set to. Figure -. SPI Serial Interface AT8B/6B. Functional Description The AT8B/6B is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 68 and 68HC series of microcontrollers. The AT8B/6B utilizes an 8-bit itruction register. The list of itructio and their operation codes are contained in Table -. All itructio, addresses, and data are traferred with the MSB first and start with a high-to-low CS traition. Table -. Itruction Set for the AT8B/6B Itruction Name Itruction Format Operation WREN X Set Write Enable Latch WRDI X Reset Write Enable Latch RDSR X Read Status Register

8 Table -. Itruction Set for the AT8B/6B Itruction Name Itruction Format Operation WRSR X Write Status Register READ X Read Data from Memory Array WRITE X Write Data to Memory Array WRITE ENABLE (WREN): The device will power up in the write disable state when V CC is applied. All programming itructio must therefore be preceded by a Write Enable itruction. WRITE DISABLE (WRDI): To protect the device agait inadvertent writes, the Write Disable itruction disables all programming modes. The WRDI itruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register itruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR itruction. Similarly, the Block Write Protection Bits indicate the extent of protection employed. These bits are set by using the WRSR itruction. Table -. Status Register Format Bit Bit 6 Bit Bit 4 Bit 3 Bit Bit Bit WPEN X X X BP BP WEN RDY Table -3. Bit Bit (RDY) Bit (WEN) Read Status Register Bit Definition Definition Bit = (RDY) indicates the device is READY. Bit = indicates the write cycle is in progress. Bit = indicates the device is not WRITE ENABLED. Bit = indicates the device is write enabled. Bit (BP) See Table -4 on page 9. Bit 3 (BP) See Table -4 on page 9. Bits 4 6 are s when device is not in an internal write cycle. Bit (WPEN) See Table - on page 9. Bits are s during an internal write cycle. WRITE STATUS REGISTER (WRSR): The WRSR itruction allows the user to select one of four levels of protection. The AT8B/6B is divided into four array segments. One-quarter, one-half, or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read only. The block write protection levels and corresponding status register control bits are shown in Table -4. The three bits BP, BP, and WPEN are nonvolatile cells that have the same properties and functio as the regular memory cells (e.g., WREN, t WC, RDSR). 8 AT8B/6B [Preliminary]

9 AT8B/6B [Preliminary] Table -4. Level Block Write Protect Bits Status Register Bits Array Addresses Protected BP BP AT8B AT6B None None (/4) 3 3FF 6 FF (/) 3FF 4 FF 3(All) 3FF FF The WRSR itruction also allows the user to enable or disable the write protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is. When the device is hardware write protected, writes to the status register, including the block protect bits and the WPEN bit, and the block-protected sectio in the memory array are disabled. Writes are only allowed to sectio of the memory that are not block-protected. NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to as long as the WP pin is held low. Table -. WPEN Operation WPEN WP WEN Protected Blocks Unprotected Blocks Status Register X Protected Protected Protected X Protected Writeable Writeable Low Protected Protected Protected Low Protected Writeable Protected X High Protected Protected Protected X High Protected Writeable Writeable READ SEQUENCE (READ): Reading the AT8B/6B via the Serial Output (SO) pin requires the following sequence. After the CS line is pulled low to select a device, the read opcode is tramitted via the line followed by the byte address to be read (A A, see Table - 6). Upon completion, any data on the line will be ignored. The data (D D) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. WRITE SEQUENCE (WRITE): In order to program the AT8B/6B, two separate itructio must be executed. First, the device must be write enabled via the WREN itruction. Then a write (WRITE) itruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. During an internal write cycle, all commands will be ignored except the RDSR itruction. 9

10 A write itruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE op-code is tramitted via the line followed by the byte address (A A) and the data (D D) to be programmed (see Table -6). Programming will start after the CS pin is brought high. The low-to-high traition of the CS pin must occur during the low-time immediately after clocking in the D (LSB) data bit. The READY/BUSY status of the device can be determined by initiating a read status register (RDSR) itruction. If Bit =, the write cycle is still in progress. If Bit =, the write cycle has ended. Only the RDSR itruction is enabled during the write programming cycle. The AT8B/6B is capable of a 3-byte page write operation. After each byte of data is received, the five low-order address bits are internally incremented by one; the high-order bits of the address will remain cotant. If more than 3 bytes of data are tramitted, the address counter will roll over and the previously written data will be overwritten. The AT8B/6B is automatically returned to the write disable state at the completion of a write cycle. NOTE: If the device is not write-enabled (WREN), the device will ignore the write itruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to reinitiate the serial communication. Table -6. Address Key Address AT8B AT6B A N A 9 A A A Don t Care Bits A A A A 3. Timing Diagrams Figure 3-. Synchronous Data Timing (for Mode ) t CS CS V IH V IL tcss t CSH V IH t WH t WL V IL t SU t H V IH V IL VALID IN t V t HO t DIS SO V OH HI-Z HI-Z V OL AT8B/6B [Preliminary]

11 AT8B/6B [Preliminary] Figure 3-. WREN Timing Figure 3-3. WRDI Timing Figure 3-4. RDSR Timing CS INSTRUCTION DATA OUT HIGH IMPEDANCE SO MSB

12 Figure 3-. WRSR Timing CS INSTRUCTION 6 DATA IN 4 3 SO HIGH IMPEDANCE Figure 3-6. CS READ Timing INSTRUCTION BYTE ADDRESS SO HIGH IMPEDANCE MSB 6 DATA OUT 4 3 Figure 3-. WRITE Timing CS INSTRUCTION BYTE ADDRESS DATA IN SO HIGH IMPEDANCE AT8B/6B [Preliminary]

13 AT8B/6B [Preliminary] Figure 3-8. HOLD Timing CS t CD t CD t HD HOLD t HD t HZ SO t LZ 3

14 4. AT8B Ordering Information Ordering Code Voltage Package Operation Range AT8B-PU (Bulk form only).8 8P3 AT8BN-SH-B () (NiPdAu Lead Finish).8 8S AT8BN-SH-T () (NiPdAu Lead Finish).8 8S AT8B-TH-B () (NiPdAu Lead Finish).8 8A AT8B-TH-T () (NiPdAu Lead Finish).8 8A AT8BY6-YH-T () (NiPdAu Lead Finish).8 8Y6 AT8BD3-DH-T ().8 8D3 AT8BU3-UU-T ().8 8U3- AT8B-W- (3).8 Die Sale Lead-free/Halogen-free/ Industrial Temperature ( 4 to 8 C) Industrial Temperature ( 4 to 8 C) Notes:. B denotes bulk.. -T deontes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP, SOT3, and dbga = K per reel. 3. Available in waffle pack, tape and reel, and wafer form; order as SL88 for inkless wafer form. Bumped die available upon request. Please contact Serial Interface Marketing. Package Type 8P3 8-lead,.3 Wide, Plastic Dual Inline Package (PDIP) 8S 8-lead,. Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8Y6 8-lead,. mm x 3. mm Body,. mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP x3 mm) 8D3 8-lead,.8 mm x. mm Body, Ultra axlanda Grid Array (ULLGA) 8U3-8-ball, die Ball Grid Array Package (dbga) Optio.8 Low Voltage (.8 to.v) 4 AT8B/6B [Preliminary]

15 AT8B/6B [Preliminary]. AT6B Ordering Information Ordering Code Voltage Package Operation Range AT6B-PU (Bulk form only).8 8P3 AT6BN-SH-B () (NiPdAu Lead Finish).8 8S AT6BN-SH-T () (NiPdAu Lead Finish).8 8S AT6B-TH-B () (NiPdAu Lead Finish).8 8A AT6B-TH-T () (NiPdAu Lead Finish).8 8A AT6BY6-YH-T () (NiPdAu Lead Finish).8 8Y6 AT6BD3-DH-T ().8 8D3 AT6BU3-UU-T ().8 8U3- AT6B-W- (3).8 Die Sale Lead-free/Halogen-free/ Industrial Temperature ( 4 to 8 C) Industrial Temperature ( 4 to 8 C) Notes:. B denotes bulk.. -T deontes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP, SOT3, and dbga = K per reel. 3. Available in tape and reel and wafer form; order as SL88 for inkless wafer form. Bumped die available upon request. Please contact Serial Interface Marketing. Package Type 8P3 8-lead,.3" Wide, Plastic Dual Inline Package (PDIP) 8S 8-lead,." Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8Y6 8-lead,. mm x 3. mm Body,. mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP x3mm) 8D3 8-lead,.8 mm x. mm Body, Ultra axlanda Grid Array (ULLGA) 8U3-8-ball, die Ball Grid Array Package (dbga) Optio.8 Low Voltage (.8 to.v)

16 6. Packaging Information 8P3 PDIP E E N Top View c ea End View D D e A A COMMON DIMENONS (Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE A. A..3.9 b.4.8. b b c.8..4 b3 4 PLCS b b L D D. 3 E E Side View e. BSC ea.3 BSC 4 L..3. Notes: R. This drawing is for general information only; refer to JEDEC Drawing MS-, Variation BA, for additional information.. Dimeio A and L are measured with the package seated in JEDEC seating plane Gauge GS D, D and E dimeio do not include mold Flash or protrusio. Mold Flash or protrusio shall not exceed. inch. 4. E and ea measured with the leads cotrained to be perpendicular to datum.. Pointed or rounded lead tips are preferred to ease iertion. 6. b and b3 maximum dimeio do not include Dambar protrusio. Dambar protrusio shall not exceed. (. mm). 3 Orchard Parkway San Jose, CA 93 TITLE 8P3, 8-lead,.3" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 /9/ REV. B 6 AT8B/6B [Preliminary]

17 AT8B/6B [Preliminary] 8S JEDEC SOIC C E E N L Top View End View e B A COMMON DIMENONS (Unit of Measure = mm) D Side View A SYMBOL MIN NOM MAX NOTE A.3. A.. b.3. C.. D 4.8. E E.9 6. e. BSC L.4. 8 Note: These drawings are for general information only. Refer to JEDEC Drawing MS-, Variation AA for proper dimeio, tolerances, datums, etc. //3 R E. Cheyenne Mtn. Blvd. Colorado Springs, CO 896 TITLE 8S, 8-lead (." Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S REV. B

18 8A TSSOP 3 Pin indicator this corner E E L N Top View L End View b e D Side View A A COMMON DIMENONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D , E 6.4 BSC E , A. A.8.. b e.6 BSC L.4.6. L. REF Notes:. This drawing is for general information only. Refer to JEDEC Drawing MO-3, Variation AA, for proper dimeio, tolerances, datums, etc.. Dimeion D does not include mold Flash, protrusio or gate burrs. Mold Flash, protrusio and gate burrs shall not exceed. mm (.6 in) per side. 3. Dimeion E does not include inter-lead Flash or protrusio. Inter-lead Flash and protrusio shall not exceed. mm (. in) per side. 4. Dimeion b does not include Dambar protrusion. Allowable Dambar protrusion shall be.8 mm total in excess of the b dimeion at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is. mm.. Dimeion D and E to be determined at Datum Plane H. /3/ R 3 Orchard Parkway San Jose, CA 93 TITLE 8A, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 8A REV. B 8 AT8B/6B [Preliminary]

19 AT8B/6B [Preliminary] 8Y6 Mini MAP A D b (8X) Pin Index Area E E Pin ID L (8X) D A A e (6X). REF. A3 COMMON DIMENONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D. BSC E 3. BSC D.4..6 E A A... A - -. A3. REF L..3.4 e. BSC b...3 Notes:. This drawing is for general information only. Refer to JEDEC Drawing MO-9, for proper dimeio, tolerances, datums, etc.. Dimeion b applies to metallized terminal and is measured between. mm and.3 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimeion should not be measured in that radius area. 8/6/ R 3 Orchard Parkway San Jose, CA 93 TITLE 8Y6, 8-lead. x 3. mm Body,. mm Pitch, Utlra Thin Mini-Map, Dual No Lead Package (DFN),(MLP x3) DRAWING NO. 8Y6 REV. C 9

20 8D3 - ULLGA D e 8 6 b L PIN # ID E PIN # ID A A e b TOP VIEW DE VIEW BOTTOM VIEW COMMON DIMENONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A.4 A.. D..8.9 E...3 b... e.4 TYP e. REF L..3.3 // R E. Cheyenne Mtn. Blvd. Colorado Springs, CO 896 TITLE 8D3, 8-lead (.8 x. mm Body) Ultra Leadframe Land Grid Array (ULLGA) D3 DRAWING NO. 8D3 REV. AT8B/6B [Preliminary]

21 AT8B/6B [Preliminary]. Revision History Lit No. Date Comments 8B /8 Changed Endurance parameter on page 6 8A 9/ Initial document release.

22 Headquarters International Atmel Corporation 3 Orchard Parkway San Jose, CA 93 USA Tel: (48) 44-3 Fax: (48) 48-6 Atmel Asia Room 9 Chinachem Golden Plaza Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (8) -98 Fax: (8) -369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP Saint-Quentin-en- Yvelines Cedex France Tel: (33) Fax: (33) Atmel Japan 9F, Tonetsu Shinkawa Bldg Shinkawa Chuo-ku, Tokyo 4-33 Japan Tel: (8) Fax: (8) Product Contact Web Site Technical Support s_eeprom@atmel.com Sales Contact Literature Requests Disclaimer: The information in this document is provided in connection with Atmel products. No licee, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL S WEB TE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN- TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUNESS INTERRUPTION, OR LOSS OF INFORMATION) ARING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSBILITY OF SUCH DAMAGES. Atmel makes no representatio or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specificatio and product descriptio at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applicatio. Atmel s products are not intended, authorized, or warranted for use as components in applicatio intended to support or sustain life. 8 Atmel Corporation. All rights reserved. Atmel, logo and combinatio thereof, and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

SPI Serial EEPROMs AT25010 AT25020 AT SPI, 1K Serial E 2 PROM. Features. Description. Pin Configurations 8-Pin PDIP. 1K (128 x 8) 2K (256 x 8)

SPI Serial EEPROMs AT25010 AT25020 AT SPI, 1K Serial E 2 PROM. Features. Description. Pin Configurations 8-Pin PDIP. 1K (128 x 8) 2K (256 x 8) Features Serial Peripheral Interface (SPI) Compatible Supports SPI Modes (,) and 3 (1,1) Low-Voltage and Standard-Voltage Operation 5. (V CC = 4.5V to 5.5V).7 (V CC =.7V to 5.5V) 1.8 (V CC = 1.8V to 3.6V).1