Instruction-Level Power Consumption Estimation of Embedded Processors for Low-Power Applications

Transcription

1 Instruction-Level Power Consumption Estimation of Embedded Processors for Low-Power Applications S. Nikolaidis and Th. Laopoulos Electronics Lab., Physics Dept., Aristotle University of Thessaloniki, Thessaloniki, 54006, Greece. Abstract: A power consumption measurement framework for embedded processing systems is presented in this work. Given an assembly or machine level program as input to this setup, the energy consumption of the specific program in the specific processing systems may be estimated. The instruction level power models are derived based on the power supply current measurement technique. The instantaneous variations of the power supply current provide the appropriate information for the accurate estimation of the power consumption at different operating situations of the processor (core) and of the overall processing system as well (consumption of peripheral units). The proposed instantaneous current measuring approach, along with the execution of special test programs for analysis of inter-instruction effects provides a clear insight information of the power behavior of embedded processing systems. Keywords: low-power design, embedded microprocessors, current measurement, power consumption, powers modeling 1. INTRODUCTION The increasing popularity of low power mobile phones, computers and other embedded computing applications drives the need for analyzing and optimizing power consumption in all parts of a system. Software constitutes nowadays a major part of such systems, where power is a constraint, and also has a significant contribution to the overall power consumption [1]. In order to analyze systematically and assess this impact, it is important to start at the most practical and fundamental level the instruction level. Accurate modeling and analysis at this level is essential in order to evaluate the software in terms of power consumption, and also to help software developers in their search for low power software implementations [2-4]. At present, power measurement tools focus mainly on the lower levels of the design; at the circuits level, at the logic level, and to a limited extend at the RT level [5]. Generally, these are very time-consuming and impractical techniques for the evaluation of the power consumption of embedded software. Moreover, they can not even be applied in most cases, due to the lack of availability of circuit and gate level information of the embedded processors. The embedded processors currently used in designs are of two kinds; the off-the-shelf microprocessors and the embedded cores. In the first case, the information available is whatever is usually included in the data books, while in the second case, the designer has logic/timing simulation models as a design verification help. In neither case the lower level information is available for the power analysis of the software. There are many advantages in developing an instruction-level power consumption model for a processor: a)estimation of the power cost to the software component of a system, b)verification of overall system's power budget, c)useful information for high-level design decisions such as hardwaresoftware partitioning, d)development of automated code generation tools with low power features, etc. 2. POWER CONSUMPTION Modern microprocessors are extremely complex systems, consisting of several interacting functional blocks. However, this internal complexity is hidden behind a simple interface the instruction set. Thus,

2 it seems rather logical to consider the power consumption of individual instructions, in order to build a model of the energy consumption of this complex system. Furthermore, each instruction involves specific processing activities across various units of the processor. These processing activities are performed by associated circuit activities which are characteristic for each instruction, and therefore vary with different instructions. Executing repeatedly certain instruction sequences, provides a means of evaluation for the power cost of these effects. Thus the sum of the power costs of the each instruction that is executed in a program, increased by the power cost of the inter-instruction effects, forms an estimate for the power cost of the program. Different techniques have been proposed for the estimation of the impact of software to the overall power consumption of a given processor. The common methodology is based on the derivation of instruction level power models by measuring the average current of the each executed instruction of the processor. The average power, P, consumed by a microprocessor while running a program is given by: P=IxVcc, where I is the average current and Vcc is the supply voltage. The energy, E, consumed by a prrjudp LV IXUWKHU JLYHQ E\ ( 3[1[2 ZKHUH 1 LV the number of clock cycles taken by the program and 2 LV WKH FORFN SHULRG 7KXV WKH DELOLW\ WR PHDVXUH WKH current drawn by the CPU during the execution of the program is essential for measuring its power/energy cost. Other teams have proposed a simple and practical technique in order to measure this current [2,3,4]. The power supply connections to the CPU are isolated from the rest of the system. A test program is executed, containing a set of repeated instructions (instruction sequence). The current waveform is then periodic, and an average value can be obtained from a standard off-the-shelf digital milliamperes meter. This inexpensive low-resolution approach seems to work well enough for this measurement. This technique was directly applied in the case of the Intel 486DX2 and the Fujitsu DSP, where the CPUs were parts of actual evaluation boards. Also, a similar technique was followed for modeling the power of the instructions of the ARM7TDMI processor and Motorola DSP in the SOFLOPO project [7,8]. A variation of the current measurement method that used a digitizing oscilloscope to measure instantaneous power was proposed in [6] to develop a power model for the JF and HD implementations of the i960 family. However, the current measurements was taken from the voltage drop at a resistor set directly in the current supply network influencing the actual level of the voltage applied to the chip and thus creating an offset noise on the current values, and consequently reducing the accuracy of the method. 3. POWER MODELING ANALYSIS The basic parameters that define the instructionlevel power consumption model of a processor should be considered first. These are actually the different operating situations of the circuitry, which are imposed by the software (instructions). The effect of each one of these situations on the power consumption should be analyzed. Special programs have to be derived for measuring the effect of each one of these parameters in the total power budget of any instruction. The basic parameters are: Instruction Base Cost: The base cost of an instruction may be thought of as the cost associated with the basic processing action needed to execute the instruction. The base power cost multiplied by the number of non-overlapped cycles needed to execute the instruction is its base energy cost. Effect of Circuit State: Given an instruction sequence, using base costs of the individual instructions to model the cost of the sequence, tends to underestimate the cost. This is so, because costs do not account the effect of the change in circuit state when two different instructions are executed consecutively. The concept of the "circuit state overhead" for a pair of instructions is needed to represent this effect. Effect of Cache Misses: For a cache miss, a certain cycle penalty has to be added to the

3 instruction time. As the base cost for instructions with memory operands are determined in the context of cache hits, a cache miss will lead to extra cycles being consumed, which leads to an energy penalty. Effect of Resource Constraints: Resource constraints in the CPU can lead to stalls, e.g. pipeline stalls. They cause an increase in the number of cycles needed to execute a sequence of instructions. It is well known that in digital systems there is a strong relation between the power consumption on the data that has to be processed. Consequently, prior to measuring power for the instruction set a number of variations in the assembly instructions that might influence power consumption has to be examined. In this way, the effect of the different source and destination registers on the measured power, the effect of the operand values, the effect of conditionally executed instructions as well as the effect of the various addressing modes have to be examined. Moreover, since the addressing mode has been proved to have significant influence on the power consumption [2,8] instructions with different addressing modes are considered as different instructions and examined separately. The above analysis is based on theoretical and "average current" information about the power consumption. It is therefore expected that a detailed information about the current waveforms should reveal more complex situations and enhance our knowledge about the software power consumption. 4. CPU's ANALYSIS The proposed current measurement approach aims to overcoming the insufficiencies of the previous methods mentioned above. The instruction level power models may now be derived based on the "instantaneous" current variations measured by a high-accuracy and high-speed automated measurement and data acquisition setup. The main task is to be performed by a high frequency oscilloscope capable of monitoring the instantaneous power supply current variations of the processor core. This measurement approach is similar to the Built-In Self Test (BIST) techniques used for testing high frequency analog circuits (monitoring the current, drawn by the circuit under test, results to evaluation of the different operating conditions). By applying proper timing and signature analysis techniques to these measurements, the power consumption of each instruction sequence used in the software may be estimated. The success of supply current monitoring in digital CMOS integrated circuits (IDDQ testing) has prompted researchers to investigate the feasibility of monitoring supply current as power consumption evaluation methodology A number of different current sensors for current monitoring have been proposed in the literature. All these sensors insert a current sensing device on the circuit s power supply path. A voltage drop across the sensing device results as the current passes through it. Drawbacks of this voltage drop include performance degradation of the circuit under test due to voltage variations etc. The resulting V DD voltage can usually be expressed as the sum of different voltage components, some of them being "I DD - independent" and some being "I DD - dependent". The resulting impedance in the supply current path (illustrated in Fig. 1). can cause an unacceptable degradation in the performance of the processing circuit under test, due to the induced noise and variations. Designing for small values of sensing circuit's impedance reduces the impact of the sensor on the performance of the processing circuit by reducing V DD variations [Fig.1] which in turn reduces the sensitivity of the sensor. These considerations about measurement accuracy are essential for power consumption estimation of embedded processing systems although they are not usual in other cases of current mode testing of digital circuits. For example in digital circuit I DDQ testing, high current sensor sensitivity is not required because the sensor only needs to distinguish two values of current which are typically at least one or more orders of magnitude apart. The situation of current testing in cases as the one presented here is

4 more similar to analog circuits current testing, where both a high sensitivity and a low impedance value are required for acceptable performance. Most current sensors proposed in the literature use a resistor or a MOS transistor biased in the triode region as the current sensing device. The voltage drop across the sensing device is used as the current value indicator. Such sensing devices tradeoff sensitivity for impact on the performance of the circuit under test. Yet the main reason for choosing this type of sensing devices is the need for a built-in configuration, which is not the case here. As the implementation of the current sensing circuit is free from the microelectronics technology and other limitations of the built-in solutions, the possible bipolar configurations may offer a highly competitive alternative in terms of frequency range and accuracy. SENSING CIRCUIT V DD POWER SUPPLY MIRROR I DD - PROCESSING SYSTEM MEASUREMENT CONFIGURATION (D.S.O.) SENSING CIRCUIT Fig. 1. Diagram of the current measurement scheme Improved current mirroring configurations based on operational amplifiers offer the desired characteristic of monitoring signals with a large DC component and smaller AC components which are of particular interest. As mentioned before, it is necessary to keep the impedance of the sensing circuit at low values because it induces a significant noise voltage during the switching of surge current components. This may be achieved either by proper design of the current sensing circuit or by inserting a decoupling capacitor to the power supply node of the processing unit (V DD ), in order to keep the total impedance value (and the resulting noise) low. This phenomenon is stronger especially at high frequencies zone where the processing units are operating usually. Such a feature is of major importance in this case, where all information about small and short variations should be taken into account in order to explore the different power consumption costs of the previously mentioned inter instruction phenomena. A number of appropriate experiments will be proceeded for the characterization of the power components of each instruction. The instruction base cost will be determined by executing programs containing a loop of several instances of the given instructions. Special programs will also be derived for the characterization of the inter-instruction effects corresponding to the power overhead, which results by executing different instructions in sequence due to the circuit stage changes. Furthermore, specific software structures for creating conditions for pipeline stalls and cache misses will be derived to measure the corresponding power costs. The above experiments will be realized for various operand values and different processing conditions so that the influence of all the factors related to power consumption to be taken into account. All the above power costs will then represent the software related power consumption and will be tabulated in specific tables. It is certainly expected that the information contained in these cost-tables may result in a form of data library, for the automated estimation of the power consumption

5 of different software solutions. To minimize the size of these tables, especially for processors with rich instruction sets, an exploration for the existence of instruction classes with similar power costs will be taken place leading to more compact tables without significant loss in accuracy. The proposed current measuring approach certainly provides more insight information on the power consumption behavior of each processor. An accurate model of the power consumption due to the different instructions or instruction sequences may be derived. The development of software solutions with minimal power consumption may then be achieved on the basis of such modeling. The established set up can also be used for measuring the power consumption of the other components at the board level. In this way, the power cost of the memory accesses the power consumption on DC/DC converters and various microprocessor peripherals per cycle can be measured leading to analogous cycled power models for these components. Also, exploiting the capability for making differential measurements accurate power models for the busses can be created. Having such models, accurate power consumption estimates can be derived at the system level, which may be used for exploring effectively different system implementations very early in the design cycle. 5. CONCLUDING COMMENTS A method for the power consumption estimation of embedded processing systems is presented in this work. The associated hardware configuration for the measurement of the instantaneous current variations I DD, along with the theoretical analysis for the different instruction-level effects which affect the total power consumption have been presented. The exploration of these effects is expected to result to a software tool, for the automated estimation of the power consumption of different software solutions for embedded systems. Such tools are expected to lead the way to embedded systems optimization in terms of power consumption, hardware/software mapping, etc. 6. REFERENCES [1] A. Chandrakasan, S. Sheng, R. Broderson, Low Power CMOS Digital Design, IEEE J. of Solid State Circuits, SC-27, , April [2] V. Tiwari, S. Malik, A. Wolfe, Power Analysis of Embedded Software: A First Step Towards Software Power Minimization, IEEE Trans. VLSI Systems, Vol.2, N.4, pp , Dec [3] V. Tiwari, S. Malik, A. Wolfe, M. Tien-Chien Lee, Instruction Level Power Analysis and Optimization of Software, Int. Conf. on VLSI Design, Banglore, India, Jan [4] M. T.-C. Lee, V. Tiwari, S. Malik, M. Fujita, Power Analysis and Minimization Techniques for Embedded DSP Software, IEEE Trans. on VLSI Systems, pp , Mar [5] F.N. Najm, A Survey of Power Estimation Techniques in VLSI Circuits, IEEE Trans. on VLSI Systems, pp , Dec [6] J. Rassel and M.F. Jacome, «Software Power Estimation and Optimization for High Performance, 32-bit Embedded Processors,» Proc. of ICCD 98. [7] G. Sinevriotis and Th. Stouraitis, «Power Analysis of the ARM 7 Embedded Microprocessor», Proc. of the 9th Inter. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 99), pp , Greece, Oct [8] T. Stouraitis, «Instrumentation setup», Deliverable 2.1, Low Power Software Development for Embedded Applications, SOFLOPO, ESD project 25403, [9] Ph. Givelin, M. Bafleur, E. Tournier, Th. Laopoulos and S. Siskos, "Application of a CMOS current mode approach to on-chip current sensing in smart power circuits", IEE Proceedings - Circuits, Devices and Systems, V.142, N.6, 1995 [10] Siskos S., Laopoulos Th., Hatzopoulos A., Bafleur M., "A current conveyor based BIC sensor for current monitoring in mixed signal circuits", IEEE Int. Conference on Electronics, Ciircuits and Systems, Rhodos, Greece, 1996 [11] A. Hatzopoulos, S. Siskos and Th. Laopoulos, "Current conveyor based test structures for mixedsignal circuits", IEE Proceedings - Circuits, Devices and Systems, V.144, N.4, 1997