True Random Number Generation TRNG Master SETI
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1 True Random Number Generation Master SETI Jean-Luc Danger Jean-Luc Danger
2 Outline overview architecture post-processing and tests Conclusions, Questions 2 Jean-Luc Danger
3 RNG Applications Cryptography Key generation Symmetric/asymetric crypto Stream ciphering (if deterministic RNG) Initialization vector For cryptographic operating modes Authentication Challenges Nonce Protection Masks to thwart Side-Channel Attacks System validation page 3 Monte-Carlo simulation Statistical analysis Channel emulation IC test Games, gambling 3 Jean-Luc Danger
4 RNG types Pseudo Random number (PRNG) Deterministic Fast Periodic (based generally on LFSRs) Adapted for stream ciphering True Random Number generator () Unpredictable Use physical sources Hybrid Random Number generator (HRNG) used as a seed of PRNG 4 Jean-Luc Danger
5 requirements Security requirements Unpredictibility Uniform distribution Robustness to attacks Testability Design requirements Low complexity Low consumption Fast speed (optionnally) 5 Jean-Luc Danger
6 Outline overview architecture post-processing and tests Conclusions, Questions 6 Jean-Luc Danger
7 Architecture 2 main blocks Entropy Source Entropy extractor 2 optional blocks Postprocessing Embedded Tests 7 Jean-Luc Danger
8 Source of randomness Two types of randomness source: Non Physical noise Keyboard and mouse activity, Processor load, network data rate, Physical noise Noise in electronics circuits Others: desintegration of radioactive atomic kernel 8 Jean-Luc Danger
9 Noise in electronics circuit Noise = Sum of different phenomenon: Thermal noise 1/F noise Shot noise Popcorn noise Crosstalk Interference 9 Jean-Luc Danger
10 Randomness extraction To sample the noise at source level Use of a sample/hold circuit, or memory element 10 Jean-Luc Danger
11 Randomness extraction Memory elements Noise Axis Horizontal: phase noise (frequency) or jitter (time) Vertical: amplitude noise 11 Jean-Luc Danger
12 Phase noise Combination of random jitter and deterministic jitter (unwanted) 12 Jean-Luc Danger
13 Amplitude noise Also called vertical noise The signal is at the boundary of 0 and 1 level, around the "metastable state" MSS (~Vdd/2) 13 Jean-Luc Danger
14 Metastability phenomenon 14 Jean-Luc Danger
15 types Jitter-based One jittery clock samples another jittery clock Metastability-based The bi-stable is placed in the MSS state, its output depends on the vertical noise Mixed Exploits both phenomemon 15 Jean-Luc Danger
16 Two-Ring oscillator Kohlbrenner et al. Paul Kohlbrenner and Kris Gaj. An embedded true random number generator for FPGAs. In Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, Jean-Luc Danger
17 Two-Ring oscillator Rationale The two clocks have roughly the same frequency There is a race between the rising edges: Sj = 1 if rising_edge(c0) is ahead of rising_edge(c1), else 0 This race depends on the jitter RNG = LSB of the number of rising_edge(c1) between two rising_edge(c0) 17 Jean-Luc Danger
18 Multiple ROs Wold et al. Knut Wold and Chik How Tan. Analysis and enhancement of random number generator in fpga based on oscillator rings. In ReConFig, pages , Jean-Luc Danger
19 Two-Ring oscillator with LFSR Tcacik Thomas Tkacik. A hardware random number generator. In BurtonS. Kaliski, ÇetinK. Koç, and Christof Paar, editors, Cryptographic Hardware and Embedded Systems - CHES 2002, volume 2523 of Lecture Notes in Computer Science, pages Springer Berlin Heidelberg, Jean-Luc Danger
20 PLL-based Fischer et al. Viktor Fischer, Milos Drutarovský, Martin Simka, and Nathalie Bochard. High performance true random number generator in altera stratix fplds. In Field Programmable Logic and Application, volume 3203 of Lecture Notes in Computer Science, pages Springer Berlin Heidelberg, Jean-Luc Danger
21 Metastability-based Kinniment et al. Bistable analog cell D.J. Kinniment and E.G. Chester. Design of an on-chip random number generator using metastability. In Proceedings of the 28 th European Solid-State Circuit Conference., Jean-Luc Danger
22 Metastability_based Intel Ivy bridge Bistable cell Trimming circuit to keep the metastable state Mike Hamburg, Paul Kocher, and Mark E. Marson. Analysis of intel s ivy bridge digital random number generator, March, Jean-Luc Danger
23 Mixed Open Loop A chain of latches with D = C Danger, J. L., Guilley, S., & Hoogvorst, P. (2009). High speed true random number generator based on open loop structures in FPGAs. Microelectronics journal, 40(11), Jean-Luc Danger
24 Outline overview architecture post-processing and tests Conclusions, Questions 24 Jean-Luc Danger
25 Post processing Mandatory process: The source of entropy is biased by the environment The extraction block is not efficient enough The samples are correlated 25 Jean-Luc Danger
26 Post processing for better entropy Goal: To increase the entropy by reducing the Bit rate Or data compression Classical methods: XOR corrector N bits are XORed to get one output bit Constant Bit rate reduction (N) XOR construction proposed by M. Dichtl* Von Neumann corrector 2 identical bits: freeze 2 different bits: 1 if "10", 0 if "01" Variable Bit rate reduction (at least 4) * Dichtl, M. (2007, January). Bad and good ways of post-processing biased physical random numbers. In Fast Software Encryption (pp ). Springer Berlin Heidelberg. 26 Jean-Luc Danger
27 Cryptographic Post processing Goal: To increase unpredictibility Exploits non-linearity properties The entropy is the same Hash function Unpredictability ensures by One-way function Symmetric cryptography cipher Could be the same as the crypto block. 27 Jean-Luc Danger
28 On-Line tests Embedded tests = health tests To ensure dynamically that the output bits have good randomness property : Under environmental variations Under attacks Discussed in "randomness assesment" session 28 Jean-Luc Danger
29 Bit Rate Often considered as a secondary parameter 1Mb/s is generally sufficient for most applications Specific cases for High Bit Rate Quantum cryptography Quantum protocol is very greedy in randomness for unconditionnal security over an optical channel High speed networks To exchange sessions keys periodically and provide resiliency against attacks (SCA) 29 Jean-Luc Danger
30 Security evaluation requirements In theory: Randomness: Entropy Shannon Min-Entropy Unpredictability: Conditionnal Entropy In practice Stochastic process H( state_{i} state_{i-1} )? Assesment Methods Statistical tests Build a stochastic model H (x)= p(x)log 2 ( p( x)) x is a bit vector H x = max( p ( x )) log 2 i 30 Jean-Luc Danger
31 Statistical tests Off-line tests FIPS140-2 NIST SP DIEHARD AIS31 On-line tests To detect in real time failures abnormal behaviour Health tests partial statistical tests 31 Jean-Luc Danger
32 Technology validation methodologies FIPS140-2 tests Originally: 4 tests applied on bit sequences Can be embedded in the circuit: Monobit (pr(bit=0)) Poker : uniform distribution of 4-bit groups Runs : check the number of run sequences of 0 and 1 of length between 1 and 6 Long runs : no run of 0 or 1 with a length equal or greater than 26 should occur NIST FIPS (Federal Information Processing Standards). Security Requirements for Cryptographic Modules publication 140-2, May Jean-Luc Danger
33 Technology validation methodologies BSI s approach AIS31/AIS20 Strongly common criteria oriented New approach: testing output as well as the randomness source 9 statistical tests are proposed: Test T0 (evaluates the well-known birthday problem) Tests T1 to T4 (inspired by the earlier FIPS140 health tests) Test T5 (autocorrelation test) Tests T6 and T7 (uniform distribution tests) Test T8 (entropy estimation) 33 Jean-Luc Danger
34 Technology validation methodologies BSI s approach AIS31/AIS20 Recommends using on-line tests, for example: Entropy source failure tests Statistical defect tests on the raw random sequence Statistical defect tests on the post-processed sequence Defines classes (PTG.x) PTG.1 represents the lower-end class and PTG.2 and PTG.3 the higher-end classes PTG.2 adds minimum entropy requirements for post-processed bits and introduces raw data online tests and entropy source stochastic model PTG.3 requires cryptographic post-processing (class DRG.3 or DRG.4) 34 Jean-Luc Danger
35 AIS31 classes 35 Jean-Luc Danger
36 Technology validation methodologies NIST s approach Drafted SP A, 90B and 90C SP A considers DRNG SP B considers entropy source design and validation SP C considers design of hybrid RNGs using SP B + SP A SP B defines requirements similar to BSI s AIS31 Two categories defined: Entropy source Full entropy source Minimal online health tests defined Lightweight runs detection test (repetition count test) Lightweight uniformity test (adaptive proportion test) 36 Jean-Luc Danger
37 Online tests 37 Jean-Luc Danger
38 Embedded test Custom sanity check Intel's Ivy bridge Use of standardized statistical tests Can be costly => partial tests 38 Jean-Luc Danger
39 attacks Passive attacks Observation of the activity Frequency of RO Register loads Allows the attacker to locate the Reverse Engineering Allows the attacker to locate the Active attacks Bias generated by fault injection Force the output or the on-line test alarm Trojans Bias generated at design or manufacturing stage 39 Jean-Luc Danger
40 Outline overview architecture post-processing and tests Conclusions, Questions 40 Jean-Luc Danger
41 Conclusions Necessity to assess Entropy and Unpredictability Statistical tests Model Necessity to embed Online test To detect abnormal behaviour Environment Attacks Future ISO standards in preparation Designing a is still a challenge Security To pass statistical tests To build a model To be robust against attacks + pure design challenges (next slide) 41 Jean-Luc Danger
42 design challenges Type of randomness extraction Type of Postprocessing Complexity Design automation Bit rate Testability (statistical and integrity tests) Power consumption => A test chip is Highly recommended 42 Jean-Luc Danger
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