Summary. Circuits for True Random Number Generation with On-Line Quality Monitoring. Applications of Random Numbers Generators (RNGs)

Size: px
Start display at page:

Download "Summary. Circuits for True Random Number Generation with On-Line Quality Monitoring. Applications of Random Numbers Generators (RNGs)"

Transcription

1 Summary Circuits for True Random Number Generation with On-Line Quality Monitoring Arnaud Tisserand CNRS, IRISA laboratory, CAIRN research team RAIM, June Motivations and context Randomness quality evaluation True random number generators (TRNGs) OCHRE circuits Implementation and evaluation results Conclusion, future prospects, references 2/4 Applications of Random Numbers Generators (RNGs) Lotteries, games and gambling Cryptography and security: key generation, initialization vectors, padding, nonces, stream ciphers, masking, blinding, randomization,... Probabilistic / randomized algorithms: Monte Carlo simulations, Las Vegas algorithms,... VLSI testing: random patterns, random schedules,... Digital communications: channel estimation/modeling, simulation,... 3/4 RNG Uses in Crypto Applications Encryption algorithms Digital signature schemes Authentication protocols Stream ciphers Key generation Padding Initialization vectors (IVs) Nonces Protection against side channel attacks: Masking (e.g. [] for AES) Blinding (e.g. blinded a b mod m for RSA [7] ) Random recoding for [k]p in ECC (e.g. [2]) Thomas talk 4/4

2 Probabilistic / Randomized Algorithms Random Numbers: Definition (/3) Numerical probabilistic algorithm: approximation of the correct result (using random choices) Examples: Buffon s needle ( /π), numerical integration, linear algebra,... Monte Carlo algorithm: always gives a result, but occasionally makes errors (incorrect result) Examples: primality tests (using Fermat s little theorem, Rabin-Miller), optimization,... E random drawings x = 4 x 2 = 6 x 3 = 2 x 4 = 7 x 5 = 5 S: random sequence Las Vegas algorithm: always gives a good result, but occasionally fails to give a result Examples: randomized quick-sort, some algorithms on graphs,... Problem in parallel randomized algorithms: initialization of many RNGs E (finite) set of numbers, n is the size of E x i the random numbers S : (x, x 2,..., x m ) sequence of random numbers (S length: m) 5/4 6/4 True random sequence: Random Numbers: Definition (2/3) equiprobable and uniform distribution P(x i = k) = n k E, i {, 2,..., m} statistical independence and non-predictability known numbers (x, x 2, x 3,..., x j ) non-reproducible: S S 2 S 3 RNG restart new number x j+ S : (x,..., x m ) S 2 : (y,..., y m ) S 3 : (z,..., z m ) 7/4 Random Numbers: Definition (3/3) Simple definition (B. Schneier): The output: looks random is unpredictable cannot be reproduced (for TRNGs) Standard definition (e.g. see D. Knuth [6, chap. 3]): The sequence of numbers (x, x 2, x 3,..., x m, x m ), with i, x i E, is random when the m numbers are: statistically independent uniformly distributed (equally probable) unpredictable Chapter 3, Random Numbers, from [6] D. E. Knuth. Seminumerical Algorithms, volume 2 of The Art of Computer Programming. Addison-Wesley, 3rd edition, 997 8/4

3 Random Sequences in Integrated Circuits Standard assumptions: 2 electrical states (voltages) as binary code: 0 and periodic sampling (at frequency f s ) Types of Random Number Generators Pseudo random number generator (PRNG): deterministic algorithms very high throughput and good statistical properties various algorithms quality/throughput/cost trade-offs state True random number generator (TRNG): THIS WORK non-deterministic algorithms (physical random source) limited throughput quality = func(environment parameters,... ) attacks 0 Hybrid random number generator (HRNG): TRNG PRNG output FUTURE WORK very high speed and very good quality selection needs more research 9/4 0/4 Randomness Quality Evaluation is Required Extract from [2] (988): Many generators have been written, most of them have demonstrably nonrandom characteristics, and some are embarrassingly bad. Randomness quality evaluation required at : design (ensures minimal randomness for ideal environment) run (check environment modifications, attacks) Randomness quality evaluation methods: mathematical and physical models statistical tests AND [2] S. K. Park and K. W. Miller. Random number generators: Good ones are hard to find. Communications of the ACM, 3(0):92 20, October 988 /4 Statistical Tests for Randomness Evaluation FIPS 40- (994): Security Requirements for Cryptographic Modules, 4 basic tests (removed in 40-2 version, 200/2002) AIS 3 (200+): Functionality Classes and Evaluation Methodology for Physical Random Number Generators. Specific tests for TRNGs NIST (2008+): A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications. More complete test suite DIEHARD (995): by G. Marsaglia, DIEHARDER (2003+): very complete test suite, maintained by R. Brown, TestU0: C library from P. L Ecuyer and R. Simard [9] (2007+) Universal test from U. Maurer [0] (992) 2/4

4 Statistical Tests Examples and Limitations FIPS 40- tests 20kb sequences Monobit: check that 9654 < #(S) < 0346 Results format Poker: split S into bit blocs, #Bi (S) number of blocs equal to X = P or F monobit poker long run run(0,) run(,) run(0,2) run(,2) run(0,3) run(,3) run(0,4) run(,4) run(0,5) run(,5) run(0,6+) run(,6+) FIPS 40- Statistical Tests Input: sequence S of bits (from the RNG) Output: PASS or FAIL X X X X X X X X X X X X X X X i ((0000)2, (000)2,..., ()2 ), with 0 i 5, check that χ25 :.03 < generator 5 X 6 #Bi (S) < i=0 x0 (*) FIPS 40- test results Mersenne twister x0 PPPPPPPPPPPPPPP xn = xn mod 23 many x0 9, 23233,... 37, 7,... PPPPPPPPPPPPPPP FPPPPPPPPPPPPPP FFPPPPPPPPPPPPP Run: check that #run(k, S) Ik for k 6 and k Ik [2267, 2733] 2 [079, 42] 3 [502, 748] 4 [223, 402] 5 [90, 223] 6+ [90, 223] xn = 33 xn mod 02,... FFPFFPPPPFPFPPF xn = xn +, 2, ,... FFPFPPPPPPPPPFP PFPPPPPPPPPPPPP Long run: check that k 34, #run(k, S) = 0 (*) some bad values for x0 Notation: run(k, S) = string of k consecutive 0s/s (i.e } or 0.{z.. } 0).{z k k 3/4 Historical Hardware TRNGs (/2) 4/4 Historical Hardware TRNGs (2/2) ATT Patent 946, source: P. Kohlbrenner YouTube: Self-Loading LEGO Dice Tower Dice-O-Matic 5/4 6/4

5 TRNGs Selection Physical noise source: quantum physics radioactive decay atmospheric noise thermal/johnson noise jitter in ring oscillator sampling meta-stability noises in circuits: /f, shot, popcorn, crosstalk,... Characteristics: throughput (? Mb/s) randomness quality (bias, entropy/bit, stability, effects of environment variations,... ) security fully integrated in the chip cost (silicon area, power consumption) VLSI implement. 7/4 Example of TRNG: Quantum Physics Source: White paper from ID Quantique (Switzerland): Random Number Generation using Quantum Physics, Apr ( photon source semi-transparent mirror photon? 50 % 0 50 % single-photon detectors Extract from IDQ white paper p. 7: The fact that a photon incident on such a component be reflected or transmitted is intrinsically random and cannot be influenced by any external parameters. Quantis-PCI-4M: random data rate 4 Mb/s ± 0 % (< % thermal noise contribution in randomness) 8/4 Basic Electronic Gates Free Running Ring Oscillator (RO) Inverter: a XOR: a b s s a 0 s 0 a 0 0 b 0 0 s 0 0 inverter: in out 0 0 S odd # of inverters (n) 0 0 ring oscillator period = f (n, delay(inv ),...) S Flip-flop: a clk s at clk edge: s(t + ) = a(t) φ random jitter (timing/phase instability) S φ period = f (n, φ,...) Remark: area scale is not respected 9/4 20/4

6 Towards a TRNG Example of Ring Oscillator (RO) Based TRNG RO RO RO 2 xor tree post processing random bits RO 2 RO 3. RO k f s on-line test alarm optional quality evaluation t output clk Remark: very limited randomness using only 2 ROs 2/4 Description: k free running ring oscillators f s is the sampling frequency post processing: enhance statistical parameters on-line quality test (environment variations, attacks,... ) 22/4 Post Processing Purpose: enhance statistical parameters of the output sequence reduce bias Pr(x = ) = ɛ (AIS 3: ɛ < 0.073) increase entropy per bit (the real randomness) Typical post processing methods: Von Neumann correction input bits (0,0) (0,) (,0) (,) output bit none 0 none Linear feedback shift register (LFSR) Hash function (e.g. SHA) Ciphering (e.g. AES) Resilient function (e.g. error code computations) Trade-off: entropy per bit, data rate, cost, quality RO Based TRNG Example [8] B. Sunar, W. J. Martin, and D. R. Stinson. A provably secure true random number generator with built-in tolerance to active attacks. IEEE Transactions on Computers, 56():09 9, January 2007 Description: k = 4 RO of 3 inverters resilient function: BCH(256, 3, 3) code mathematical model (but not realistic assumptions) data rate 2.5 Mb/s on FPGA Problems: very complex calibration (external measurement of the jitter!!!) too many transitions in the xor tree setup/hold violations in the flip-flop 23/4 24/4

7 Flip-Flop Setup/Hold Problems Correct flip-flop behavior: input signal must stable: slightly before the clock edge slightly after the clock edge setup hold There are TRNGs based on (mixing): ring oscillators and Improvement Example LFSR (linear feedback shift register), p(x) = n i=0 p ix i clk XOR XOR XOR XOR XOR p 0 p p 2 p 3 p n input output? Remarks: Mixed true and pseudo random architecture Limited jitter accumulation 25/4 26/4 Metastability Example of Metastability based TRNGs Proba= 2 metastable state Proba= 2 Principle: adjust delay d (w.r.t. d 2 ) to force flip-flop in metastable state stable states clk d output Example: flip-flop output in metastable state voltage random delay d 2 0 Remark: small amount of randomness (use multiple elements in practice) 27/4 28/4

8 Example of Measurements on FPGAs TRNG References [8] P. Kohlbrenner and K. Gaj. An embedded true random number generator for FPGAs. In Proc. Field Programmable Gate Arrays (FPGA), pages ACM, February 2004 TRNG from [4] (Altera Stratix II): [5] V. Fischer, M. Drutarovsky, M. Simka, and N. Bochard. High performance true random number generator in altera stratix FPLDs. In Proc. Field Programmable Logic and Applications (FPL), volume 3203 of LNCS, pages Springer, August 2004 Run test AIS [7] D. Schellekens, B. Preneel, and I. Verbauwhede. FPGA vendor agnostic true random number generator. In Proc. Field Programmable Logic and Applications (FPL), pages 6. IEEE, August 2006 Success percentage (%) [4] M. Dichtl and J. D. Golic. High-speed true random number generation with logic gates only. In Proc. Cryptographic Hardware and Embedded Systems (CHES), volume 4727 of LNCS, pages Springer, September [9] I. Vasyltsov, E. Hambardzumyan, Y.-S. Kim, and B. Karpinskyy. Fast digital TRNG based on metastable ring oscillator. In Proc. Cryptographic Hardware and Embedded Systems (CHES), volume 554 of LNCS, pages Springer, August TRNG by Dichtl and al Data rates (Mb/s) [3] J.-L. Danger, S. Guilley, and P. Hoogvorst. High speed true random number generator 9 6 based on open loop structures in FPGAs. Microelectronics Journal, 40(): , x 0 November /4 OCHRE Circuits (On-Chip Randomness Extraction) (/2) OCHRE V, 2009Q2 30/4 OCHRE Circuits (On-Chip Randomness Extraction) (2/2) 00 % OK mm mw (CMOS 30 nm.2 V STMicro) TRNG from [7] (0 RO with 3 inv.) PRNG (cellular automaton) 95 MHz 89 MHz FIPS 40- embedded statistical tests OCHRE V2, 200Q4 00 % OK 4 mm2 (CMOS 30 nm.2 V STMicro) TRNGs [8]/[9]/[4]/[20] FIPS 40- and AIS 3 tests AES 235/628/746/363 MHz 80 MHz 24 MHz We also have FPGA implementations (Xilinx, Altera and Actel). 3/4 32/4

9 OCHRE V2 Circuit Some Measurement Results (/2) frequency test [x000] µ+σ µ µ σ f s [MHz] B A 33/4 34/4 Some Measurement Results (2/2) TRNG Design and Use poker test χ 2 [x000] 00 0 µ+σ µ µ σ f s [MHz] B electromagnetic interferences circuit random source V dd EMI clk temperature entropy extraction At run : - statistical tests - attack detection At design : - physical/mathematical modeling - simulations post processing on-line test? OK OK random stream alarm quality evaluation results 35/4 36/4

10 Conclusion & Future Prospects TRNGs are important elements of security systems Randomness quality evaluation is very complex accurate models, simulations, measurements,... Embedded security systems on-line quality evaluation We have implementations for both ASIC and FPGA targets Future research topics: Very intensive measurements for various parameters and domains: V dd, temperature, electromagnetic radiations, clock variations,... Hybrid generators = TRNG + PRNG Design space exploration at system level References I [] M. Baudet, D. Lubicz, J. Micolod, and A. Tassiaux. On the security of oscillator-based random number generators. Journal of Cryptology, 24(2): , April 20. Special Issue on Hardware and Security. [2] T. Chabrier, D. Pamula, and A. Tisserand. Hardware implementation of DBNS recoding for ECC processor. In Proc. 44rd Asilomar Conference on Signals, Systems and Computers, pages 29 33, Pacific Grove, California, U.S.A., November 200. IEEE. [3] J.-L. Danger, S. Guilley, and P. Hoogvorst. High speed true random number generator based on open loop structures in FPGAs. Microelectronics Journal, 40(): , November [4] M. Dichtl and J. D. Golic. High-speed true random number generation with logic gates only. In Proc. Cryptographic Hardware and Embedded Systems (CHES), volume 4727 of LNCS, pages Springer, September [5] V. Fischer, M. Drutarovsky, M. Simka, and N. Bochard. High performance true random number generator in altera stratix FPLDs. In Proc. Field Programmable Logic and Applications (FPL), volume 3203 of LNCS, pages Springer, August [6] D. E. Knuth. Seminumerical Algorithms, volume 2 of The Art of Computer Programming. Addison-Wesley, 3rd edition, 997. [7] P. C. Kocher. Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems. In Proc. Advances in Cryptology (CRYPTO), volume 09 of LNCS, pages Springer, August 996. [8] P. Kohlbrenner and K. Gaj. An embedded true random number generator for FPGAs. In Proc. Field Programmable Gate Arrays (FPGA), pages ACM, February /4 38/4 References II References III [9] P. L Ecuyer and R. Simard. TestU0: A C library for empirical testing of random number generators. ACM Transactions on Mathematical Software, 33(4):22: 40, August [0] U. M. Maurer. A universal statistical test for random bit generators. Journal of Cryptology, 5(2):89 05, January 992. [] T. S. Messerges. Securing the AES finalists against power analysis attacks. In Proc. 7th International Workshop on Fast Software Encryption (FSE), volume 978 of LNCS, pages 50 64, New York, USA, April Springer. [2] S. K. Park and K. W. Miller. Random number generators: Good ones are hard to find. Communications of the ACM, 3(0):92 20, October 988. [3] R. Santoro, S. Roy, and O. Sentieys. Search for optimal five-neighbor FPGA-based cellular automata random number generators. In Proc. Int. Symp. Signals, Systems and Electronics (ISSSE), pages , Montreal, Canada, July [4] R. Santoro, O. Sentieys, and S. Roy. On-line monitoring of random number generators for embedded security. In Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pages , Taipei, Taiwan, May [5] R. Santoro, O. Sentieys, and S. Roy. On-the-fly evaluation of FPGA-based true random number generator. In Proc. Int. Symp. on VLSI (ISVLSI), pages IEEE Computer Society, May [6] R. Santoro, A. Tisserand, O. Sentieys, and S. Roy. Arithmetic operators for on-the-fly evaluation of TRNGs. In Proc. Advanced Signal Processing Algorithms, Architectures and Implementations XVIII, volume 7444, pages 2, San Diego, California, U.S.A., August SPIE. [7] D. Schellekens, B. Preneel, and I. Verbauwhede. FPGA vendor agnostic true random number generator. In Proc. Field Programmable Logic and Applications (FPL), pages 6. IEEE, August [8] B. Sunar, W. J. Martin, and D. R. Stinson. A provably secure true random number generator with built-in tolerance to active attacks. IEEE Transactions on Computers, 56():09 9, January [9] I. Vasyltsov, E. Hambardzumyan, Y.-S. Kim, and B. Karpinskyy. Fast digital TRNG based on metastable ring oscillator. In Proc. Cryptographic Hardware and Embedded Systems (CHES), volume 554 of LNCS, pages Springer, August [20] S.-K. Yoo, D. Karakoyunlu, B. Birand, and B. Sunar. Improving the robustness of ring oscillator TRNGs. ACM Transactions on Reconfigurable Technology and Systems, 3(2):9: 30, May 200. NIST references on RNG: 39/4 40/4

11 The end, some questions? Contact: CAIRN Group IRISA Laboratory, CNRS INRIA Univ. Rennes 6 rue Kérampont, BP 8058, F Lannion cedex, France Thank you 4/4

True Random Number Generation TRNG Master SETI

True Random Number Generation TRNG Master SETI True Random Number Generation Master SETI Jean-Luc Danger Jean-Luc Danger Outline overview architecture post-processing and tests Conclusions, Questions 2 Jean-Luc Danger RNG Applications Cryptography

More information

The Design and Analysis of a True Random Number Generator in a Field Programmable Gate Array. By Paul Kohlbrenner November 20, 2003

The Design and Analysis of a True Random Number Generator in a Field Programmable Gate Array. By Paul Kohlbrenner November 20, 2003 The Design and Analysis of a True Random Number Generator in a Field Programmable Gate Array By Paul Kohlbrenner November 20, 2003 Presentation Organization 1. Thesis goal 2. The need for random bits in

More information

A True Random Number Generator Based On Meta-stable State Lingyan Fan 1, Yongping Long 1, Jianjun Luo 1a), Liangliang Zhu 1 Hailuan Liu 2

A True Random Number Generator Based On Meta-stable State Lingyan Fan 1, Yongping Long 1, Jianjun Luo 1a), Liangliang Zhu 1 Hailuan Liu 2 This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. IEICE Electronics Epress, Vol.* No.*,*-* A True Random Number Generator Based On Meta-stable

More information

A Closer Look at Security in Random Number Generators Design

A Closer Look at Security in Random Number Generators Design A Closer Look at Security in Random Number Generators Design Viktor Fischer To cite this version: Viktor Fischer. A Closer Look at Security in Random Number Generators Design. Werner Schindler; Sorin Huss.

More information

True Random Number Generator using Solar Output Characteristics

True Random Number Generator using Solar Output Characteristics True Random Number Generator using Solar Output Characteristics Stephen Ritter, Tyler Pigg, Connor Brown, and Biswajit Ray Presenter: Biswajit Ray, Assistant Professor Electrical and Computer Engineering,

More information

Stream Ciphers. Çetin Kaya Koç Winter / 13

Stream Ciphers. Çetin Kaya Koç   Winter / 13 Çetin Kaya Koç http://koclab.cs.ucsb.edu Winter 2016 1 / 13 Block Ciphers Cryptography Plaintext: M i with M i = n, where n is the block length (in bits) Ciphertext: C i with C i = m, where m n, however,

More information

ECC1 Core. Elliptic Curve Point Multiply and Verify Core. General Description. Key Features. Applications. Symbol

ECC1 Core. Elliptic Curve Point Multiply and Verify Core. General Description. Key Features. Applications. Symbol General Description Key Features Elliptic Curve Cryptography (ECC) is a public-key cryptographic technology that uses the mathematics of so called elliptic curves and it is a part of the Suite B of cryptographic

More information

Stream Ciphers. Koç ( ucsb ccs 130h explore crypto fall / 13

Stream Ciphers.   Koç (  ucsb ccs 130h explore crypto fall / 13 Stream Ciphers Çetin Kaya Koç http://cs.ucsb.edu/~koc koc@cs.ucsb.edu Koç (http://cs.ucsb.edu/~koc) ucsb ccs 130h explore crypto fall 2014 1 / 13 Block Ciphers Plaintext: M i with M i = n, where n is the

More information

Chapter 6 Random Number Generation

Chapter 6 Random Number Generation Chapter 6 Random Number Generation Requirements / application Pseudo-random bit generator Hardware and software solutions [NetSec/SysSec], WS 2007/2008 6.1 Requirements and Application Scenarios Security

More information

DESIGNING OF STREAM CIPHER ARCHITECTURE USING THE CELLULAR AUTOMATA

DESIGNING OF STREAM CIPHER ARCHITECTURE USING THE CELLULAR AUTOMATA DESIGNING OF STREAM CIPHER ARCHITECTURE USING THE CELLULAR AUTOMATA 1 Brundha K A MTech Email: 1 brundha1905@gmail.com Abstract Pseudo-random number generators (PRNGs) are a key component of stream ciphers

More information

Network Security. Random Number Generation. Chapter 6. Network Security (WS 2003): 06 Random Number Generation 1 Dr.-Ing G.

Network Security. Random Number Generation. Chapter 6. Network Security (WS 2003): 06 Random Number Generation 1 Dr.-Ing G. Network Security Chapter 6 Random Number Generation Network Security (WS 2003): 06 Random Number Generation 1 Tasks of Key Management (1) Generation: It is crucial to security, that keys are generated

More information

General Security. Physical Unclonable Functions and True Random Number Generator. Digital Storage. Authentication. What We Want to Achieve?

General Security. Physical Unclonable Functions and True Random Number Generator. Digital Storage. Authentication. What We Want to Achieve? General Security Physical Unclonable Functions and True Random Number Generator Mohammad Tehranipoor ECE695: Hardware Security & Trust University of Connecticut ECE Department 2 Digital Storage Authentication

More information

Improved Structure of True Random Number Generator with Direct Amplification of Analog Noise V. Kote 1, 2, V. Molata 1, 2, J.

Improved Structure of True Random Number Generator with Direct Amplification of Analog Noise V. Kote 1, 2, V. Molata 1, 2, J. Ročník 01 Číslo VI Improved Structure of True Random Number Generator with Direct Amplification of Analog Noise V. Kote 1,, V. Molata 1,, J. Jakovenko 1 1 Department of Microelectronics, Faculty of Electrical

More information

CSC 580 Cryptography and Computer Security

CSC 580 Cryptography and Computer Security CSC 580 Cryptography and Computer Security Random Bit Generators (Sections 8.1-8.3) February 20, 2018 Overview Today: HW 4 solution discussion Pseudorandom generation - concepts and simple techniques Reminder:

More information

Design and evaluation of random number generators

Design and evaluation of random number generators Journal of Applied Mathematics & Bioinformatics, vol.5, no.3, 2015, 155-176 ISSN: 1792-6602 (print), 1792-6939 (online) Scienpress Ltd, 2015 Design and evaluation of random number generators George Marinakis

More information

Proposed Pseudorandom Number Generator

Proposed Pseudorandom Number Generator IJSRD National Conference on Technological Advancement and Automatization in Engineering January 2016 ISSN:2321-0613 Mahesh S Naik Research Scholar Shri Jagdishprasad Jhabarmal Tibrewala University, Rajasthan

More information

RESEARCH ARTICLE Software/Hardware Parallel Long Period Random Number Generation Framework Based on the Well Method

RESEARCH ARTICLE Software/Hardware Parallel Long Period Random Number Generation Framework Based on the Well Method International Journal of Advances in Engineering, 2015, 1(3), 84-89 ISSN: 2394-9260 (printed version); ISSN: 2394-9279 (online version); url:http://www.ijae.in RESEARCH ARTICLE Software/Hardware Parallel

More information

Reliable Physical Unclonable Function based on Asynchronous Circuits

Reliable Physical Unclonable Function based on Asynchronous Circuits Reliable Physical Unclonable Function based on Asynchronous Circuits Kyung Ki Kim Department of Electronic Engineering, Daegu University, Gyeongbuk, 38453, South Korea. E-mail: kkkim@daegu.ac.kr Abstract

More information

Analysis, demands, and properties of pseudorandom number generators

Analysis, demands, and properties of pseudorandom number generators Analysis, demands, and properties of pseudorandom number generators Jan Krhovják Department of Computer Systems and Communications Faculty of Informatics, Masaryk University Brno, Czech Republic Jan Krhovják

More information

GENERATION OF PSEUDO-RANDOM NUMBER BY USING WELL AND RESEEDING METHOD. V.Divya Bharathi 1, Arivasanth.M 2

GENERATION OF PSEUDO-RANDOM NUMBER BY USING WELL AND RESEEDING METHOD. V.Divya Bharathi 1, Arivasanth.M 2 GENERATION OF PSEUDO-RANDOM NUMBER BY USING WELL AND RESEEDING METHOD V.Divya Bharathi 1, Arivasanth.M 2 1 PG Scholar, M.E-VLSI Design,Srinivasan Engineering College, Perambalur, TamilNadu, India. 2 Assistant

More information

FPGA BASED RANDOM NUMBER GENERATION ACCESSED THROUGH ARDUINO

FPGA BASED RANDOM NUMBER GENERATION ACCESSED THROUGH ARDUINO FPGA BASED RANDOM NUMBER GENERATION ACCESSED THROUGH ARDUINO V Raghu Ram 1, T Naveen Kumar 2, G Kishore Naidu 3, K Divya Kanti 4 1,2,3,4 ECE Department, Lendi Institute of Engineering and Technology, (India)

More information

- 0 - CryptoLib: Cryptography in Software John B. Lacy 1 Donald P. Mitchell 2 William M. Schell 3 AT&T Bell Laboratories ABSTRACT

- 0 - CryptoLib: Cryptography in Software John B. Lacy 1 Donald P. Mitchell 2 William M. Schell 3 AT&T Bell Laboratories ABSTRACT - 0 - CryptoLib: Cryptography in Software John B. Lacy 1 Donald P. Mitchell 2 William M. Schell 3 AT&T Bell Laboratories ABSTRACT With the capacity of communications channels increasing at the current

More information

IMPLEMENTATION OF PSEUDO-RANDOM SEQUENCE GENERATOR (PRNG) BASED ON SECURE HASH -1 ALGORITHM

IMPLEMENTATION OF PSEUDO-RANDOM SEQUENCE GENERATOR (PRNG) BASED ON SECURE HASH -1 ALGORITHM IMPLEMENTATION OF PSEUDO-RANDOM SEQUENCE GENERATOR (PRNG) BASED ON SECURE HASH -1 ALGORITHM 1 CH.S.RANADHEER, 2 RAMESH JITTY Dept of ECE, TRINITY COLLEGE OF ENGINEERING AND TECHNOLOGY, KARIMNAGAR. Abstract:

More information

Minimum Area Cost for a 30 to 70 Gbits/s AES Processor

Minimum Area Cost for a 30 to 70 Gbits/s AES Processor Minimum Area Cost for a 30 to 70 Gbits/s AE Processor Alireza Hodjat and Ingrid Verbauwhede Electrical Engineering Department University of California, Los Angeles {ahodjat, ingrid} @ ee.ucla.edu Abstract

More information

Parallel Implementation of the NIST Statistical Test Suite

Parallel Implementation of the NIST Statistical Test Suite Parallel Implementation of the NIST Statistical Test Suite Alin Suciu, Iszabela Nagy, Kinga Marton, Ioana Pinca Computer Science Department Technical University of Cluj-Napoca Cluj-Napoca, Romania Alin.Suciu@cs.utcluj.ro,

More information

Hardware Architectures

Hardware Architectures Hardware Architectures Secret-key Cryptography Public-key Cryptography Cryptanalysis AES & AES candidates estream candidates Hash Functions SHA-3 Montgomery Multipliers ECC cryptosystems Pairing-based

More information

TABLE OF CONTENTS CHAPTER NO. TITLE PAGE NO.

TABLE OF CONTENTS CHAPTER NO. TITLE PAGE NO. vii TABLE OF CONTENTS CHAPTER NO. TITLE PAGE NO. ABSTRACT LIST OF TABLES LIST OF FIGURES LIST OF SYMBOLS AND ABBREVIATION iii xii xiv xvii 1 INTRODUCTION 1 1.1 GENERAL 1 1.2 TYPES OF WIRELESS COMMUNICATION

More information

George Landon Chao Shen Chengdong Li

George Landon Chao Shen Chengdong Li George Landon Chao Shen Chengdong Li An Introduction George Landon Anyone who considers arithmetical methods of producing random digits is, of course, in a state of sin. John Von Neumann (1951) Introduction

More information

On-Chip True Random Number Generation in Nanometer Cmos

On-Chip True Random Number Generation in Nanometer Cmos University of Massachusetts Amherst ScholarWorks@UMass Amherst Masters Theses 1911 - February 2014 2012 On-Chip True Random Number Generation in Nanometer Cmos Vikram Belur Suresh University of Massachusetts

More information

Correlated Power Noise Generator as a Low Cost DPA Countermeasures to Secure Hardware AES Cipher

Correlated Power Noise Generator as a Low Cost DPA Countermeasures to Secure Hardware AES Cipher Correlated Power Noise Generator as a Low Cost DPA Countermeasures to Secure Hardware AES Cipher Najeh Kamoun 1, Lilian Bossuet 2, and Adel Ghazel 1 1 CIRTA COM, SUP COM 2 IMS, University of Bordeaux Tunis,

More information

T Cryptography and Data Security

T Cryptography and Data Security T-79.159 Cryptography and Data Security Lecture 10: 10.1 Random number generation 10.2 Key management - Distribution of symmetric keys - Management of public keys Kaufman et al: Ch 11.6; 9.7-9; Stallings:

More information

High Speed True Random Number Generators in Xilinx FPGAs

High Speed True Random Number Generators in Xilinx FPGAs High Speed True Random Number Generators in Xilinx FPGAs Catalin Baetoniu 1 1 Xilinx, Inc., 2100 Logic rive San Jose, CA 95124-3400, USA catalin.baetoniu@xilinx.com Abstract. This paper introduces a method

More information

Recurrent Neural Network Models for improved (Pseudo) Random Number Generation in computer security applications

Recurrent Neural Network Models for improved (Pseudo) Random Number Generation in computer security applications Recurrent Neural Network Models for improved (Pseudo) Random Number Generation in computer security applications D.A. Karras 1 and V. Zorkadis 2 1 University of Piraeus, Dept. of Business Administration,

More information

Acronyms. International Organization for Standardization International Telecommunication Union ITU Telecommunication Standardization Sector

Acronyms. International Organization for Standardization International Telecommunication Union ITU Telecommunication Standardization Sector Acronyms 3DES AES AH ANSI CBC CESG CFB CMAC CRT DoS DEA DES DoS DSA DSS ECB ECC ECDSA ESP FIPS IAB IETF IP IPsec ISO ITU ITU-T Triple DES Advanced Encryption Standard Authentication Header American National

More information

Correlated Power Noise Generator as a Low Cost DPA Countermeasure to Secure Hardware AES Cipher

Correlated Power Noise Generator as a Low Cost DPA Countermeasure to Secure Hardware AES Cipher Author manuscript, published in "Proceeding of the 3rd IEEE International Conference on Signals, Circuits and Systems, SCS 2009, pp. 1-6, Djerba, Tunisa, November 2009., Tunisia (2009)" Correlated Power

More information

Pushing the Limits of SHA-3 Hardware Implementations to Fit on RFID

Pushing the Limits of SHA-3 Hardware Implementations to Fit on RFID Motivation Keccak Our Designs Results Comparison Conclusions 1 / 24 Pushing the Limits of SHA-3 Hardware Implementations to Fit on RFID Peter Pessl and Michael Hutter Motivation Keccak Our Designs Results

More information

Basic principles of pseudo-random number generators

Basic principles of pseudo-random number generators Basic principles of pseudo-random number generators Faculty of Informatics, Masaryk University Outline PRNGs True-randomness and pseudo-randomness Linear feedback shift registers Cryptographically secure

More information

Analysis of Cryptography and Pseudorandom Numbers

Analysis of Cryptography and Pseudorandom Numbers ISSN: 2454-2377 Volume 2, Issue 2, June 2016 Analysis of Cryptography and Pseudorandom Numbers Richa Agarwal Student, M. Tech., Computer Science, Invertis University, Bareilly, India Abstract: With the

More information

A Countermeasure Circuit for Secure AES Engine against Differential Power Analysis

A Countermeasure Circuit for Secure AES Engine against Differential Power Analysis A Countermeasure Circuit for Secure AES Engine against Differential Power Analysis V.S.Subarsana 1, C.K.Gobu 2 PG Scholar, Member IEEE, SNS College of Engineering, Coimbatore, India 1 Assistant Professor

More information

IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY FPGA

IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY FPGA IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY FPGA Implementations of Tiny Mersenne Twister Guoping Wang Department of Engineering, Indiana University Purdue University Fort

More information

Efficient Hardware Design and Implementation of AES Cryptosystem

Efficient Hardware Design and Implementation of AES Cryptosystem Efficient Hardware Design and Implementation of AES Cryptosystem PRAVIN B. GHEWARI 1 MRS. JAYMALA K. PATIL 1 AMIT B. CHOUGULE 2 1 Department of Electronics & Telecommunication 2 Department of Computer

More information

Cryptography and Network Security Chapter 7

Cryptography and Network Security Chapter 7 Cryptography and Network Security Chapter 7 Fifth Edition by William Stallings Lecture slides by Lawrie Brown (with edits by RHB) Chapter 7 Stream Ciphers and Random Number Generation The comparatively

More information

Acronyms. International Organization for Standardization International Telecommunication Union ITU Telecommunication Standardization Sector

Acronyms. International Organization for Standardization International Telecommunication Union ITU Telecommunication Standardization Sector Acronyms 3DES AES AH ANSI CBC CESG CFB CMAC CRT DoS DEA DES DoS DSA DSS ECB ECC ECDSA ESP FIPS IAB IETF IP IPsec ISO ITU ITU-T Triple DES Advanced Encryption Standard Authentication Header American National

More information

SAC: G: 3-D Cellular Automata based PRNG

SAC: G: 3-D Cellular Automata based PRNG SAC: G: 3-D Cellular Automata based PRNG Rosemary Koikara Kungpook National University School of Computer Science and Engineering Daegu, South Korea rosekoikara@gmail.com ABSTRACT Random numbers are critical

More information

DESIGN AND IMPLEMENTATION OF PSEUDO RANDOM NUMBER GENERATOR USED IN AES ALGORITHM

DESIGN AND IMPLEMENTATION OF PSEUDO RANDOM NUMBER GENERATOR USED IN AES ALGORITHM DESIGN AND IMPLEMENTATION OF PSEUDO RANDOM NUMBER GENERATOR USED IN AES ALGORITHM M.SUNITHA (1), P.S.SUREKHA (2) M.TECH Scholor, VLSI Design, Jyothismathi College of Engineering and Technology (1) ASST.Professor,

More information

What is the Q in QRNG?

What is the Q in QRNG? What is the Q in QRNG? V1.2 October 2017 Table of Content 1. What is the Q in QRNG?... 3 2. What is a random number?... 3 3. Generating random numbers... 4 3.1 Types of random number generator... 4 3.2

More information

Cryptographic Implementations In Digital Design

Cryptographic Implementations In Digital Design EECS 151 Spring 2018 Cryptographic Implementations In Digital Design 1 Cryptography and Digital Implementations Cryptography has long been a "typical" application for digital design A large repetitive

More information

Evaluation of ASIC Implementation of Physical Random Number Generators using RS Latches

Evaluation of ASIC Implementation of Physical Random Number Generators using RS Latches Evaluation of ASIC Implementation of Physical Random Number Generators using RS Latches Hirotaka Kokubo, Dai Yamamoto, Masahiko Takenaka, Kouichi Itoh, and Naoya Torii Fujitsu Laboratories Ltd., Secure

More information

Security. Communication security. System Security

Security. Communication security. System Security Security Communication security security of data channel typical assumption: adversary has access to the physical link over which data is transmitted cryptographic separation is necessary System Security

More information

Monte Carlo Integration and Random Numbers

Monte Carlo Integration and Random Numbers Monte Carlo Integration and Random Numbers Higher dimensional integration u Simpson rule with M evaluations in u one dimension the error is order M -4! u d dimensions the error is order M -4/d u In general

More information

ECE 646 Fall 2009 Final Exam December 15, Multiple-choice test

ECE 646 Fall 2009 Final Exam December 15, Multiple-choice test ECE 646 Fall 2009 Final Exam December 15, 2009 Multiple-choice test 1. (1 pt) Parallel processing can be used to speed up the following cryptographic transformations (please note that multiple answers

More information

Novel Approach Design of Elliptic curve Cryptography Implementation in VLSI

Novel Approach Design of Elliptic curve Cryptography Implementation in VLSI Novel Approach Design of Elliptic curve Cryptography Implementation in VLSI V. CHANDRASEKARAN Department of Electronics and Communication Engineering Central Polytechnic College Chennai 113, INDIA N.NAGARAJAN

More information

OPTICAL networks require secure data transmission at

OPTICAL networks require secure data transmission at 366 IEEE TRANSACTIONS ON COMPUTERS, VOL. 55, NO. 4, APRIL 2006 Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors Alireza Hodjat, Student Member, IEEE, and Ingrid Verbauwhede,

More information

PRNGs & DES. Luke Anderson. 16 th March University Of Sydney.

PRNGs & DES. Luke Anderson. 16 th March University Of Sydney. PRNGs & DES Luke Anderson luke@lukeanderson.com.au 16 th March 2018 University Of Sydney Overview 1. Pseudo Random Number Generators 1.1 Sources of Entropy 1.2 Desirable PRNG Properties 1.3 Real PRNGs

More information

Design of an Efficient Architecture for Advanced Encryption Standard Algorithm Using Systolic Structures

Design of an Efficient Architecture for Advanced Encryption Standard Algorithm Using Systolic Structures Design of an Efficient Architecture for Advanced Encryption Standard Algorithm Using Systolic Structures 1 Suresh Sharma, 2 T S B Sudarshan 1 Student, Computer Science & Engineering, IIT, Khragpur 2 Assistant

More information

A Comprehensive Set of Schemes for PUF Response Generation

A Comprehensive Set of Schemes for PUF Response Generation A Comprehensive Set of Schemes for PUF Response Generation Bilal Habib and Kris Gaj Electrical and Computer Engineering Department George Mason University, Fairfax VA, USA {bhabib, kris}@gmu.edu Abstract.

More information

Implementation of Full -Parallelism AES Encryption and Decryption

Implementation of Full -Parallelism AES Encryption and Decryption Implementation of Full -Parallelism AES Encryption and Decryption M.Anto Merline M.E-Commuication Systems, ECE Department K.Ramakrishnan College of Engineering-Samayapuram, Trichy. Abstract-Advanced Encryption

More information

Computer Security: Principles and Practice

Computer Security: Principles and Practice Computer Security: Principles and Practice Chapter 2 Cryptographic Tools First Edition by William Stallings and Lawrie Brown Lecture slides by Lawrie Brown Cryptographic Tools cryptographic algorithms

More information

HOWTO: A Simple Random Number Generator for the ATmega1280 Microcontroller under C and TinyOS

HOWTO: A Simple Random Number Generator for the ATmega1280 Microcontroller under C and TinyOS HOWTO: A Simple Random Number Generator for the ATmega1280 Microcontroller under C and TinyOS Patrik Fimml Martin Perner Bernhard Petschina May 21, 2015 (v2.0) Contents 1 Introduction 1 1.1 True randomness

More information

Advanced WG and MOWG Stream Cipher with Secured Initial vector

Advanced WG and MOWG Stream Cipher with Secured Initial vector International Journal of Scientific and Research Publications, Volume 5, Issue 12, December 2015 471 Advanced WG and MOWG Stream Cipher with Secured Initial vector Dijomol Alias Pursuing M.Tech in VLSI

More information

A Secured Key Generation Scheme Using Enhanced Entropy

A Secured Key Generation Scheme Using Enhanced Entropy 236 A Secured Key Generation Scheme Using Enhanced Entropy M.S. Irfan Ahmed Asst. Professor, VLB Engineering College, Coimbatore E.R. Naganathan Reader, Computer Science Department Alagappa University,

More information

Groestl Tweaks and their Effect on FPGA Results

Groestl Tweaks and their Effect on FPGA Results Groestl Tweaks and their Effect on FPGA Results Marcin Rogawski and Kris Gaj George Mason University {kgaj, mrogawsk}@gmu.edu Abstract. In January 2011, Groestl team published tweaks to their specification

More information

An Efficient Stream Cipher Using Variable Sizes of Key-Streams

An Efficient Stream Cipher Using Variable Sizes of Key-Streams An Efficient Stream Cipher Using Variable Sizes of Key-Streams Hui-Mei Chao, Chin-Ming Hsu Department of Electronic Engineering, Kao Yuan University, #1821 Jhongshan Rd., Lujhu Township, Kao-Hsiung County,

More information

Security against Timing Analysis Attack

Security against Timing Analysis Attack International Journal of Electrical and Computer Engineering (IJECE) Vol. 5, No. 4, August 2015, pp. 759~764 ISSN: 2088-8708 759 Security against Timing Analysis Attack Deevi Radha Rani 1, S. Venkateswarlu

More information

I. INTRODUCTION II. EXISTING SYSTEM

I. INTRODUCTION II. EXISTING SYSTEM Design and Implementation of Pseudo Random Number Generator Used in AES Algorithm N.Madhavi 1, R.Viswanadham 2 M. Tech Student, Department of ECE, Shri Vishnu Engg College for women Asst. Professor, Department

More information

New Approach for Modifying Blowfish Algorithm by Using Multiple Keys

New Approach for Modifying Blowfish Algorithm by Using Multiple Keys IJCSNS International Journal of Computer Science and Network Security, VOL. No.3, March 20 2 New Approach for Modifying Blowfish Algorithm by Using Multiple Keys Afaf M. Ali Al-Neaimi, Rehab F. Hassan

More information

Survey of Commercially available chips and IP cores implementing cryptographic algorithms

Survey of Commercially available chips and IP cores implementing cryptographic algorithms Survey of Commercially available chips and IP cores implementing cryptographic algorithms Prepared by - Micheal Dugan, Prajakta Gogte, Prerna Arora Prepared for - ECE 646, Prof. Kris Gaj December 19, 2005

More information

COZMO - A New Lightweight Stream Cipher

COZMO - A New Lightweight Stream Cipher COZMO - A New Lightweight Stream Cipher Rhea Bonnerji 0000-0002-5825-8800, Simanta Sarkar 0000-0002-4210-2764, Krishnendu Rarhi 0000-0002-5794-215X, Abhishek Bhattacharya School of Information Technology,

More information

FAULT DETECTION IN THE ADVANCED ENCRYPTION STANDARD. G. Bertoni, L. Breveglieri, I. Koren and V. Piuri

FAULT DETECTION IN THE ADVANCED ENCRYPTION STANDARD. G. Bertoni, L. Breveglieri, I. Koren and V. Piuri FAULT DETECTION IN THE ADVANCED ENCRYPTION STANDARD G. Bertoni, L. Breveglieri, I. Koren and V. Piuri Abstract. The AES (Advanced Encryption Standard) is an emerging private-key cryptographic system. Performance

More information

A systematic approach to eliminating the vulnerabilities in smart cards evaluation

A systematic approach to eliminating the vulnerabilities in smart cards evaluation A systematic approach to eliminating the vulnerabilities in smart cards evaluation Hongsong Shi, Jinping Gao, Chongbing Zhang hongsongshi@gmail.com China Information Technology Security Evaluation Center

More information

Random and Pseudorandom Bit Generators

Random and Pseudorandom Bit Generators Random and Pseudorandom Bit Generators Random bit generators Pseudorandom bit generators Cryptographically Secure PRBG Statistical tests Unpredictable quantities The security of many cryptographic systems

More information

FPGA Implementation of High Speed AES Algorithm for Improving The System Computing Speed

FPGA Implementation of High Speed AES Algorithm for Improving The System Computing Speed FPGA Implementation of High Speed AES Algorithm for Improving The System Computing Speed Vijaya Kumar. B.1 #1, T. Thammi Reddy.2 #2 #1. Dept of Electronics and Communication, G.P.R.Engineering College,

More information

MM23SC8128RM Flash Security Turbo Microcontroller Smart Card Chip With 1024 bit RSA & Maths Co-processor

MM23SC8128RM Flash Security Turbo Microcontroller Smart Card Chip With 1024 bit RSA & Maths Co-processor Flash Security Turbo Microcontroller Smart Card Chip With 1024 bit RSA & Maths Co-processor 08 September 2009 This document is property of My-MS and My-MS has the right to make any changes to the contents

More information

FPGA Implementation of WG Stream Cipher

FPGA Implementation of WG Stream Cipher FPGA Implementation of WG Stream Cipher Anna Johnson Assistant Professor,ECE Department, Jyothi Engineering College,Thrissur Abstract Cryptography is the technique of providing security to a network. The

More information

Pseudo-random Bit Generation Algorithm Based on Chebyshev Polynomial and Tinkerbell Map

Pseudo-random Bit Generation Algorithm Based on Chebyshev Polynomial and Tinkerbell Map Applied Mathematical Sciences, Vol. 8, 2014, no. 125, 6205-6210 HIKARI Ltd, www.m-hikari.com http://dx.doi.org/10.12988/ams.2014.48676 Pseudo-random Bit Generation Algorithm Based on Chebyshev Polynomial

More information

Cryptography. Dr. Michael Schneider Chapter 10: Pseudorandom Bit Generators and Stream Ciphers

Cryptography. Dr. Michael Schneider Chapter 10: Pseudorandom Bit Generators and Stream Ciphers Cryptography Dr. Michael Schneider michael.schneider@h-da.de Chapter 10: Pseudorandom Bit Generators and Stream Ciphers December 12, 2017 h_da WS2017/18 Dr. Michael Schneider 1 1 Random and Pseudorandom

More information

Information Security CS526

Information Security CS526 Information Security CS 526 Topic 3 Cryptography: One-time Pad, Information Theoretic Security, and Stream CIphers 1 Announcements HW1 is out, due on Sept 11 Start early, late policy is 3 total late days

More information

On Optimized FPGA Implementations of the SHA-3 Candidate Grøstl

On Optimized FPGA Implementations of the SHA-3 Candidate Grøstl On Optimized FPGA Implementations of the SHA-3 Candidate Grøstl Bernhard Jungk, Steffen Reith, and Jürgen Apfelbeck Fachhochschule Wiesbaden University of Applied Sciences {jungk reith}@informatik.fh-wiesbaden.de

More information

By Charvi Dhoot*, Vincent J. Mooney &,

By Charvi Dhoot*, Vincent J. Mooney &, By Charvi Dhoot*, Vincent J. Mooney &, -Shubhajit Roy Chowdhury*, Lap Pui Chau # *International Institute of Information Technology, Hyderabad, India & School of Electrical and Computer Engineering, Georgia

More information

Low-Overhead Implementation of a Soft Decision Helper Data Algorithm for SRAM PUFs

Low-Overhead Implementation of a Soft Decision Helper Data Algorithm for SRAM PUFs Low-Overhead Implementation of a Soft Decision Helper Data Algorithm for SRAM PUFs Roel Maes 1, Pim Tuyls 1,2, Ingrid Verbauwhede 1 1. COSIC, K.U.Leuven and IBBT 2. Intrinsic-ID, Eindhoven Workshop on

More information

SEE Tolerant Self-Calibrating Simple Fractional-N PLL

SEE Tolerant Self-Calibrating Simple Fractional-N PLL SEE Tolerant Self-Calibrating Simple Fractional-N PLL Robert L. Shuler, Avionic Systems Division, NASA Johnson Space Center, Houston, TX 77058 Li Chen, Department of Electrical Engineering, University

More information

Efficient FPGA Implementations of PRINT CIPHER

Efficient FPGA Implementations of PRINT CIPHER Efficient FPGA Implementations of PRINT CIPHER 1 Tadashi Okabe Information Technology Group Tokyo Metropolitan Industrial Technology Research Institute, Tokyo, Japan Abstract This article presents field

More information

Comparative Analysis of SLA-LFSR with Traditional Pseudo Random Number Generators

Comparative Analysis of SLA-LFSR with Traditional Pseudo Random Number Generators International Journal of Computational Intelligence Research ISSN 0973-1873 Volume 13, Number 6 (2017), pp. 1461-1470 Research India Publications http://www.ripublication.com Comparative Analysis of SLA-LFSR

More information

A Case Against Currently Used Hash Functions in RFID Protocols

A Case Against Currently Used Hash Functions in RFID Protocols A Case Against Currently Used Hash Functions in RFID Protocols Martin Feldhofer and Christian Rechberger Graz University of Technology Institute for Applied Information Processing and Communications Inffeldgasse

More information

THE FINITE LAB-TRANSFORM (FLT) Peter Lablans

THE FINITE LAB-TRANSFORM (FLT) Peter Lablans THE FINITE LAB-TRANSFORM (FLT) Peter Lablans Warning: The subject matter of this article is, at least partially, protected by Copyright Registration and by issued patents and pending patent applications.

More information

On-Line Self-Test of AES Hardware Implementations

On-Line Self-Test of AES Hardware Implementations On-Line Self-Test of AES Hardware Implementations G. Di Natale, M. L. Flottes, B. Rouzeyre Laboratoire d Informatique, de Robotique et de Microélectronique de Montpellier Université Montpellier II / CNRS

More information

Increasing randomness using DCM-based tunable True Random Number Generator

Increasing randomness using DCM-based tunable True Random Number Generator Increasing randomness using DCM-based tunable True Random Number Generator J.Shouba Tharani 1, Dr.V.Seethalakshmi 2 PG Scholar, Dept of VLSI Design, KPR Institute of Engineering and Technology, Coimbatore,

More information

On Boolean and Arithmetic Masking against Differential Power Analysis

On Boolean and Arithmetic Masking against Differential Power Analysis On Boolean and Arithmetic Masking against Differential Power Analysis [Published in Ç.K. Koç and C. Paar, Eds., Cryptographic Hardware and Embedded Systems CHES 2000, vol. 1965 of Lecture Notes in Computer

More information

Outline. Trusted Design in FPGAs. FPGA Architectures CLB CLB. CLB Wiring

Outline. Trusted Design in FPGAs. FPGA Architectures CLB CLB. CLB Wiring Outline Trusted Design in FPGAs Mohammad Tehranipoor ECE6095: Hardware Security & Trust University of Connecticut ECE Department Intro to FPGA Architecture FPGA Overview Manufacturing Flow FPGA Security

More information

Dolphin DCI 1.2. FIPS Level 3 Validation. Non-Proprietary Security Policy. Version 1.0. DOL.TD DRM Page 1 Version 1.0 Doremi Cinema LLC

Dolphin DCI 1.2. FIPS Level 3 Validation. Non-Proprietary Security Policy. Version 1.0. DOL.TD DRM Page 1 Version 1.0 Doremi Cinema LLC Dolphin DCI 1.2 FIPS 140-2 Level 3 Validation Non-Proprietary Security Policy Version 1.0 DOL.TD.000921.DRM Page 1 Version 1.0 Table of Contents 1 Introduction... 3 1.1 PURPOSE... 3 1.2 REFERENCES... 3

More information

Light Weight Cellular Automata Computations and Symmetric Key for Achieving Efficient Cryptography

Light Weight Cellular Automata Computations and Symmetric Key for Achieving Efficient Cryptography International Journal of Emerging Engineering Research and Technology Volume 3, Issue 12, December 2015, PP 84-91 ISSN 2349-4395 (Print) & ISSN 2349-4409 (Online) Light Weight Cellular Automata Computations

More information

Public Key Encryption. Modified by: Dr. Ramzi Saifan

Public Key Encryption. Modified by: Dr. Ramzi Saifan Public Key Encryption Modified by: Dr. Ramzi Saifan Prime Numbers Prime numbers only have divisors of 1 and itself They cannot be written as a product of other numbers Prime numbers are central to number

More information

FPGA Implementation of A Cryptography Technology Using Pseudo Random Number Generator

FPGA Implementation of A Cryptography Technology Using Pseudo Random Number Generator FPGA Implementation of A Cryptography Technology Using Pseudo Random Number Generator Hariprasad 1 NagaDeepa. Ch. 2 1 (M.Tech, Department of Electronics and Communication Engineering,VNR-VJIET, Hyderabad,

More information

A SIMPLE 1-BYTE 1-CLOCK RC4 DESIGN AND ITS EFFICIENT IMPLEMENTATION IN FPGA COPROCESSOR FOR SECURED ETHERNET COMMUNICATION

A SIMPLE 1-BYTE 1-CLOCK RC4 DESIGN AND ITS EFFICIENT IMPLEMENTATION IN FPGA COPROCESSOR FOR SECURED ETHERNET COMMUNICATION A SIMPLE 1-BYTE 1-CLOCK RC4 DESIGN AND ITS EFFICIENT IMPLEMENTATION IN FPGA COPROCESSOR FOR SECURED ETHERNET COMMUNICATION Abstract In the field of cryptography till date the 1-byte in 1-clock is the best

More information

SIDE CHANNEL ATTACKS AGAINST IOS CRYPTO LIBRARIES AND MORE DR. NAJWA AARAJ HACK IN THE BOX 13 APRIL 2017

SIDE CHANNEL ATTACKS AGAINST IOS CRYPTO LIBRARIES AND MORE DR. NAJWA AARAJ HACK IN THE BOX 13 APRIL 2017 SIDE CHANNEL ATTACKS AGAINST IOS CRYPTO LIBRARIES AND MORE DR. NAJWA AARAJ HACK IN THE BOX 13 APRIL 2017 WHAT WE DO What we do Robust and Efficient Cryptographic Protocols Research in Cryptography and

More information

CRYPTOGRAPHY AND NETWORK SECURITY

CRYPTOGRAPHY AND NETWORK SECURITY CRYPTOGRAPHY AND NETWORK SECURITY PRINCIPLES AND PRACTICE FIFTH EDITION William Stallings Prentice Hall Boston Columbus Indianapolis New York San Francisco Upper Saddle River Amsterdam Cape Town Dubai

More information

Power Analysis of MAC-Keccak: A Side Channel Attack. Advanced Cryptography Kyle McGlynn 4/12/18

Power Analysis of MAC-Keccak: A Side Channel Attack. Advanced Cryptography Kyle McGlynn 4/12/18 Power Analysis of MAC-Keccak: A Side Channel Attack Advanced Cryptography Kyle McGlynn 4/12/18 Contents Side-Channel Attack Power Analysis Simple Power Analysis (SPA) Differential Power Analysis (DPA)

More information

Bus Matrix Synthesis Based On Steiner Graphs for Power Efficient System on Chip Communications

Bus Matrix Synthesis Based On Steiner Graphs for Power Efficient System on Chip Communications Bus Matrix Synthesis Based On Steiner Graphs for Power Efficient System on Chip Communications M.Jasmin Assistant Professor, Department Of ECE, Bharath University, Chennai,India ABSTRACT: Power consumption

More information

INTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY

INTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY INTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY A PATH FOR HORIZING YOUR INNOVATIVE WORK MORE RANDOMNESS OF IMPROVED RC4 (IRC4) THAN ORIGINAL RC4 HEMANTA DEY 1, DR. UTTAM

More information

ECE 297:11 Reconfigurable Architectures for Computer Security

ECE 297:11 Reconfigurable Architectures for Computer Security ECE 297:11 Reconfigurable Architectures for Computer Security Course web page: http://mason.gmu.edu/~kgaj/ece297 Instructors: Kris Gaj (GMU) Tarek El-Ghazawi (GWU) TA: Pawel Chodowiec (GMU) Kris Gaj George

More information