Basic Sample and Hold Element. Prof. Paul Hasler Georgia Institute of Technology

Transcription

1 Basic Sample and Hold Element Prof. Paul Hasler Georgia Institute of Technology

2 Sample and Hold Elements

3 Sample and Hold Elements Amplitude (Hold) (Sample) (Hold) Time

4 Sample and Hold Elements Amplitude (Hold) (Sample) (Hold) Time

5 Sample and Hold Elements Amplitude (Hold) (Sample) (Hold) Valid Time

6 Sample and Hold Elements Amplitude (Hold) (Sample) (Hold) Settling time (t s ) = time required to settle to the final held voltage to within an accuracy tolerance Valid t s Time

7 Sample and Hold Elements Amplitude Acquisition time (t a ) = time required to acquire the analog voltage (Hold) (Sample) (Hold) t a Valid t s Time

8 Sample and Hold Elements Amplitude T sample = t a + t s F sample (max) < 1/ T sample (Hold) (Sample) (Hold) t a Valid t s Time

9 Sample and Hold Elements Amplitude (Hold) (Sample) (Hold) Aperture time = the time required for the sampling switch to open after the S/H command is initiated Aperture jitter = variation in the aperture time due to clock variations and noise t a Valid t s Time

10 Basic Sample and Hold Element

11 Basic Sample and Hold Element

12 Basic Sample and Hold Element = 1 (Vdd) 1

13 Basic Sample and Hold Element = 1 (Vdd) 1 1

14 Basic Sample and Hold Element = 1 (Vdd) 1 1 = 0 (Vdd) 0

15 Basic Sample and Hold Element = 1 (Vdd) 1 1 = 0 (Vdd) 0 0

16 Acquisition and Hold Time Acquisition Time Hold Time 0V R on but R on is not a constant. 10pF 1pF 100fF 10fF I 1 I 2 I 2 : Leakage through the reversed-biased pn junction Typically 1fA to 100fA (dark) I 1 : Leakage through the MOS transistor Can be negligable with correct biasing Hold time (1mV drop) with I 1 = 10fA 1s 100ms 10ms 1ms

17 Basic S/H elements

18 Basic S/H elements

19 Basic S/H elements [n] Would use a buffer to drive loads that are not purely capacitive

20 S/H elements φ 1 More accurate, but slower φ 2 φ 1 [n] φ 1 and φ 2 are non-overlapping clocks

21 Non-Overlapping s We will always be using non-overlapping clocks; therefore, we want a waveform like φ 1 We effectively have four phases. φ 2 t d (1) (2) (3) (4) [n] cycle t

22 Non-Overlapping s We will always be using non-overlapping clocks; therefore, we want a waveform like φ 1 We effectively have four phases. φ 2 t d (1) (2) (3) (4) [n] cycle t Would want t d as small as possible for proper operation We will also assume that the input is held constant through the entire [n] th cycle

23 Non-Overlapping s We will always be using non-overlapping clocks; therefore, we want a waveform like φ 1 We effectively have four phases. φ 2 t d (1) (2) (3) (4) [n] cycle Would want t d as small as possible for proper operation We will also assume that the input is held constant through the entire [n] th cycle t Circuit to generate waveform N-stages of delay (sets t d ) in φ 1 φ 2

24 S/H elements Initial Phase (φ 1, φ 2 = 0) [n-1]

25 S/H elements Phase I (φ 1 = 1, φ 2 = 0) φ 1 ~

26 S/H elements Phase II (φ 1, φ 2 = 0) [n]

27 S/H elements φ 2 [n] are ~ ; therefore ready for the next phase

28 S/H elements φ 1 φ 2 φ 1 [n] φ 1 and φ 2 are non-overlapping clocks

29 S/H elements Basic S/H concepts Basic MOS switch issues Basic MOS S/H elements An additional S/H element