Modular Multilevel Converter Solution in RT-LAB

Transcription

1 Modular Multilevel Converter Solution in RT-LAB Wei Li, Esmaeil Ghahremani OPAL-RT Sebastien Dennetiere RTE 1

2 Chinese MMC Project and emegasim Simulator Installation MMC Project XJ Group CEPRI SPERI Nari emegasim Installed at MMC Manufacturer Zhejiang Grid CSG 2

3 Contents What is Modular Multilevel Converter (MMC) MMC Advantages and Challenges OPAL-RT solutions for MMC System Verification Applications Demo: modeling MOV in MMC system Conclusions August 19, 2014 OPAL-RT 3 3

4 MMC Sub-module (SM) What is MMC: Modular Multilevel Converter Sub-module (SM) are two-terminal devices MMC Half-bridge (HB): with 2-IGBT in each SM SM output is either capacitor voltage or zero at active mode The 7th International Conference MMC Full-bridge (FB): with 4 IGBTs in each SM SM output is either positive or negative of capacitor voltage or zero at active mode A + I SM T V cap T 3 B V ab - T 2 T 4 MMC-1P MMC-2P 4

5 MMC Topology description MMC-HB ac-dc converter I up-a + SM 1 V sm1 SM V smup-a SM 2 V sm2 SM I up-b I up-c SM 1 SM 2 I dc+ V dc+ - V up-a SM k + - V smk V up-b SM k V up-c SM k V t-a I a V low-a L s L s V t-a I a V low-b L s L s V t-a I a V low-c L s L s Sub-module (SM) SM 1 SM 1 SM 1 SM 2 SM 2 SM 2 SM k SM k SM k I low-a I low-b I low-c I dc- V dc- 5

6 MMC Topology description MMC-FB STATCOM V t-a L s V t-a V t-a I a I b I c L s L s Sub-module (SM) SM 1 SM 2 SM 1 SM 2 SM 1 SM 2 SM k SM k SM k V n 6

7 MMC 1P working principle Sum of all SM capacitor voltage in 1 arm equals two times the dc link voltage At any given time, only half SM output their capacitor voltage. 7

8 MMC Characteristics Arm currents are continuous Commutating inductors are in arms Capacitors in each cell (energy storage in MMC) SM capacitor voltage has to be balanced (on a larger time scale) DC-link voltage is controlled by switch states (fast) 8

9 MMC Advantages Low PWM frequency reduced switch losses Low ac harmonic content no need for a filter Continuous currents in MMC arm and DC link - dc link capacitor omitted Fast recovery from AC/DC-bus short-circuit Reliability - system can remain operating for a certain period even when a few SM are out of order 9

10 Challenges More complex controller and protection(design and validation) More challenge for Simulation large number of components large number of and I/Os Non-linear elements, e.g. MOV 10

11 OPAL-RT Solution for MMC Simulation MMC HB and FB models MMC application in HVDC or STATCOM MMC solutions for real time or fast simulation. MMC HIL and RCP (rapid control prototyping) Hardware IOs Copper wiring or optical fibers MMC example controller In RT-LAB or Hypersim platform MMC solution in CPU and FPGA 11

12 CPU models Supporting MMC-HB and MMC-FB Unlimited number of SM per valve Taking several CPU cores to calculate the models 1 CPU can solve 300 cell at a time step of 25 us Providing Vcell-cap debugging mode to help user developing their controller 12

13 FPGA models Support MMC-HB (will support MMC-FB in 2014 Q3) For 1 FPGA VIRTEX 6 (OP7000 system) up to 250 SM/valve * 6 valve, or 500 SM/vlve*2valve. VIRTEX 7 FPGA (OP7020 system) up to 500 SM/valve * 6 valve + protocol drive + SFP *16 Kintex-7 FPGA (OP4500 system) up to 250 SM/valve * 6 valve + protocol drive + SFP *4 Support multiple FPGAs. 13

14 FPGA models (continued) No CPU resources to calculate the models, MMC block calculates at a time step of 250 ns or 500 ns Pulse modulation and capacitor voltage balancing control (VBC) embedded in FPGA Providing Vcell-cap debugging mode to help user developing their controller Supporting both RT-LAB and Hypersim Platform 14

15 Interface between external controller & MMC models Analog output for Vcap and digital input for gating pulses SFP optical fiber with Aurora protocol SFP optical fiber with Gigabit Ethernet protocol 15

16 Simulating MMC in CPU model Target MMC pole control MMC valve control Voltage balancing control + gating signal generation Grid MMC Other MMC and Grid etc. CPU 1 CPU 2 CPU 3 CPU 4 16

17 HIL Simulating MMC in CPU model Grid MMC CPU 1 Other MMC and Grid etc. CPU 2 Target IO Actual MMC pole controller Actual MMC valve controller 17

18 Selector k3 Selector k1 The 7th International Conference MMC FPGA model in OP7020 Target Reference from CPU Gating Signals from CPU MMC & system Measurements MMC valve control Voltage balancing control + gating signal generation Gating signals by valve control Gating Signals to MMC MMC Selector k2 Capacitor voltage FPGA Gating signals to protocol Gating signals from protocol Capacitor Voltage from Protocol Protocol drive (or IO drive) SPF or IO 18

19 Selector k3 Selector k1 The 7th International Conference Simulating MMC in FPGA (valve control in CPU) Target Valve control Pole control Grid Reference from CPU Gating Signals from CPU MMC & system Measurements MMC valve control Voltage balancing control + gating signal generation Gating signals by valve control Gating Signals to MMC MMC Selector k2 Capacitor voltage FPGA Gating signals to protocol Gating signals from protocol Capacitor Voltage from Protocol Protocol drive (or IO drive) SPF or IO 19

20 Selector k3 Selector k1 The 7th International Conference Simulating MMC in FPGA (valve control in same FPGA) Target Pole control Grid Reference from CPU Gating Signals from CPU MMC & system Measurements MMC valve control Voltage balancing control + gating signal generation Gating signals by valve control Gating Signals to MMC MMC Selector k2 Capacitor voltage FPGA Gating signals to protocol Gating signals from protocol Capacitor Voltage from Protocol Protocol drive (or IO drive) SPF or IO 20

21 Selector k3 Selector k3 Selector k1 Selector k1 The 7th International Conference HIL Applications of MMC in FPGA CPU based Target 1 Pole ctrl I/O Copper wiring System measurements I/O CPU based Target 2 Grid Reference from CPU valve control Gating Signals from CPU Gating signals by valve control Gating Signals to MMC MMC MMC Sys. Meas. Reference from CPU MMC valve control Gating Signals from CPU Gating signals by valve control Gating Signals to MMC MMC MMC System. Measurements. Selector k2 Capacitor voltage Selector k2 Capacitor voltage FPGA 1 Gating signals to protocol Gating signals from protocol Capacitor Voltage from Protocol FPGA 2 Gating signals to protocol Gating signals from protocol Capacitor Voltage from Protocol Protocol drive Protocol drive SPF SPF Fiber optic Fiber optic MMC measurements & commands 21

22 Selector k3 Selector k1 The 7th International Conference HIL Testing of Actual MMC Controller Copper wiring System measurements I/O CPU based Target Grid Actual MMC controller Reference from CPU MMC valve control Gating Signals from CPU Gating signals by valve control Gating Signals to MMC MMC MMC System. Measurements. Selector k2 Capacitor voltage FPGA Gating signals to protocol Gating signals from protocol Capacitor Voltage from Protocol Protocol drive SPF MMC measurements & commands Fiber optic 22

23 Selector k3 Selector k1 The 7th International Conference RCP of MMC Controller in FPGA CPU based Target Pole ctrl I/O Copper wiring System measurements Reference from CPU valve control Gating Signals from CPU Gating signals by valve control Gating Signals to MMC MMC MMC Sys. Meas. Downgraded MMC system Selector k2 Capacitor voltage FPGA Gating signals to protocol Gating signals from protocol Capacitor Voltage from Protocol Protocol drive SPF MMC measurements & commands Fiber optic 23

24 MMC Customer customer site delivery time ABB Switzerland 2012 MMC model / Hardware MMC FPGA model, MMC controller/op7000 cell number /Terminals 8*6 2 terminals IO/protocol projects 48 AO, 96 DI hardware-in-the-loop test controller Alstom UK 2012 MMC cpu model /OP *6 2 terminals no fast simulation China South Grid (CSG) China 2013 MMC FPGA model/op *6 3 terminals Aurora simulation a real 3-terminal MMC HVDC project and validation its controller China Electric Power Research Institute (CEPRI) China 2013 MMC FPGA model/op *6 2 terminals no simulation of a 3-terminal MMC HVDC project Nari-Relays (NR) phase 1 China 2011 MMC CPU and fpga model/op5600+ml605 50*6 2 terminals 48*6 AO, 96*6 DI hardware-in-the-loop test Nari-Relays (NR) phase 2 China 2013 MMC fpga model/op *6 5 terminals Aurora/Gigabit simulation of a 5-terminal MMC HVDC project XJ Group phase 1 China 2013 MMC controller/op terminals IO Rapid Control Prototyping (RCP) State Power Economic Research Institute (SPERI) China 2013 MMC controller/op terminals 24

25 Naoao 3-terminal MMC project (1 st multiterminal in the world) Parameters Sucheng Jinniu Qingao station station station Transfomre connection Yn/D11 Yn/D11 Yn/D11 Rated power (MVA) Primary voltage (kv) Secondary voltage (kv) Primary impedance (pu) [R1,L1] [ ] [ ] [ ] Secondary impedance (pu) [R2,L2] [ ] [ ] [ ] Grounding resistance (kω) MMC capacity(mva) Number of SMs in an arm Number of redandant SMs Rated SM voltage(kv)

26 Naoao MMC Full HIL Configuration and Performance Time 28 us Step CPU # 6 (3 for 3 MMC 1 for ac grid 1 for wind farm 1 for data acquisition and logging) FPGA # 3 Virtex-6 IO 32*3 AO 32*3 DI 32*3 DO 26

27 Demo: Testing MOV in MMC 27

28 MMC Model with Arrester (MOV) Top Level August 19, 2014 OPAL-RT 28 28

29 MMC Model with Arrester (MOV) - Subsystem August 19, 2014 OPAL-RT 29 29

30 The Arrester Connected to DC-Pole August 19, 2014 OPAL-RT 30 30

31 Arrester Modelling with Non-Linear Shunt Resistor The nonlinear characteristics is composed for more than 20 segments (up to 30). August 19, 2014 OPAL-RT 31 31

32 MMC Model HIL Configuration August 19, 2014 OPAL-RT 32 32

33 Simulation Preferences Enable or Disable Iterations August 19, 2014 OPAL-RT 33 33

34 Simulation Results No Iterations Compare with EMTP August 19, 2014 OPAL-RT 34 34

35 Simulation Results No Iterations Compare with EMTP August 19, 2014 OPAL-RT 35 35

36 Simulation Results Enable Iterations August 19, 2014 OPAL-RT 36 36

37 Simulation Results Enable Iterations Compare with EMTP August 19, 2014 OPAL-RT 37 37

38 Simulation Results Enable Iterations Compare with EMTP August 19, 2014 OPAL-RT 38 38

39 Real-Time Performance of MMC HIL Configurations Time 25 us Step CPU # 3 System Target IO 32*2 = 64 AO 13*2 = 26 AIN 12*2 = 24 DIN 39

40 Summaries Challenges Small time step for SM Large number of SM Connection to controller with fast rate and small latency Accuracy on non-linear elements, e.g. MOV Tested reliability OPAL-RT Solutions Minimum MMC time step Maximum number of SM per FPGA Support Multi- FPGA Connection to controller Accuracy on nonlinear element OPAL-RT solutions others 250 ns >2.5 us 3000 SM 1500 yes Aurora, Gigabit Ethernet yes yes Aurora no 40

41 Thanks 41