NHD UCY3. OLED Display Module

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NHD 2.7 2864UCY3 OLED Display Module NHD Newhaven Display 2.7 2.7 diagonal size 2864 28 x 64 pixel resolution UC Model Y Emitting Color: Yellow 3 +3V power supply Newhaven Display International, Inc.

1 NHD UCY3 OLED Display Module NHD Newhaven Display diagonal size x 64 pixel resolution UC Model Y Emitting Color: Yellow 3 +3V power supply Newhaven Display International, Inc. 25 Technology Drive, Suite Elgin IL, 624 Ph: Fax: nhtech@newhavendisplay.com nhsales@newhavendisplay.com []

2 Document Revision History Revision Date Description Changed by 5//2 Initial Product Release Functions and Features 28 x 64 pixel resolution Built in SSD325 controller Parallel or serial MPU interface Single, low voltage power supply RoHS compliant [2]

3 Mechanical Drawing NHD UCY3 [3]

4 Interface Description Parallel Interface: Pin No. Symbol External Function Description Connection VSS Power Supply Ground 2 VDD Power Supply Supply Voltage for OLED and logic. 3 NC No Connect 4 D/C MPU Register select signal. D/C=: Command, D/C=: Data 5 R/W or /WR MPU 68 interface: Read/Write select signal, R/W=: Read R/W: =: Write 88 interface: Active LOW Write signal. 6 E or /RD MPU 68 interface: Operation enable signal. Falling edge triggered. 88 interface: Active LOW Read signal. 7 4 DB DB7 MPU 8 bit Bi directional data bus lines. 5 NC No Connect 6 /RES MPU Active LOW Reset signal. 7 /CS MPU Active LOW Chip Select signal. 8 NC No Connect 9 BS2 MPU MPU Interface Select signal. 2 BS MPU MPU Interface Select signal. Serial Interface: Pin No. Symbol External Function Description Connection VSS Power Supply Ground 2 VDD Power Supply Supply Voltage for OLED and logic. 3 NC No Connect 4 D/C MPU Register select signal. D/C=: Command, D/C=: Data 5 6 VSS Power Supply Ground 7 SCLK MPU Serial Clock signal. 8 SDIN MPU Serial Data Input signal. 9 NC No Connect 4 VSS Power Supply Ground 5 NC No Connect 6 /RES MPU Active LOW Reset signal. 7 /CS MPU Active LOW Chip Select signal. 8 NC No Connect 9 BS2 MPU MPU Interface Select signal. 2 BS MPU MPU Interface Select signal. MPU Interface Pin Selections Pin Name 68 Parallel 8 bit interface 88 Parallel 8 bit interface Serial Interface BS2 BS [4]

5 MPU Interface Pin Assignment Summery Bus Data/Command Interface Interface D7 D6 D5 D4 D3 D2 D 8 bit 68 8 bit 88 SPI Tie LOW D[7:] D[7:] NC SDIN D SCLK Control Signals E E /RD R/W R/W /WR /CS /CS /CS D/C D/C D/C Tie LOW /CS D/C /RES /RES /RES /RES Wiring Diagrams [5]

6 Electrical Characteristics Item Symbol Condition Min. Typ. Max. Unit Operating Temperature Range Top Absolute Max ⁰C Storage Temperature Range Tst Absolute Max 4 +9 ⁰C Supply Voltage VDD V Supply Current (logic) IDD Ta=25 C, VDD=2.8V 25 4 µa Supply Current (display) ICC VDD=2.8V, 5% ON 3 39 ma VDD=2.8V, % ON ma Sleep Mode Current IDD+ICC SLEEP 2 µa H Level input Vih.8VDD VDD V L Level input Vil VSS.2VDD V H Level output Voh.9VDD VDD V L Level output Vol VSS.VDD V Optical Characteristics Item Symbol Condition Min. Typ. Max. Unit Viewing Angle Vertical (top) AV 8 ⁰ Viewing Angle Vertical (bottom) AV 8 ⁰ Viewing Angle Horizontal (left) AH 8 ⁰ Viewing Angle Horizontal (right) AH 8 ⁰ Contrast Ratio Cr 2: Response Time (rise) Tr us Response Time (fall) Tf us Brightness 5% checkerboard 7 cd/m 2 Lifetime Ta=25 C, 5% 4, Hrs checkerboard Note: Lifetime at typical temperature is based on accelerated high temperature operation. Lifetime is tested at average 5% pixels on and is rated as Hours until Half Brightness. The Display OFF command can be used to extend the lifetime of the display. Luminance of active pixels will degrade faster than inactive pixels. Residual (burn in) images may occur. To avoid this, every pixel should be illuminated uniformly. [6]

7 Built in SSD325 controller Instruction Table Instruction Set Column Address Set Row Address Set Contrast Control Code D/C HEX DB7 DB6 DB5 DB4 DB3 DB2 DB DB 5 A[5:] A A B[5:] B5 B4 B3 B2 B B 75 A[6:] B[6:] 8 A[6:] B6 B5 B4 B3 B2 A B A [7] A B A Description Set column start and end address A[5:]: Column start address. Range: 63d B[5:]: Column end address. Range: 63d Set row start and end address A[6:]: Row start address. Range: 79d B[6:]: Row end address. Range: 79d Set Current Range 84~86 X X x84 = Quarter Current Range x85 = Half Current Range x86 = Full Current Range Set Remap A A[6:] A A Double byte command to select out of 28 contrast steps. Contrast increases as the value increases. RESET value A[] = ; Disable Column Address remap A[] = ; Enable Column Address remap A[] = ; Disable Nibble remap A[] = ; Enable Nibble remap A[2] = ; Horizontal Address Increment A[2] = ; Vertical Address Increment A[4] = ; Disable COM remap A[4] = ; Enable COM A[6] = ; Disable COM split Odd/Even A[6] = ; Enable COM split Odd/Even Set display RAM display start line register from 79. Set Display Start Line A A[6:] A A Set Display Offset A[6:] A A Display Mode /A7 X2 X X x = Normal display x = Entire display ON, all pixels Grayscale level 5 x = Entire display OFF xa7 = Inverse display Set Multiplex Ratio Master configuration A8 A[6:] AD A[:] A A A A Set vertical shift by COM from ~79. Set MUX ratio to N+ MUX N=A[6:]; from 6MUX to 8MUX ( to 4 are invalid) A[] = ; Disable DC DC converter A[] = ; Enable DC DC converter A[] = ; Disable internal VCOMH A[] = ; Enable internal VCOMH 63d 79d x4 x84 x 8

8 Set Display ON/ OFF Set VCOMH Voltage Set Precharge Voltage AE~AF X3 xae = Display OFF (sleep mode) xaf = Display ON Set Phase Length Set Row Period Set Display Clock Divide Ratio / Oscillator Frequency Set Grayscale Table Set Biasing Current for DC DC converter BE A[5:] BC A[7:] B A[3:] A[7:4] B2 A[7:] B3 A[3:] A[7:4] B8 A[2:] B[2:] B[6:4] C[2:] C[6:4] D[2:] D[6:4] E[2:] E[6:4] F[2:] F[6:4] G[2:] G[6:4] H[2:] H[6:4] CF A[7:6] A7 A7 A7 A7 A7 B6 C6 D6 E6 F6 G6 H6 B5 C5 D5 E5 F5 G5 H5 B4 C4 D4 E4 F4 G4 H4 B2 C2 D2 E2 F2 G2 H2 A A A A A A B C D E F G H A A A A A A B C D E F G H Sets the VCOMH voltage level. A[5:] = xxxxx =.VREF Sets the precharge voltage level A[7:] = xxxxxxx connects to VCOMH A[7:] = xxxxx equals.vref A[3:] = P. Phase period of 5 DCLK clocks A[7:4] = P2. Phase 2 period of 5 DCLK clocks Sets number of DCLKs (K) per row. Range 2 58DCLKs. K = P + P2 + GS5 pulse width (RESET values: ) A[3:] = Define the divide ratio of the display clocks. Range 6 Divide ratio = A[3:] + A[7:4] = Set the Oscillator Frequency. Frequency increases with the value of A[7:4]. Range b~b. Sets the gray scale level. Range 5 A[2:] = L B[2:] = L2 B[6:4] = L3 C[2:] = L4 C[6:4] = L5 D[2:] = L6 D[6:4] = L7 E[2:] = L8 E[6:4] = L9 F[2:] = L F[6:4] = L G[2:] = L2 G[6:4] = L3 H[2:] = L4 H[6:4] = L5 xf = HIGH x7 = LOW NOP E3 Command for No Operation AEh DCLKs (x25) 2 xf For detailed instruction information, see datasheet: [8]

9 MPU Interface For detailed timing information, see datasheet: 68 MPU Parallel Interface The parallel interface consists of 8 bi directional data pins, R/W, D/C, E, and /CS. A LOW on R/W indicates write operation, and HIGH on R/W indicates read operation. A LOW on D/C indicates Command read or write, and HIGH on D/C indicates Data read or write. The E input serves as data latch signal, while /CS is LOW. Data is latched at the falling edge of E signal. Function E R/W /CS D/C Write Command Read Status Write Data Read Data 88 MPU Parallel Interface The parallel interface consists of 8 bi directional data pins, /RD, /WR, D/C, and /CS. A LOW on D/C indicates Command read or write, and HIGH on D/C indicates Data read or write. A rising edge of /RS input serves as a data read latch signal while /CS is LOW. A rising edge of /WR input serves as a data/command write latch signal while /CS is LOW. Function /RD /WR /CS D/C Write Command Read Status Write Data Read Data Alternatively, /RD and /WR can be kept stable while /CS serves as the data/command latch signal. Function /RD /WR /CS D/C Write Command Read Status Write Data Read Data [9]

10 Serial Interface The serial interface consists of serial clock SCLK, serial data SDIN, D/C, and /CS. D acts as SCLK and D acts as SDIN. D2 should be left open. D3~D7, E, and R/W should be connected to GND. Function /RD /WR /CS D/C D Write Command Write Data SDIN is shifted into an 8 bit shift register on every rising edge of SCLK in the order of D7, D6, D. D/C is sampled on every eighth clock and the data byte in the shift register is written to the GDRAM or command register in the same clock. Note: Read is not available in serial mode. For detailed protocol information, see datasheet: Example Initialization Sequence: Set_Display_On_Off_2864(x); // Display Off (x/x) Set_Display_Clock_2864(x9); // Set Clock as 35 Frames/Sec Set_Multiplex_Ratio_2864(x3F); // /64 Duty (xf~x5f) Set_Display_Offset_2864(x4C); // Shift Mapping RAM Counter (x~x5f) Set_Start_Line_2864(x); // Set Mapping RAM Display Start Line (x~x5f) Set_Master_Config_2864(x); // Disable Embedded DC/DC Converter (x/x) Set_Remap_Format_2864(x5); // Set Column Address Mapped to SEG // Disable Nibble Remap // Horizontal Address Increment // Scan from COM[N ] to COM // Enable COM Split Odd Even Set_Current_Range_2864(x2); // Set Full Current Range Set_Gray_Scale_Table_2864(); // Set Pulse Width for Gray Scale Table Set_Contrast_Current_2864(brightness); // Set Scale Factor of Segment Output Current Control Set_Frame_Frequency_2864(x5); // Set Frame Frequency Set_Phase_Length_2864(x55); // Set Phase as 5 Clocks & Phase 2 as 5 Clocks Set_Precharge_Voltage_2864(x); // Set Pre Charge Voltage Level Set_Precharge_Compensation_2864(x2,x2); // Set Pre Charge Compensation Set_VCOMH_2864(xC); // Set High Voltage Level of COM Pin Set_VSL_2864(xD); // Set Low Voltage Level of SEG Pin Set_Display_Mode_2864(x); // Normal Display Mode (x/x/x2/x3) Fill_RAM_2864(x); // Clear Screen Set_Display_On_Off_2864(x); // Display On (x/x) []

11 Quality Information Test Item Content of Test Test Condition Note High Temperature storage Test the endurance of the display at high +9⁰C, 24hrs 2 storage temperature. Low Temperature storage Test the endurance of the display at low 4⁰C, 24hrs,2 storage temperature. High Temperature Operation applying electric stress (voltage & current) at high temperature. +85⁰C 24hrs 2 Low Temperature Operation High Temperature / Humidity Operation Thermal Shock resistance Vibration test Atmospheric Pressure test Static electricity test applying electric stress (voltage & current) at low temperature. applying electric stress (voltage & current) at high temperature with high humidity. applying electric stress (voltage & current) during a cycle of low and high temperatures. applying vibration to simulate transportation and use. applying atmospheric pressure to simulate transportation by air. 4⁰C, 24hrs,2 +6⁰C, 9% RH, 24hrs,2 4⁰C,3min > 25⁰C,5min > 85⁰C,3min = cycle cycles 22Hz, 5mm amplitude Hz,.5G 3min in each of 3 directions X,Y,Z 5mbar, 4hrs 3 VS=8V, RS=.5kΩ, CS=pF One time applying electric static discharge. Note : No condensation to be observed. Note 2: Conducted after 2 hours of storage at 25⁰C, %RH. Note 3: Test performed on product itself, not inside a container. Evaluation Criteria: : Display is fully functional during operational tests and after all tests, at room temperature. 2: No observable defects. 3: Luminance >5% of initial value. 4: Current consumption within 5% of initial value Precautions for using OLEDs/LCDs/LCMs See Precautions at Warranty Information and Terms & Conditions Newhaven Display International, Inc. reserves the right to alter this product or specification at any time without notification. []

Newhaven Display International, Inc Technology Drive, Suite 101 Elgin IL, Ph: Fax:

NHD 28 25664UCY2 Graphic OLED Display Module NHD Newhaven Display 28 28 diagonal size 25664 256 x 64 pixel resolution UC Model Y Emitting Color: Yellow 2 +295V power supply Newhaven Display International,