Newhaven Display International, Inc Galvin Ct. Elgin IL, Ph: Fax:

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1 NHD UCW2 Graphic OLED Display Module NHD- Newhaven Display Diagonal Size x 64 Pixel Resolution UC- Model W- Emitting Color: White V Power Supply Newhaven Display International, Inc 266 Galvin Ct Elgin IL, 624 Ph: Fax: wwwnewhavendisplaycom nhtech@newhavendisplaycom nhsales@newhavendisplaycom

2 Document Revision History Revision Date Description Changed by 7/27/5 Initial Product Release SB 6/6/7 Optical Characteristics Updated SB 2 /3/8 Mechanical Drawing Updated TM Functions and Features 256 x 64 pixel resolution Built-in SSD322 controller Parallel or serial MPU interface Single, low voltage power supply RoHS compliant [2]

3 SYMBOL REVISION DATE A A B B Segment 2 ( Column ) Segment 357 ( Column 256 ) C Common A ( Row 64 ) Segment 239 ( Column 28 ) Segment 24 ( Column 29 ) Common B ( Row 64 ) C Common A63 ( Row ) Common B63 ( Row ) D 3 28 D 28 3 Detail "A" E E F Notes: Color: White 2 Driver IC: SSD322 3 Interface: 8-Bit 68XX/8XX Parallel, 3 or 4-Wire SPI STANDARD TOLERANCES (UNLESS OTHERWISE SPECIFIED) LINEAR: XX ±3 mm XXX ±3 mm XXXX ±3 mm UNLESS OTHERWISE SPECIFIED - DIMENSIONS ARE IN MILLIMETERS DRAWING/PART NUMBER: NHD UCW DRAWN BY: T Mellenthin CHECKED BY: TMellenthin APPROVED BY: S Baxi REVISION: SIZE: DRAWN DATE: /3/8 CHECKED DATE: /3/8 APPROVED DATE: /3/8 X:X - THIRD ANGLE PROJECTION DO NOT SCALE DRAWING SHEET OF THIS DRAWING IS SOLELY THE PROPERTY OF NEWHAVEN DISPLAY INTERNATIONAL, INC THE INFORMATION IT CONTAINS IS NOT TO BE DISCLOSED, REPRODUCED OR COPIED IN WHOLE OR PART WITHOUT WRITTEN APPROVAL FROM NE WHAVEN DISPLAY SCALE: F

4 Interface Description Parallel Interface: Pin No Symbol External Connection Function Description VSS Power Supply Ground 2 VDD Power Supply Supply Voltage for OLED and logic 3 NC - No Connect 4 D/C MPU Register select signal D/C=: Command, D/C=: Data 5 R/W or /WR MPU 68-interface: Read/Write select signal, R/W=: Read R/W: =: Write 88-interface: Active LOW Write signal 6 E or /RD MPU 68-interface: Operation enable signal Falling edge triggered 88-interface: Active LOW Read signal 7-4 DB DB7 MPU 8-bit Bi-directional data bus lines 5 NC - No Connect 6 /RES MPU Active LOW Reset signal 7 /CS MPU Active LOW Chip Select signal 8 NC - No Connect 9 BS MPU MPU Interface Select signal 2 BS MPU MPU Interface Select signal Serial Interface: Pin No Symbol External Connection Function Description VSS Power Supply Ground 2 VDD Power Supply Supply Voltage for OLED and logic 3 NC - No Connect 4 D/C MPU Register select signal D/C=: Command, D/C=: Data Tie LOW for 3-wire Serial Interface 5-6 VSS Power Supply Ground 7 SCLK MPU Serial Clock signal 8 SDIN MPU Serial Data Input signal 9 NC - No Connect -4 VSS Power Supply Ground 5 NC - No Connect 6 /RES MPU Active LOW Reset signal 7 /CS MPU Active LOW Chip Select signal 8 NC - No Connect 9 BS MPU MPU Interface Select signal 2 BS MPU MPU Interface Select signal MPU Interface Pin Selections Pin Name 68 Parallel 8-bit interface 88 Parallel 8-bit interface 3-wire Serial Interface 4-wire Serial Interface BS BS [4]

5 MPU Interface Pin Assignment Summery Bus Data/Command Interface Control Signals Interface D7 D6 D5 D4 D3 D2 D D E R/W /CS D/C /RES 8-bit 68 D[7:] E R/W /CS D/C /RES 8-bit 88 D[7:] /RD /WR /CS D/C /RES 3-wire SPI Tie LOW NC SDIN SCLK Tie LOW /CS Tie LOW /RES 4-wire SPI Tie LOW NC SDIN SCLK Tie LOW /CS D/C /RES Wiring Diagrams [5]

6 Electrical Characteristics Item Symbol Condition Min Typ Max Unit Operating Temperature Range TOP Absolute Max ⁰C Storage Temperature Range TST Absolute Max ⁰C Supply Voltage VDD V Supply Current (logic) IDD TOP=25 C, VDD=3V ma Supply Current (display) ICC 5% ON, VDD=3V ma % ON, VDD=3V ma H Level input VIH - 8 VDD - VDD V L Level input VIL - VSS - 2 VDD V H Level output VOH - 9 VDD - VDD V L Level output VOL - VSS - VDD V Optical Characteristics Item Symbol Condition Min Typ Max Unit Top ϕy ⁰ Optimal Viewing Bottom ϕy ⁰ Angles Left θx ⁰ Right θx ⁰ Contrast Ratio Cr - :: Response Time Rise TR µs Fall TF µs Brightness LV 5% Checkerboard cd/m 2 Lifetime - LV = 6 cd/m² 5% Checkerboard 5, 25, - Hrs Note: Lifetime at typical temperature is based on accelerated high-temperature operation Lifetime is tested at average 5% pixels on and is rated as Hours until Half-Brightness The Display OFF command can be used to extend the lifetime of the display Luminance of active pixels will degrade faster than inactive pixels Residual (burn-in) images may occur To avoid this, every pixel should be illuminated uniformly [6]

7 Built-in SSD322 controller Instruction Table Instruction Enable Grayscale Table Set Column Address Code Description D/C HEX DB7 DB6 DB5 DB4 DB3 DB2 DB DB Enable the Grayscale table settings (see command xb8) 5 A[6:] B[6:] A6 B6 A5 B5 A4 B4 B3 B2 A B [7] A B Set column start and end address A[6:]: Column start address Range: -9d B[6:]: Column end address Range: -9d Write RAM 5C Enable MCU to write Data into RAM Command Read RAM 5D Enable MCU to read Data from RAM Command Set Row Address 75 Set row start and end address A[6:] A6 A5 A4 A A A[6:]: Row start address Range: -27d B[6:] B6 B5 B4 B3 B2 B B B[6:]: Row end address Range: -27d Set Remap A A[] = ; Horizontal Address Increment A[5:] A5 A4 A A A[] = ; Vertical Address Increment B[4] B4 A[] = ; Disable Column Address remap A[] = ; Enable Column Address remap A[2] = ; Disable Nibble remap A[2] = ; Enable Nibble remap A[4] = ; Scan from COM to COM[N-] A[4] = ; Scan from COM[N-] to COM A[5] = ; Disable COM split Odd/Even A[5] = ; Enable COM split Odd/Even B[4] = ; Disable Dual COM mode B[4] = ; Enable Dual COM mode Note: A[5] must be if B[4] is Set Display Start A Line A[6:] A6 A5 A4 A A Set Display Offset A[6:] A6 A5 A4 A A Display Mode A4/A7 X2 X X xa4 = Entire display OFF xa5 = Entire display ON, all pixels Grayscale level 5 xa6 = Normal display xa7 = Inverse display Enable Partial Display A8 A[6:] B[6:] A6 B6 A5 B5 A4 B4 B3 B2 A B A B RESET value Set display RAM display start line register from -27 Set vertical shift by COM from ~27 Turns ON partial mode A[6:] = Address of start row B[6:] = Address of end row (B[6:] > A[6:]) 9d 27d xa6

8 Exit Partial Display A9 Exit Partial Display mode Function Selection AB A[] = ; External VDD A[] A A[] = ; Internal VDD regulator Set Sleep Mode ON/OFF AE~AF X xae = Sleep Mode ON (display OFF) xaf = Sleep Mode OFF (display ON) Set Phase Length B A[7:] A7 A6 A5 A4 A A A[3:] = P Phase period of 5-3 DCLK clocks A[7:4] = P2 Phase 2 period of 3-5 DCLK clocks 9 7 Set Display Clock B3 A[3:] = ; divide by Divide Ratio / A[7:] A7 A6 A5 A4 A A A[3:] = ; divide by 2 Oscillator A[3:] = ; divide by 4 A[3:] = ; divide by 8 Frequency A[3:] = ; divide by 6 A[3:] = ; divide by 32 A[3:] = ; divide by 64 A[3:] = ; divide by 28 A[3:] = ; divide by 256 A[3:] = ; divide by 52 A[3:] = ; divide by 24 A[3:] >= ; invalid b A[7:4] = Set the Oscillator Frequency Frequency increases with the value of A[7:4] Range b~b Set GPIO Set Second Precharge Period Set Grayscale Table B5 A[3:] B6 A[3:] B8 A[7:] [7:] A4[7:] A5[7:] A7 7 A47 A57 A6 6 A46 A56 A5 5 A45 A55 A4 4 A44 A54 3 A43 A53 2 A42 A52 A A A A4 A5 [8] A A A A4 A5 A[:] = ; GPIO input disabled A[:] = ; GPIO input enabled A[:] = ; GPIO output LOW A[:] = ; GPIO output HIGH A[3:2] = ; GPIO input disabled A[3:2] = ; GPIO input enabled A[3:2] = ; GPIO output LOW A[3:2] = ; GPIO output HIGH Sets the second precharge period A[3:] = DCLKs Sets the gray scale pulse width in units of DCLK Range -8d A[7:] = Gamma Setting for GS [7:] = Gamma Setting for GS2 A4[7:] = Gamma Setting for GS4 A5[7:] = Gamma Setting for GS5 Note: < GS < GS2 < GS3 < GS4 < GS5 The setting must be followed by command x Select Default B9 Sets Linear Grayscale table b b b

9 Linear Gray Scale Table Set Precharge Voltage Set VCOMH Voltage Set Contrast Control Master Contrast Control Set Multiplex Ratio Set Command Lock BB A[4:] BE A[3:] C A[7:] C7 A[3:] CA A[6:] FD A[2] A7 A6 A6 A5 A5 A4 A4 A4 A A A A A A A A A A GS pulse width = GS pulse width = GS pulse width = 8 GS pulse width = 6 GS pulse width = 4 GS pulse width = 2 Set precharge voltage level A[4:] = x; 2VCC A[4:] = x3e; 6VCC Sets the VCOMH voltage level A[3:] = x; 72VCC A[3:] = x4; 8VCC A[3:] = x7; 86VCC Double byte command to select out of 256 contrast steps Contrast increases as the value increases A[3:] = x; Reduce output for all colors to /6 A[3:] = x; Reduce output for all colors to 2/6 A[3:] = xe; Reduce output for all colors to 5/6 A[3:] = xf; no change Set MUX ratio to N+ MUX N=A[6:]; from 6MUX to 28MUX ( to 4 are invalid) A[2] = ; Unlock OLED to enable commands A[2] = ; Lock OLED from entering commands x7 x4 x7f xf 27d x2 For detailed instruction information, see datasheet: [9]

10 MPU Interface For detailed timing information, see datasheet: 68-MPU Parallel Interface The parallel interface consists of 8 bi-directional data pins, R/W, D/C, E, and /CS A LOW on R/W indicates write operation, and HIGH on R/W indicates read operation A LOW on D/C indicates Command read or write, and HIGH on D/C indicates Data read or write The E input serves as data latch signal, while /CS is LOW Data is latched at the falling edge of E signal Function E R/W /CS D/C Write Command Read Status Write Data Read Data 88-MPU Parallel Interface The parallel interface consists of 8 bi-directional data pins, /RD, /WR, D/C, and /CS A LOW on D/C indicates Command read or write, and HIGH on D/C indicates Data read or write A rising edge of /RS input serves as a data read latch signal while /CS is LOW A rising edge of /WR input serves as a data/command write latch signal while /CS is LOW Function /RD /WR /CS D/C Write Command Read Status Write Data Read Data Alternatively, /RD and /WR can be kept stable while /CS serves as the data/command latch signal Function /RD /WR /CS D/C Write Command Read Status Write Data Read Data []

11 Serial Interface (4-wire) The 4-wire serial interface consists of serial clock SCLK, serial data SDIN, D/C, and /CS D acts as SCLK and D acts as SDIN D2 should be left open D3~D7, E, and R/W should be connected to GND Function /RD /WR /CS D/C D Write Command Tie LOW Tie LOW Write Data Tie LOW Tie LOW SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, D D/C is sampled on every eighth clock and the data byte in the shift register is written to the GDRAM or command register in the same clock Note: Read is not available in serial mode Serial Interface (3-wire) The 3-wire serial interface consists of serial clock SCLK, serial data SDIN, and /CS D acts as SCLK and D acts as SDIN D2 should be left open D3~D7, E, R/W, and D/C should be connected to GND Function /RD /WR /CS D/C D Write Command Tie LOW Tie LOW Tie LOW Write Data Tie LOW Tie LOW Tie LOW SDIN is shifted into an 9-bit shift register on every rising edge of SCLK in the order of D/C, D7, D6, D D/C (first bit of the sequential data) will determine if the following data byte is written to the Display Data RAM (D/C = ) or the command register (D/C = ) Note: Read is not available in serial mode For detailed protocol information, see datasheet: []

12 Example Initialization Sequence: Set_Command_Lock(x2); // Unlock Basic Commands (x2/x6) Set_Display_On_Off(x); // Display Off (x/x) Set_Column_Address(xC,x5B); Set_Row_Address(x,x3F); Set_Display_Clock(x9); // Set Clock as 8 Frames/Sec Set_Multiplex_Ratio(x3F); // /64 Duty (xf~x3f) Set_Display_Offset(x); // Shift Mapping RAM Counter (x~x3f) Set_Start_Line(x); // Set Mapping RAM Display Start Line (x~x7f) Set_Remap_Format(x4); // Set Horizontal Address Increment // Column Address Mapped to SEG // Disable Nibble Remap // Scan from COM[N-] to COM // Disable COM Split Odd Even // Enable Dual COM Line Mode Set_GPIO(x); // Disable GPIO Pins Input Set_Function_Selection(x); // Enable Internal VDD Regulator Set_Display_Enhancement_A(xA,xFD); // Enable External VSL Set_Contrast_Current(x9F); // Set Segment Output Current Set_Master_Current(xF); // Set Scale Factor of Segment Output Current Control //Set_Gray_Scale_Table(); // Set Pulse Width for Gray Scale Table Set_Linear_Gray_Scale_Table(); //set default linear gray scale table Set_Phase_Length(xE2); // Set Phase as 5 Clocks & Phase 2 as 4 Clocks Set_Display_Enhancement_B(x2); // Enhance Driving Scheme Capability (x/x2) Set_Precharge_Voltage(xF); // Set Pre-Charge Voltage Level as 6VCC Set_Precharge_Period(x8); // Set Second Pre-Charge Period as 8 Clocks Set_VCOMH(x7); // Set Common Pins Deselect Voltage Level as 86VCC Set_Display_Mode(x2); // Normal Display Mode (x/x/x2/x3) Set_Partial_Display(x,x,x); // Disable Partial Display Set_Display_On_Off(x); [2]

13 Quality Information Test Item Content of Test Test Condition Note High Temperature storage Test the endurance of the display at high +9⁰C, 24hrs 2 storage temperature Low Temperature storage Test the endurance of the display at low -4⁰C, 24hrs,2 storage temperature High Temperature Operation applying electric stress (voltage & current) at high temperature +85⁰C, 24hrs 2 Low Temperature Operation High Temperature / Humidity Operation Thermal Shock resistance Vibration test Atmospheric Pressure test Static electricity test applying electric stress (voltage & current) at low temperature applying electric stress (voltage & current) at high temperature with high humidity applying electric stress (voltage & current) during a cycle of low and high temperatures applying vibration to simulate transportation and use applying atmospheric pressure to simulate transportation by air -4⁰C, 24hrs,2 +6⁰C, 9% RH, 24hrs,2-4⁰C 3min -> 25⁰C 5min -> 85⁰C 3min = cycle For cycles -22Hz, 5mm amplitude Hz, 5G 3min in each of 3 directions X,Y,Z 5mbar, 4hrs 3 VS=8V, RS=5kΩ, CS=pF One time applying electric static discharge Note : No condensation to be observed Note 2: Conducted after 2 hours of storage at 25⁰C, %RH Note 3: Test performed on product itself, not inside a container Evaluation Criteria: : Display is fully functional during operational tests and after all tests, at room temperature 2: No observable defects 3: Luminance >5% of initial value 4: Current consumption within 5% of initial value Precautions for using OLEDs/LCDs/LCMs See Precautions at wwwnewhavendisplaycom/specs/precautionspdf Warranty Information and Terms & Conditions Newhaven Display International, Inc reserves the right to alter this product or specification at any time without notification [3]

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