SPI Overview and Operation

Transcription

1 White Paper Abstract Communications between semiconductor devices is very common. Many different protocols are already defined in addition to the infinite ways to communicate with a proprietary protocol. This paper will provide an overview of SPI, show some of its advantages and disadvantages, and provide a working example for the M16C/Tiny Series of microcontrollers. REJxxxxxxx-xxxx/Rev.5.00 August 2007 Page 1 of 10

2 Contents 1. SPI Overview Interface Communication Advantages and Disadvantages References... 8 REJxxxxxxx-xxxx/Rev.0.10 February 2008 Page 2 of 10

3 1. SPI Overview SPI Overview and Operation SPI stands for Serial Peripheral Interface. It is often referred to as Es Pee Eye or Spy. These are generally accepted as interchangeable and mean the same thing. Originally defined at Motorola, SPI is one of the main serial interfaces used in embedded systems today, and consists of a simple 4 wire interface and basic signaling rules. In any SPI system, there is always at least one Master device which generates the bus clock for the system, and always at least one Slave device which is the peripheral in the system. A very common setup is to have a 16bit Microcontroller as the Master, and a SPI EEPROM (Electrically Erasable Programmable Read Only Memory) device as a slave. A real world application could be a diagnostic module where the microcontroller collects environmental information and stores it periodically in Non-Volatile memory (the EEPROM). SPI is one of the least constrictive serial standards. Other than the definition of the bus interface, and the polarity and phase of the signaling (explained in depth later), almost all of the other elements of communication are either left to the system designer or are required by the logic of the slave for proper operation. 2. Interface Figure 1, below, shows a simple single Master, single Slave SPI system. The interface lines are: SCLK Serial Clock (from the master) MOSI Master Out / Slave In (data from the master) MISO Master In / Slave Out (data from the slave, but clocked out by the master) SS Slave Select (Active Low signal selects/enables the slave device) Figure 1. Simple SPI Block Diagram / Bus Interface These names are not strictly defined although they make logical sense from a system perspective. Some datasheets and descriptions will use other naming conventions for the bus wires, such as Chip Select (CS) for Slave Select, or more usually SDO and SDI (Serial Data Out and Serial Data In, respectively) which is more complex to deal with because those descriptions rely on the perspective from one of the devices. i.e. A Slave s SDO pin would have to be connected to the SDI pin of the Master. REJxxxxxxx-xxxx/Rev.0.10 February 2008 Page 3 of 10

4 3. Communication 3.1 SPI Modes SPI supports four modes of operation. There are two choices of clock polarity and two choices of phase. The labels for these modes are usually CPOL (Clock Polarity) and CPHA (Clock Phase) and they describe when data should be sampled relative to the clock and the clocks behavior. So Mode 0,0 would be polarity (CPOL) = zero, and phase (CPHA) = zero. The other modes are 0,1 1,0 and 1,1 Here is a visual description of the clock signal in the various modes: Figure 3: SPI Modes In the case of Mode 0,0 shown in the top-left corner of Figure 3, CPOL dictates that the clock s rest state is at logic 0. You can see that the clock starts out low. CPHA in this mode is 0, which means that data will be sampled on the first clock edge in this case the rising edge. This is shown by the red sample line. In the case of Mode 0,1 shown in the top-right corner, CPOL dictates that the clock s rest state is at logic 0. The clock starts out low. CPHA in this mode is 1, which means that data will be sampled on the second clock edge in this case the falling edge. This is shown by the red sample line. In the case of Mode 1,0 shown in the bottom-left corner of Figure 3, CPOL dictates that the clock s rest state is at logic 1. The clock starts out high. CPHA in this mode is 0, which means that data will be sampled on the first clock edge in this case a falling edge. In the case of Mode 1,1 shown in the bottom-right corner, CPOL dictates that the clock s rest state is at logic 1. The clock starts out high. CPHA in this mode is 1, which means that data will be sampled on the second clock edge in this case the rising edge. Take another look at the real trace in Figure 2, you can see that the data on the SDO line from the microcontroller is being latched on the falling edge and read to be sampled on the 2 nd edge i.e. rising. The rest state of the clock is high, so this communication is in Mode 1,1. Not all devices support all SPI modes. Some examples are below: ST Micro M95080 EEPROM supports MODE 0, MODE 3 National Semi LM74 Temp Sensor supports MODE 0, MODE 3 Maxim MAX5422 Digital Potentiometer - supports MODE 3 only REJxxxxxxx-xxxx/Rev.0.10 February 2008 Page 4 of 10

5 3.2 Slave Select SPI Overview and Operation In a single or multiple slave system, the active slave is designated by its individual SS pin. This negates the need for any addressing, but can add to the physical resources used, as each slave may need its own dedicated SS from the master. The master sends the SS line low, sends data, and then deselects the SS line by sending it high. Some slaves may allow themselves to be permanently active, meaning the master in a single master, single slave configuration doesn t need to control the SS line it can be connected to ground. Of course, you will need to check the slave datasheet to make sure this is valid operation. In the majority of embedded systems where a microcontroller acts as the master, the SS is implemented with a simple I/O pin, sent high or low using software. 3.3 Clock Generation The Master device is responsible for generating the clock signal. There are a number of ways to achieve this if you intend to use a microcontroller as the master. One partly automated way to send and receive 8-bit data, is to configure the UART of the device to clock out the transmitted data, and send dummy bytes (the data sent could be 0x00 for example) to clock data back out of the slave. One thing to be mindful of here is the speed of the clock. Take care to set the generated clock speed (or baud rate) at a frequency equal to or less than the maximum specified frequency of the slave. 3.4 Framing It should be noted that SPI words are not framed. There are no start or stop bits, nor any built in arbitration or error checking. This can be a major advantage in terms of flexibility, speed and ease of use, or a big problem if communications don t go to plan. Robust design is always encouraged and mechanisms such as check-summing and timeouts should be employed to ensure the system doesn t crash in some way. However, these things are not mandatory in SPI. 3.5 Full Duplex Operation SPI communications are full duplex. Often, when the Master provides clock signals, the slave will send out data. This data is not always relevant and the Master should decide whether to accept or discard the data on the MISO line. REJxxxxxxx-xxxx/Rev.0.10 February 2008 Page 5 of 10

6 3.6 Example Communication SPI Overview and Operation Figure 2, below shows a real SPI communication between a Renesas M16C28 microcontroller and a ST Micro M95080 SPI serial EEPROM. Figure 2: A real SPI trace REJxxxxxxx-xxxx/Rev.0.10 February 2008 Page 6 of 10

7 Picture 1 The SS (labeled CS for Chip Select in the scope trace) is sent low to enable the EEPROM. Picture 2 SPI Overview and Operation The first byte is sent from the M16C28. Eight clocks are sent on SCLK (SCK in the scope trace), and the MOSI (SDO) data is Binary (Hexadecimal 0x03) sent Most Significant Bit first. This is a command to the EEPROM to read from the memory. Picture 3 The next two bytes sent are 0x00 and 0x00 which is the 16bit address that the read should start from. Picture 4 Then with each byte clocked, the EEPROM will send back the contents of the memory at that address and automatically increment its address pointer. In the example we are clocking out 4 bytes from the memory starting at address 0x0000. The first byte is 0xAA so the contents of the EEPROM at address 0x0000 is 0xAA. Picture 5 The data on the MISO line shows the contents of the EEPROM at addresses 0x0001 thru 0x0003 are all 0xFF Picture 6 The SS is then sent high to deselect the slave and reset its logic, ready for the next command. 3.7 Data Words In keeping with the unrestrictive nature of SPI, the bit size of a data word is not defined. There are SPI slaves that logically use 8, 12, 16bit and other word sizes. The master configuration and software needs to be aware of this as it generates the correct number of clocks and interprets data to and from the buffers. To send a data word which is not a standard 8 bits, it is important to either set up the UART or serial peripheral to send clocked data bits without start and stop edges. Some peripherals may not support this, but it would always be possible to send words of any length using bit-banged I/O pins and custom firmware. This also means that there is no defined error checking or recovery system. At the application level it may be prudent to employ a checksum when communicating with a storage device like a serial EEPROM. For example; when writing a block of data to an EEPROM, the data could be used to calculate a checksum, then written to the EEPROM and then read back. The read data is then used to calculate a checksum and compared against the original to ensure the correct data was stored without errors. 3.8 Data Direction SPI data is sent and received Most Significant Bit (MSB) first. REJxxxxxxx-xxxx/Rev.0.10 February 2008 Page 7 of 10

8 4. Advantages and Disadvantages 4.1 Advantages Full Duplex Operation Potentially faster than I2C or Microwire due to decreased overhead Flexible packet size - not restricted to 8bit data User chooses message content and meaning Simple hardware interface Slaves use the master clock no need for additional oscillators No transceivers required physical interface is user defined Less pins required than parallel interface 4.2 Disadvantages More pins required on each device than I2C or < 4-wire interfaces No addressing so each slave needs independent SS signals No Slave acknowledgment No bus arbitration Multi-master systems are difficult to implement No formal standard makes quality control and testing more difficult 5. References SPI Block Guide - Freescale Semiconductor ST Micro M95080 SPI EEPROM Device Datasheet Maxim MAX542x Digital Potentiometer Datasheet National Semiconductor LM74 Temp Sensor Datasheet Renesas M16C28 Device Datasheet REJxxxxxxx-xxxx/Rev.0.10 February 2008 Page 8 of 10

9 Website and Support Renesas Technology Website Renesas Technology America Website Inquiries (Global Support) (United States / Canada / Mexico only) Revision Record Description Rev. Date Page Summary 0.10 Feb Pre-Release 0.20 Feb Multiple Changes to Layout and Content from 1 st Draft REJxxxxxxx-xxxx/Rev.0.10 February 2008 Page 9 of 10

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