NCP347. Positive Overvoltage Protection Controller with Internal Low R ON NMOS FET and Status FLAG

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1 Positive Overvoltage Protection Controller with Internal Low R ON NMOS FET and Status The NCP347 is able to disconnect the systems from its output pin in case wrong input operating conditions are detected. The system is positive overvoltage protected up to +8 V. Due to this device using internal NMOS, no external device is necessary, reducing the system cost and the PCB area of the application board. The NCP347 is able to instantaneously disconnect the output from the input, due to integrated Low R ON Power NMOS (6 m ), if the input voltage exceeds the overvoltage threshold (OVLO) or undervoltage threshold (UVLO). At powerup ( pin = low level), the V out turns on 0 ms after the V in exceeds the undervoltage threshold. The NCP347 provides a negative going flag () output, which alerts the system that a fault has occurred. In addition, the device has ESD-protected input ( kv Air) when bypassed with a.0 F or larger capacitor. Features Overvoltage Protection up to 8 V On-Chip Low R DS(on) NMOS Transistor: 6 m Internal Charge Pump Overvoltage Lockout (OVLO) Undervoltage Lockout (UVLO) Internal 0 ms Startup Delay Alert Output Shutdown Input Compliance to IEC (Level 4) 8.0 kv (Contact) kv (Air) ESD Ratings: Machine Model = B Human Body Model = 3 0 Lead WDFN.x mm Package This is a Pb-Free Device Applications Cell Phones Camera Phones Digital Still Cameras Personal Digital Applications MP3 Players WDFN0 MT SUFFIX CASE 6AA P CONNECTIONS MARKG DIAGRAM XXX = Specific Device Code M = Date Code = Pb-Free Package GND 3 4 PAD GND PAD (Top View) XXX M NC NC OUT OUT ORDERG FORMATION See detailed ordering, marking and shipping information in the package dimensions section on page of this data sheet. Semiconductor Components Industries, LLC, 008 April, Rev. Publication Order Number: NCP347/D

2 V Bat V Bat Wall Adapter - AC/DC NCP347 OUT 6 4 F OUT 7 NC 8 0 NC 9 V Bat 3 ABLE / M Microprocessor GND 0 D3 70X/SM NCP83B 3 V CC 4.7 F ISEL K CFLG FAULT TIMER Figure. Typical Application Circuit 6 VP8 7 VSNS 9 BAT 0 GND pf ABLE / Microprocessor VP8 V Bat 00 nf Lithium BATTERY 0 PUT OUTPUT 60 ma ESD Protection Core Negative Protection Output Impedance = 00 k Charge Pump Gate Driver 00 khz Delay Generator ESD Protection LDO Oscillator Power ON 0 V V REG V REG Block UVLO V REF UVLO OVLO OVLO V REF V REF DISABLE ESD Protection Figure. Functional Block Diagram

3 P FUNCTION DESCRIPTION Pin No. Symbol Function Description 4 POWER Input Voltage Pin. This pin is connected to the power supply. The device system core is supplied by this input. A F low ESR ceramic capacitor, or larger, must be connected between this pin and GND. The three pins must be hardwired to common supply. GND POWER Ground 3 OUTPUT Fault Indication Pin. This pin allows an external system to detect a fault on pin. The pin goes low when input voltage exceeds OVLO threshold or drop below UVLO threshold. Since the pin is open drain functionality, an external pull up resistor to V CC must be added. 6 7 OUT OUTPUT Output Voltage Pin. This pin follows pin when no fault is detected. The output is disconnected from the V in power supply when the input voltage is under the UVLO threshold or above OVLO threshold. The two OUT pins must be hardwired to common supply. 8 NC OP No Connect 9 NC OP No Connect 0 PUT Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the output is disconnected from the input. To allow normal functionality, the pin shall be connected to GND to a pull down or to a I/O pin. This pin does not have an impact on the fault detection. PAD PAD, under the device. See PCB recommendations page 0. Can be shorted to GND. PAD The PAD is electrically connected to the internal NMOS drain and connected to Pins 4 and. See PCB recommendations page 0. MAXIMUM RATGS Rating Symbol Value Unit Minimum Voltage ( to GND) Vmin in -0.3 V Minimum Voltage (All others to GND) Vmin -0.3 V Maximum Voltage ( to GND) Vmax in 30 V Maximum Voltage (All others to GND) Vmax 7.0 V Maximum Current (UVLO<V <OVLO) Imax.0 A Thermal Resistance, Junction-to-Air (Note ) R JA 80 C/W Operating Ambient Temperature Range T A -40 to +8 C Storage Temperature Range T stg -6 to +0 C Junction Operating Temperature T J 0 C ESD Withstand Voltage (IEC ) (input only) when bypassed with.0 F capacitor Human Body Model (HBM), Model = (Note ) Machine Model (MM) Model = B (Note 3) Vesd Air, 8.0 Contact Moisture Sensitivity MSL Level - Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. The R JA is highly dependent on the PCB heat sink area (connected to pad ). As example R JA is 68 C/W with 30 mm (copper 3 m) and 89 C/W with 400 mm.. Human Body Model, 00 pf discharged through a. k resistor following specification JESD/A4. 3. Machine Model, 00 pf discharged through all pins following specification JESD/A. kv V V 3

4 ELECTRICAL CHARACTERISTICS (Min/Max limits values (-40 C < T A < +8 C) and V in = +.0 V. Typical values are T A = + C, unless otherwise noted.) Characteristic Symbol Conditions Min Typ Max Unit Input Voltage Range V in V Undervoltage Lockout Threshold (Note 4) UVLO V in falls down UVLO threshold from V to.7 V V Undervoltage Lockout Hysteresis UVLO hyst V in rises up UVLO + UVLO hyst mv Overvoltage Lockout Threshold (Note 4) NCP347MTAE NCP347MTAF NCP347MTAH NCP347MTAI OVLO V in rises up OVLO threshold V Overvoltage Lockout Hysteresis NCP347MTAE, NCP347MTAF, NCP347MTAI NCP347MTAH OVLO hyst V in falls down OVLO + OVLO hyst 30 0 V in versus V out Resistance R DS(on) V in =.0 V, = GND, Load connected to V out m Supply Quiescent Current Idd No load. =.0 V A No load. = Gnd A UVLO Supply Current Idd uvlo V =.7 V A Output Low Voltage Vol flag. V < V < UVLO Sink 0 A on/ pin mv mv V > OVLO Sink.0 ma on pin mv Leakage Current leak level =.0 V na Voltage High Vih V Voltage Low Vol V Leakage Current leak =.0 V or GND na TIMGS Startup Delay NCP347MTAE, NCP347MTAF, NCP347MTAH NCP347MTAI Going Up Delay NCP347MTAE, NCP347MTAF, NCP347MTAH NCP347MTAI ton From V in > UVLO to V out = 0.3 V (See Figures 3 & 7) tstart From V out = 0.3 V to =. V (See Figures 3 & 9) Output Turn Off Time toff From V in > OVLO to V out < = 0.3 V (See Figures 4 & 8) V in increasing from.0 V to 8.0 V at 3.0 V/ s Rload connected on V out ms ms -..0 s Alert Delay tstop From V in > OVLO to < = 0.4 V (See Figures 4 & 0) V in increasing from.0 V to 8.0 V at 3.0 V/ s Rload connected on V out s Disable Time tdis From > =. V to V out < 0.3 V Rload =.0 (See Figures & ) s NOTE: Electrical parameters are guaranteed by correlation across the full range of temperature. 4. Additional UVLO and OVLO thresholds ranging from UVLO and from OVLO can be manufactured. Contact your ON Semiconductor representative for availability. 4

5 TIMG DIAGRAMS V in V out UVLO t on 0.3 V t start <OVLO V in - (R DS(on) I) OVLO V in t off V out V in - (R DS(on) I) t stop 0.3 V. V 0.4 V Figure 3. Startup Figure 4. Shutdown on Overvoltage Detection. V V out V in - (R DS(on) I). V t dis 0.3 V V in OVLO UVLO 00 ms Figure. Disable on = Figure 6. Response with =

6 TYPICAL OPERATG CHARACTERISTICS Figure 7. Startup V in = Ch, V out = Ch3 Figure 8. Output Turn Off Time V in = Ch, V out = Ch Figure 9. Going Up Delay V out = Ch3, = Ch Figure 0. Alert Delay V out = Ch, = Ch3 Figure. Initial Overvoltage Delay V in = Ch, V out = Ch, = Ch3 Figure. Disable Time = Ch, V out = Ch, = Ch3 6

7 TYPICAL OPERATG CHARACTERISTICS Figure 3. Inrush Current with C out = 00 F, I charge = A, Output Wall Adaptor Inductance H Figure 4. Output Short Circuit Figure. Output Short Circuit (Zoom Fig. 4) 7

8 OUT CONDITIONS V > OVLO 0 < V < UVLO And/Or VOLTAGE DETECTION / = Figure 6. Simplified Diagram OUT CONDITIONS / = 0 & VOLTAGE DETECTION UVLO < V < OVLO Figure 7. Simplified Diagram Operation The NCP347 provides overvoltage protection for positive voltage, up to 8 V. A Low R DS(on) NMOS FET protects the systems (i.e.: charger) connected on the Vout pin, against positive overvoltage. At powerup, with pin = low, the output is rising up 0 ms after the input overtaking undervoltage UVLO (Figure 3). The NCP347 provides a output, which alerts the system that a fault has occurred. A 0 ms additional delay, regarding available output (Figure 3) is added between output signal rising up and to signal rising up. pin is an open drain output. 8

9 V out = 0 = Low Reset Timer V in < UVLO or V in > OVLO V out = 0 = Low Timer Count OVLO > V in > UVLO Timer Check T < 0 ms T = 0 ms Reset Timer V in < UVLO or V in > OVLO Check V in = Low Timer Count UVLO < V in < OVLO V out = Open = Check = 0 V out = V in V in < UVLO or V in > OVLO Timer Check T < 0 ms T = 0 ms UVLO < V in < OVLO Check UVLO < V in < OVLO = = 0 V out = Open = High Check V in V in < UVLO or V in > OVLO V out = V in = High Check V in Figure 8. State Machine 9

10 Undervoltage Lockout (UVLO) To ensure proper operation under any conditions, the device has a built-in undervoltage lockout (UVLO) circuit. During V in positive going slope, the output remains disconnected from input until V in voltage is below.9 V, plus hysteresis, nominal. The output is tied to low as long as V in does not reach UVLO threshold. This circuit has a 60 mv hysteresis to provide noise immunity to transient condition. Additional UVLO thresholds ranging from UVLO can be manufactured. (See Selection Guide on page ) Contact your ON Semiconductor representative for availability. Overvoltage Lockout (OVLO) To protect connected systems on V out pin from overvoltage, the device has a built-in overvoltage lockout (OVLO) circuit. During overvoltage condition, the output remains disabled as long as the input voltage exceeds.67 V typical (NCP347MTAE). Additional OVLO thresholds ranging from OVLO can be manufactured. (See Selection Guide on page ) Contact your ON Semiconductor representative for availability. output is tied to low until V in is higher than OVLO. This circuit has a 90 mv hysteresis to provide noise immunity to transient conditions. Output The NCP347 provides a output, which alerts external systems that a fault has occurred. This pin is tied to low as soon the OVLO threshold is exceeded or when the V in level is below the UVLO threshold. When V in level recovers normal condition, is held high, keeping in mind that an additional 0 ms delay has been added between available output and = high. The pin is an open drain output, thus a pull up resistor (typically M, minimum 0 k ) must be added to V bat. Minimum V bat supply must be. V. The level will always reflects V in status, even if the device is turned off ( = ). Input To enable normal operation, the pin shall be forced to low or connected to ground. A high level on the pin, disconnects OUT pin from pin. does not overdrive an OVLO or UVLO fault. Internal NMOS FET The NCP347 includes an internal Low R DS(on) NMOS FET to protect the systems, connected on OUT pin, from positive overvoltage. Regarding electrical characteristics, the R DS(on), during normal operation, will create low losses on V out pin. As example: R load = 8.0, V in =.0 V Typical R DS(on) = 6 m I out = 68 ma V out = 8 x 0.68 = 4.9 V NMOS losses = R DS(on) x Iout = 0.06 x 0.68 = mw ESD Tests The NCP347 input pin fully supports the IEC F (minimum) must be connected between V in and GND, close to the device. That means, in Air condition, V in has a kv ESD protected input. In Contact condition, V in has 8.0 kv ESD protected input. Please refer to Figure 9 to see the IEC electrostatic discharge waveform. Figure 9. Electrostatic Discharge Waveform PCB Recommendations The NCP347 integrates a amperes rated NMOS FET, and the PCB rules must be respected to properly evacuate the heat out of the silicon. The PAD is internally isolated from the active silicon and should preferably be connected to ground. The PAD of the NCP347 package is connected to the internal NMOS drain and can be used to increase the heat transfer if necessary from an applications standpoint. Depending upon the power dissipated in the application, one can either use the PCB tracks connected to Pins 4 and to evacuate heat, or make profit of the PAD area to add extra copper surface to reduce the junction temperature (See Figure 0). Of course, in any case, this pad shall be not connected to any other potential. Figure 0 shows copper area according to R JA and allows the design of the heat transfer plane connected to PAD. 0

11 30 90 oz C.F. JA ( C/W) oz C.F. oz Sim oz Sim COPPER HEAT SPREADG AREA (mm ) Figure 0. PUT OUTPUT Figure. Demo Board Layout F V XR 0603 C Murata GRM88R6E0KAD _Power _State 4 0 NCP347 OUT OUT NC NC GND C 00 nf 0 V X7R 080 not necessary Power R M R 00 k 3 R3 00 k J _State GND F F F3 F4 Figure. Demo Board Schematic

12 ORDERG FORMATION NCP347MTAETBG NCP347MTAFTBG NCP347MTAHTBG NCP347MTAITBG Device Marking Package Shipping BAL BAM BAK ACJ WDFN-0 (Pb-Free) 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. SELECTION GUIDE The NCP347 can be available in several undervoltage and overvoltage thresholds versions. Part number is designated as follows: NCP347MTxxTxG a b c Code a b c Contents UVLO Typical Threshold a: A =.9 V OVLO Typical Threshold b: E =.63 V b: F =.90 V b: H = 7.0 V b: I =.8 V Tape & Reel Type c: B = 3000

13 PACKAGE DIMSIONS WDFN0,.x, 0.P CASE 6AA-0 ISSUE C 0X X P ONE REFERCE 0.0 C X 0.0 C 0.0 C 0.08 C 0.0 C A B D ÍÍÍ ÍÍÍ A A3 0.0 C D3 D 0X L G A K B E A C SEATG PLANE NOTES:. DIMSIONG AND TOLERANCG PER ASME Y4.M, CONTROLLG DIMSION: MILLIMETERS. 3. DIMSION b APPLIES TO PLATED TERMAL AND IS MEASURED BETWE 0. AND 0.30mm FROM TERMAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMALS. MILLIMETERS DIM M NOM A A A3 0.0 REF b D.0 BSC D D e 0.0 BSC E.00 BSC E G 0.37 BSC G 0.3 BSC K L SOLDERG FOOTPRT* MAX X 0.8 E.3 0X X e 0.0 C A B 0.0 C 0 G 6 b 0X 0.0 C 0.0 C A B NOTE PITCH DIMSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERG FORMATION LITERATURE FULFILLMT: Literature Distribution Center for ON Semiconductor P.O. Box 63, Denver, Colorado 807 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your loca Sales Representative NCP347/D