Freescale Semiconductor, I CHAPTER 1 - GENERAL INFORMATION

Transcription

1 nc. GENERAL INFORMATION CHAPTER 1 - GENERAL INFORMATION 1 1 INTRODUCTION This manual provides a general information for the M68302FADS-ENA. It include, preparation for use, installation and operating instructions, functional description, and support information.the ENA is an adapter board for the 68EN302 In order to use this board the user has to connect it to the M68302FADS Board and be familiar with it. 1 2 GENERAL FEATURES A complete system development board for The MC68EN302 processor running at 20Mhz. Expansion connectors providing all EN302 processor signals. 12V supply for the AUI Ethernet. Dram socket for 2 SIMM up to 8Mbyte Ethernet interface (twisted-pair and AUI) using Motorola MC Status LEDs for Ethernet interface. 1

2 GENERAL INFORMATION nc. 1 3 SPECIFICATIONS The M68302FADS-ENA specifications and cooling requirements are given in Table 1-1. Table 1-1 ENA Specifications CHARACTERISTICS Power requirements For ENA adapter and M68302FADS SPECIFICATIONS 3.15 A (maximum) 1 A (maximum) Microprocessor - 20 MHz M68EN302 processor addressing Total address range. SRAM FLASH memory EEPROM DRAM Operating temperature Storage temperature Relative humidity Dimensions Height Depth Thickness 1 4 COOLING REQUIREMENTS 16M byte On the M68302FADS 512K byte, 16 bit wide. (Expandable to 1M bytes) On the M68302FADS 1M byte, 16 bits wide. On the M68302FADS 2K byte, 8 bit wide. On the M68302FADS 8Mbyte 16 bit wide. (+ Parity) On the ENA 0 degrees to 30 degrees C ambient air temperature -25 degrees to 85 degrees C 5% to 90% (non-condensing) 110mm 236mm 1.6mm The M68302FADS-ENA is specified designed, and tested to operate reliably with ambient air temperature range from 0 to 30 degrees C. Dynamic Burn-in is performed while the board is table mounted with connection to M68302FADS board attached to it. Test software is executed as the board is subjected to temperature variations. If the board is attached to other boards, the thermal conditions may worsen. 2

3 nc. GENERAL INFORMATION 1 5 GENERAL DESCRIPTION The M68302FADS-ENA is a development tool for the MC68EN302RC device. The ENA must be connected to M68302FADS and U10,U23,U27 on the M68302FADS must be unpopulated.this board is used for hardware and software development of applications using MC68EN302RC device. The M68302FADS- ENA has expansion connectors, providing physical connection to all processors pins. The logic analyzer connectors on the M68302FADS, enable to monitor bus activity, by providing a direct connection to HP or other logic analyzers. The expansion connectors let the user, to attach hardware applications and to use board resources, to verify the design. 1 6 RELATED DOCUMENTATION The following publications are applicable to the M68302FADS-ENA and may provide additional helpful information. MC68302 IMP User s Manual. M68302FADS manual. MC68EN302 User s Manual. MC68160 EEST User s Manual. 1 7 ABBREVIATIONS USED IN THE DOCUMENT IMP - The MC68302 integrated communication processor. ENA - M68EN302 Adapter board. EEST - Enhanced Ethernet Serial Transceiver MC68160 device. ADS - Application Development System for the 302 family processor. DRAM - Dynamic Random Access Memory SIMM - Single In-line Memory Module. AUI - Attachment Unit Interface. TP - Twisted Pair. spec - Engineering specification document. nsec - nano second. µsec - micro second. NMI - Non Maskable Interrupt. 1 8 REQUIRED EQUIPMENT The M68302FADS-ENA connected to M68302FADS can be operated in two working environments: Host controlled. Stand-alone. 3

4 GENERAL INFORMATION nc. FIGURE 1-1 describes the setup of an host controlled mode. The required equipment in this mode is as follows: +5V/3A,+12V/1A power supply. Host Computer, one of the following: o Sun - 4 (Sbus interface) o IBM-PC/XT/AT ADI board - compatible with the host computer. 37 line flat cable with female 37 pin D-type connectors on each end. FIGURE 1-1 Host Controlled Configuration Running the debugger P3 P1 P2 P3 P4 ENA M68302FADS P10=5V supply When the board is connected as shown in FIGURE 1-1, turn on the 5V power supply and run the host software, by typing: host <ADI sbus slot No.> <ADS ADI address> The manufacturer settings for ADS ADI address is 0. For more details on ADI addresses setting, please see section on M68302FADS User Manual. For example, to run the host on a sun machine with an ADI card installed in its Sbus slot number 1 and with ADS ADI address, set to 3, you should type, at command line prompt: P9 P9 ADI cable P4 P5 P10 P12 P12 host 1 3 The prompt you will get will be: EN302 Monitor/Debugger - Version 0.0 (C) Copyright 1996 Motorola inc Cold Start EN302bug 4

5 nc. GENERAL INFORMATION Stand alone setup FIGURE 1-2 describes the setup of a stand-alone operating mode.the required equipment in this mode is: +5V/3A,12V/1A power supply. VT100 compatible terminal. RS-232 cable with male 9 pin D-type connector on the ADS side. FIGURE 1-2 Stand-alone Configuration RS232 cable P1 P2 P3 P4 P9 P9 P10 P12 P12 P3 P4 P5 ENA P10=5V supply M68302FADS Terminal settings The terminal connected to a M68302FADS board, should be initialized to work with the following settings: Speed bps. Character size - 8 bits. Stop bit length - 1 bit. (1.5 or 2 is fine but 1 is preferred for being a bit faster) No parity. These settings are written shortly as , 8, 1 N. After setting the terminal as specified and turning on the power, a debugger prompt should appear on terminal screen as shown before. 5

6 GENERAL INFORMATION nc Parallel ADI / Serial port, priority. There is no control on 68302FADS board, to select between the parallel ADI or the serial port communication. The debugger decides automatically, with which it should communicate, by giving a priority to the serial port, in case, a terminal is detected. The serial port has some signals, by with the debugger can detect the presence of a terminal. If it is present, then the ADI connection is ignored and all board communication, goes to the serial port. When a terminal is not detected on the serial port, all communication, goes to the ADI port. 6

7 nc. HARDWARE PREPARATION AND INSTALLATION CHAPTER 2 - HARDWARE PREPARATION AND INSTALLATION 2 1 INTRODUCTION This chapter provides unpacking instructions, hardware preparation, and installation instructions for the M68302FADS-ENA. 2 2 UNPACKING INSTRUCTIONS NOTE If the shipping carton is damaged upon receipt, request carrier s agent be present during unpacking and inspection of equipment. Unpack equipment from shipping carton. Refer to packing list and verify that all items are present. Save packing material for storing and reshipping of equipment. CAUTION AVOID TOUCHING AREAS OF INTEGRATED CIRCUITRY; STATIC DISCHARGE CAN DAMAGE CIRCUITS. 7

8 HARDWARE PREPARATION AND INSTALLATION nc. 2 3 HARDWARE PREPARATION To select the desired configuration and ensure proper operation of the M68302FADS-ENA board. Make sure that U10,U23 or U27 not populated on the M68302ADS board. Before connecting the two boards, the following are the Dip-Switch setting required on the M68302FADS. - On M68302FADS board resources enable (SRAM, Flash, EEPROM, ADI port and DUART) - Bus width always setting to 16bit wide. - Processor type selection. - ADI port address selection. The following is Jumper setting required on the M68302FADS-ENA -J2 (DISCPU) on the ENA should be connected on pins 2,3. Switches, LEDs, Dip-Switches, and connectors on the M68302FADS are illustrated in FIGURE 2-1. FIGURE 2-2 describes the M68302FADS-ENA.The ENA board has been factory tested and is shipped with jumpers settings as described in the following paragraphs. 8

9 nc. HARDWARE PREPARATION AND INSTALLATION FIGURE 2-1 M68302FADS Location diagram P4 U37 U9 U39 A B C D P3 E F P2 HALT PCOFF POWER LD2 LD3 LD G H J K L M N RUN PCMCIA U10 P9 DS1 U36 U38 + D2 U31 U32 U33 LC302 PLL R OFF ON Y1 F1 J1 D1 + P1 RN1 C1 RN2 HOST TERMINAL LD1 U20 U A B C D RN4 U23 E F U1 K G H J L M N P12 P5 P6 P7 P8 U17 U6 U28 U29 U7 RN5 U U27 A B C D E F K G H J L M N P P11 OFF ON RLY1 + U2 U3 U5 U26 U25 +C2 U22 U19 U13 ADI PORT RN3 U4 U14 U11 RN6 U21 U18 U15 U12 U30 GND HOOK DS2 RN8 RN7 ADDR LOW SW1 SW2 ADDR HIGH U35 Y2 U8 U34 J3 J2 P10 PCEN PCVCCEN RAMEN FLASHEN EEPROMEN ADIEN DUARTEN ADSA0 ADSA1 ADSA2 DATA CONTROL IOIS16 MODCLK BUSW GND HOOK CHIPTYPE ABORT RESET Pchip PLL PCMCIA PWR INT PC +5V GND 9

10 HARDWARE PREPARATION AND INSTALLATION nc. FIGURE 2-2 M68EN302 ENA Location Diagram DRAM DRAM 10

11 nc. HARDWARE PREPARATION AND INSTALLATION DS1 DIP switch configuration on M68302FADS. Table 2-1 describes the function of switches 1-7. FIGURE 2-3 Dip-Switch DS1 Table 2-1 Dip-Switch DS1 Description Switch Name Function 1 PCEN (Not in use) 2 PCVCCEN (Not in use) OFF EEPREN DS1 ON PCEN PCVCCEN RAMEN FLSHEN ADIEN DUARTEN ADSA0 ADSA1 ADSA2 Direct control over the Pchip signal PCEN. When set to On, the internal Pchip PCMCIA interface is disabled. When set to ON, the board is powered unconditionally, with respect to PCMCIA host power. When set to OFF, the board is powered, only when the host connected to the board through the PCMCIA port, is turned on. 3 RAMEN When set to ON, on board SRAM is enabled. (1Mbyte space) ON 4 FLSHEN When set to ON, on board FLASH memory is enabled. ON Default setting ON ON 5 EEPREN When set to ON, on board EEPROM is enabled. ON 6 ADIEN When set to ON, ADI interface is enabled. ON 7 DUARTEN When set to ON, DUART MC68681 along with its RS232 port are enabled. ON 11

12 HARDWARE PREPARATION AND INSTALLATION nc ADI Port Address Selection (Dip-Switch DS1 switches 8-10) Each M68302FADS can have eight possible ADI port addresses, enabling up to eight M68302FADS boards to be connected to the same ADI card in a host computer. Address selection is done by setting switches 8, 9, 10 in DS1 Dip-Switch. Switch 10 is the most significant bit of the address while switch 8 is the least. A switch set to its "ON" state, stands for logical 0. The default setting is ADI address - 7. Table 2-2 describes the switch settings for each slave address: Table 2-2 ADI Address Selection ADDRESS Switch 10 Switch 9 Switch 8 0 ON ON ON 1 ON ON OFF 2 ON OFF ON 3 ON OFF OFF 4 OFF ON ON 5 OFF ON OFF 6 OFF OFF ON 7 OFF OFF OFF 12

13 nc. HARDWARE PREPARATION AND INSTALLATION DS2 DIP switch configuration The M68302FADS. FIGURE 2-4 Dip-Switch DS2 OFF DS2 ON 1 IOIS16 2 MODCLK 3 BUSW CHIPTYPE Table 2-3 Dip-Switch DS2 description. Switch Name Function Default 1 IOIS16 (Not in use) 2 MODCLK (Not in use) Set IOIS16 PCMCIA signal level. IOIS16, is not supported by the Pchip. When set to on, PCMCIA I/O transfers are 8 bits width. When set to off, PCMCIA I/O transfers, are 16 bits width. Select PLL multiplication factor when PLL is enabled. (See J1, J2 jumpers) ON - selects x4 multiplication factor and OFF - selects x401 for 32KHz crystal. 3 BUSW Must be OFF OFF 10 CHIPTYPE Must be ON ON = IMP ON ON 13

14 HARDWARE PREPARATION AND INSTALLATION nc. 2 4 INSTALLATION INSTRUCTIONS In order to operate the M68302FADS-ENA the user should connect the two boards, M68302FADS-ENA and M68302FADS together through P12,P9 and then configure the two boards, it can be installed according to the required working environment as follows: V Power Supply Connection for M68302FADS. The M68302FADS requires 2A max, power supply for operation. The ADS has 3.15A fuses on the +5V line. and it is protected against reverse connection of the power supply. Connect the +5V supply to connector P10 as shown below: FIGURE 2-5 P10: +5V Power Connector P10 on M68302FADS is a 3 terminals block power connector with power plug. The plug is designed to accept 14 to 22 AWG wires. It is recommended to use 14 to 18 AWG wires. To insure solid ground, two Gnd terminals are supplied. It is recommended to connect both Gnd wires to the common of the power supply, while VCC is connected with a single wire VCC 5V Gnd Gnd P10 ON M68302FADS +12V Power Supply Connection on the ENA for the AUI port. The M68302FADS-ENA requires 1A max for the AUI port. The ENA has 1A fuse on the 12V line and it is protected against reverse connection of the power supply. Connect the +12Vpower supply to connector P4 as shown below: FIGURE 2-6 P4+12V Power Connector for AUI port VPP 12V Gnd P4 on M68302FADS-ENA is a 2 terminals block power connector with power plug. The plug is designed to accept 14 to 22 AWG wires. It is recommended to use 14 to 18 AWG wires. 1 2 P4 ON ENA NOTE Since hardware applications can be connected to the M68302FADS-ENA using the expansion connectors P3 and P5, the additional power consumption should be taken into consideration when a power supply is connected to the M68302FADS-ENA. 14

15 nc. OPERATING INSTRUCTIONS CHAPTER 3 - OPERATING INSTRUCTIONS 3 1 INTRODUCTION This chapter provides necessary information to use the M68302FADS and the ENA in host-controlled and in a stand-alone configuration. This includes controls, indicators, memory map details, and software initialization of the boards. 3 2 CONTROLS AND INDICATORS ON THE M68302FADS The M68302FADS has the following switches and indicators NMI (Abort) Switch SW1 The NMI switch SW2 asserts level 7 interrupt to the processor. The switch signal is debounced, and It is not possible to disable it by software. The NMI (Abort) switch is normally used to abort program execution and return the debugger control RESET Switch SW2 The RESET switch SW2, resets all ADS devices and performs reset to the 302 processor. The switch signal is debounced, and it is not possible to disable it by software RUN indicator LD1 This yellow indicator is connected to the 302 processor address strobe (AS~) signal. It lit when AS~ is low (asserted) to indicate a bus activity HALT indicator LD2 This red indicator, lit whenever the 302 processor HALT~ pin is low (asserted) Power indicator LD4 This green indicator, lit when the board is powered. Please be aware that suppling 5V to P10 connector does not assure it is powered. When DIP switch DS2 switch number 2, is set to its off position, board power, is PCMCIA power dependent. (This option is for other type of M68XX302).The on board relay switches the power off, unless a 5V power is detected on the PCMCIA port. When DIP switch DS2 switch number 2, is set to its on position, the board is powered when 5V is supplied trough P10, unconditionally of PCMCIA port status J1 J2 J3 LD3 UNUSED JUMPERS AND LEDS ON THE M68302FADS 15

16 OPERATING INSTRUCTIONS nc. 3 3 CONTROL AND INDICATORS ON THE M68302FADS-ENA Ethernet TPJABB Indicator LD1 Red LED Ethernet TP Jabber indicator LD1 lights whenever a jabber condition is detected on the TP P1 port Ethernet TPPLR indicator LD2 Red LED Ethernet TP Polarity indicator LD2 lights if the wires connected to the receiver input of TP P1 port are reversed. The LED is lit by the EEST, and remains on when the EEST has automatically corrected for the reversed wires Ethernet TPLIL LD3 Yellow LED Ethernet Twisted Pair Link Integrity indicator LD3 lights to indicate good link integrity on the TP P1 port. The LED is off when the link integrity fails, or when the AUI port is selected Ethernet CLSN Indicator LD4 The red LED Ethernet Collision indicator LD4 blinks whenever a collision is detected in the AUI P2 port or the TP P1 port, or a jabber condition is detected in TP mode Ethernet RX Indicator LD5 The green LED Ethernet Receive indicator LD5 blinks whenever the EEST is receiving data from one of the Ethernet ports P1 or P Ethernet TX Indicator LD6 The green LED Ethernet Transmit indicator LD6 blinks whenever the EEST is transmitting data through one of the Ethernet ports P1 or P2. 16

17 nc. OPERATING INSTRUCTIONS RAS0-RAS1 J1 RAS0 - Enabled When the jumper is installed on pins 2-3, M68EN302 RAS0 is used for the DRAM. 1 RAS0-RAS1 JUMPER RAS1 - Enabled When the jumper is installed on pins 1-2, the EN302 RAS1 is used for the DRAM. RAS0-RAS1 JUMPER CPU - Enable CPU - Disable DISCPU Jumper J2 When the jumper is installed on pins 2-3, the CPU is enabled. When the jumper is installed on pins 1-2, the CPU is disabled. 1 DISCPU JUMPER DISCPU JUMPER 17

18 OPERATING INSTRUCTIONS nc TPSQEL - Twisted Pair Signal Quality Error Test Enable -J3 This pin can be driven constant to GND, VCC or controlled by PB7. Forcing TPSQEL to low enables testing of the internal TP collision detect circuitry after each transmit operation to the TP media. This function provides simulate collision to as match of the MC68160 collision detect circuity as possible without affecting the attached twisted pair channel. A normal SQE test results in a high logic state at the CLSN controller interface pin which begins 6 to 16-bit times after the last transition of a transmitted signal and continues for 5 to 15-bit times. TPSQEL- Input, Drive Low TPSQEL When the jumper J3 is installed on pins 2-3, The TPSQEL EEST input is constant connected to GND and enables testing of the internal TP collision detect circuitry after each transmit operation to the TP media. TPSQEL - Input, Drive High When the jumper is not installed on pins 1-2,nor 2-3 the The TPSQEL EEST input is constant connected to VCC and disable testing of the internal TP collision detected. TPSQEL - Input, Drive By PB(7) When the jumper is installed on pins 2-3, the The TPSQEL EEST input is controlled by The 68EN302 PB(7) pin. 1 TPSQEL TPSQEL 18

19 nc. OPERATING INSTRUCTIONS TPFULDL- Twisted Pair Full Duplex Mode select.- J4 This pin can be driven constant to GND, VCC or controlled by PB(6). Forcing this pin low simultaneous transmit and receive operation on the twisted pair port without an indicated collision. This pin is not to be asserted with LOOP as a test mode is enabled that disrupts normal operation. TPFULDL- Input, Drive Low TPFULDL When the jumper J4 is installed on pins 2-3, The TPFULDL EEST input is constant connected to GND it allow simultaneous transmit and receive on the twisted pair port without indicated collision. 1 TPFULDL - Input, Drive High When the jumper is not installed on pins 1-2,nor 2-3 the The TPFULDL EEST input is constant connected to VCC, it disable simultaneous transmit and receive on the twisted pair port without indicated collision. TPFULDL - Input, Drive By PB(6) When the jumper is installed on pins 1-2 the The TPFULDL EEST input is controlled by The EN302 PB(6) pin. TPFULDL TPFULDL 19

20 OPERATING INSTRUCTIONS nc TPAPCE - Twisted Pair Automatic Polarity Correction Enable - J5 This pin can be driven constant to GND, VCC or controlled by PB(8). When this pin is high, an automatic polarity correction is enabled and the MC68160 will internally correct for polarity fault on the receive circuit. Additionally, when TPAPCE is high the presence of polarity fault is indicated on TPPLR. TPAPCE- Input, Drive Low When the jumper J5 is installed on pins 2-3, The TPAPCE EEST input is constant connected to GND, it will disable automatic polarity correction. 1 TPAPCE TPAPCE - Input, Drive High When the jumper is not installed on pins 1-2,nor 2,3 the The TPAPCE EEST input is constant connected to VCC, it will enable automatic polarity correction and internally correct for a polarity fault on the receive circuit. TPAPCE - Input, Drive By PB(8) When the jumper is installed on pins 1-2, the The TPAPCE EEST input is controlled by The EN302 PB(8) pin. TPAPCE TPAPCE 20

21 nc. OPERATING INSTRUCTIONS TPEN - Twisted Pair Port Enable - J6 This pin can be driven constant to GND, VCC or controlled by PB(10).If APORT is low TPEN is an input which determines whenever the AUI port (TPEN low) or TP port (TPEN high) will be manually selected.if the AUI port is manually selected, the MC68160 will not produce link pulses for the TP port. If APORT is high, TPEN is an output which will indicate which port has been automatically selected by driving TPEN low (for AUI) or high (for TP). TPEN- Input, Drive Low When the jumper J6 is installed on pins 2-3, The TPEN EEST input is constant connected to GND through pull down resistor, and if APORT is low the AUI port is selected. If APORT is high TPEN will be driven by the EEST 1 TPEN TPEN - Input, Drive High When the jumper is not installed on pins 1-2 nor 2-3 the The TPEN EEST input is constant connected to VCC through pull up resistor, and if APORT is low the TP port is selected. If APORT is high TPEN will be driven by the EEST TPEN TPEN - Input, Drive By PB(10) TPEN When the jumper is installed on pins 1-2, the The TPEN EEST input is connected to The M68EN302 PB(10) pin. 21

22 OPERATING INSTRUCTIONS nc CS2 - Chip Select - J7 This pin can be driven constant to GND, VCC or controlled by PB(11). A low on this pin enable the EEST CS2- Input, Drive Low CS2 When the jumper J7 is installed on pins 2-3, The CS2 EEST input is constant connected to GND and (Enable the EEST). 1 CS2 - Input, Drive High When the jumper is not installed on pins 1-2,nor 2-3 the. The CS2 EEST input is constant connected to VCC and the EEST will be on standby Mode. CS2 - Input, Drive By PB(11) When the jumper is installed on pins 1-2, the The CS2 EEST input is controlled by The EN302 PB(11) pin. CS2 CS2 22

23 nc. OPERATING INSTRUCTIONS LOOP - Diagnostic LoopBack - J8 This pin can be driven constant to GND, VCC or controlled by PB(5). Asserting this function causes serial NRZ data at the TX input to be Manchester encoded and then looped back through the Manchester decoder, appearing at the RX output. This diagnostic loopback function operate independent of TP or AUI port connectivity or activity. Neither the TP nor AUI ports transmits data from the controller while diagnostic loopback is selected. Likewise, the controller interface receives data neither from the TP nor AUI receivers while in this mode. The polarity fault detection and link integrity functions are not inhibited by the diagnostic loopback mode. If otherwise enabled, they continue to function. If the twisted pair is selected, and TSQEL is driven to the low logic state, a collision detect pulls is delivered following each transmission to simulate the twisted pair SEQ test. LOOP- Input, Drive Low LOOP When the jumper J8 is installed on pins 2-3, The LOOP EEST input is constant connected to GND. and Loop back is disable. LOOP - Input, Drive High When the jumper is not installed on pins 1-2 nor 2-3 the. The LOOP EEST input is constant connected to VCC (assertion) and the loop back is enable. A serial NRZ data at the TX input to be Manchester encoded and then looped back through the Manchester decoder, appearing at the RX output. LOOP - Input, Drive By PB(5) When the jumper is installed on pins 1-2, the The LOOP EEST input is controlled by The EN302 PB(5) pin, the PB(5) enable or disable the Loop Back. 1 LOOP LOOP 23

24 OPERATING INSTRUCTIONS nc APORT -Automatic Port Selection Enable - J9 This pin can be driven constant to GND, VCC or controlled by PB(9). When high MC68160 will automatically select the TP or AUI port based on the presence or absence of valid link beats or frames at the TP receive input. If the AUI port is automatically selected the MC68160 will continue to produce link pulses for the TP port. Changing port requires approximately 1ms to allow the circuitry for the new port to resume normal operation. APORT- Input, Drive Low When the jumper J8 is installed on pins 2-3, The APORT EEST input is constant connected to GND. 1 APORT APORT - Input, Drive High When the jumper is not installed on pins 1-2 nor 2-3 the. The APORT EEST input is constant connected to VCC. The AUI or TP port is automatically selected. LOOP - Input, Drive By PB(9) When the jumper is installed on pins 1-2, the The APORT EEST input is controlled by The EN302 PB(9) pin. APORT APORT 24

25 nc. OPERATING INSTRUCTIONS 3 4 EN302 MEMORY MAP FIGURE 3-1 IMP memory map on this page, is one of two maps. After a cold or warm reset, the 302 processor s CS0, is automatically enabled for the first block of 8K bytes. In this page the 302 processor sees the first 8K bytes of the 1M bytes FLASH memory installed. No other space than those 8K, is available this time. At this point, the stack pointer and the program counter are fetched from Flash and the debugger starts. One of the debugger first tasks, is to enable the map shown in FIGURE 3-1. It is done by copying the code for the swap task, into the 302 processor s dual port Ram and jump to execute the code. The code redefines CS0, CS1 and CS2 to enable the map shown in FIGURE 3-1 and goes back to the debugger which has been moved due to the new map, to offset H. The swap task is executed from the dual port RAM, so it would not be interrupted by the swap. The swap is done, in order to map a RAM at the 302 processor vector table (start at $0), so the user would be able to change those vectors. (and not a FLASH at $0 - a must after reset) FIGURE 3-1 M68EN302 memory map FFFFFE FF000 6FF FFFFE FFFFE FFFFE FFFFE D15 D8 D7 D0 Reserved for MC68302 internal space and user applications. EN302 Internal Registers MC68681 DUART K byte EEPROM FFFFE ADI handshake ADI port data 1M byte FLASH memory FFFFFF FF001 6FF FFFFF FFFFF FFFFF FFFFF FFFFF FFFFE 0FFFFF K byte static RAM expansion memory FFFE 512K byte static RAM base memory 07FFFF Each FADS board comes with 1M byte of Flash memory (oriented as 512K words of 16 bits each) and a 512K bytes of static RAM (oriented as 256K words 16 bits each). The RAM can be expanded, on board to 25

26 OPERATING INSTRUCTIONS nc. a total of 1M bytes. ADI logic, DUART MC68681 and 2K byte EEPROM, occupies each 64K byte which is the minimum division available, by on board chip select logic. Each empty space in the map, is considered available for the user. Any of the on board resources, can be disabled, to free its memory allocation for the user. Please see Table 2-1 Dip-Switch DS1 Description on page

27 nc. OPERATING INSTRUCTIONS 3 5 The EN302 debugger. Each M68302FADS-ENA (connected to the M68302FADS) board, is installed with a debugger, resides on the first two sectors of FLASH memories, U6, U7. Each sector of AM29F040 device, is 64K bytes, thus a total of 128K bytes (1 sectors per FLASH), are allocated for the debugger. Those two sectors are protected by software against, accidental programming Debugger upgrade. The debugger supports an on board upgrade capabilities. A new debugger release, is programmed on board, without the need to take the FLASHes out of their sockets and without the need of a special programmer. Further instruction will be supplied, with each upgrade The debugger programming, of internal EN302 processor registers. The initialization done by the debugger to an internal 302 family processor registers, is writing to the base address register (BAR) and programming CS0, CS1 and CS2. The BAR is initialized, so the processor register block, resides starting from $ The MOBAR initialized to address $6FF000 CS0 is initiated for 1M bytes FLASH starting at H. CS1 is initiated for 1M bytes RAM (512K bytes actually installed) starting at H. CS2 is initiated for 30000H bytes starting at H. CS2 is used for the ADI, EEPROM and DUART. The internal division of this space, is done by an additional logic, outside the302 processor. 27

28 OPERATING INSTRUCTIONS nc. 3 6 Functional description FIGURE 3-2 HARDWARE BLOCK DIAGRAM AUI interface & connector Twisted pair interface & connector EN302 dedicated expansions connectors 2 SIMM 4M x 9Bit Motorola MC68160 (Socket) (EEST) ENA M68302FADS MC68EN302 Processor ADS compatible expansions connectors ADS expansion conn. 28

29 nc. OPERATING INSTRUCTIONS MC68EN302 - (Sheet 1) The EN302 is a version of the original MC IMP. In additional it has 16Bit Ethernet controller and DRAM controller. The Ethernet controller has a 16Bit interface, sits on the bus and provide complete IEEE compatibility. The programing module that is used is adopted from the standard programing module. The DRAM controller is adopted from the product.it is enhanced to support both parity and external bus master. The EN302 on the ENA is a 180 pin PGA package. The PGA package is intended primary for development tools and is used in the M68302FADS-ENA. The resisters R7,R8,R29,R30 on this page are used for internal testing MCM DRAM. (Sheet 2) On this sheet there are two MCM94000 which is a 36M dynamic random access memory (DRAM)module organized as 4,194,304x9Bits the module is 30-lead single-in-line memory module (SIMM) consisting of nine MCM54100A DRAM housed in 20/26 J-lead small outline packages (SOJ). The M68EN302 can be connected glue less to the DRAM modules. The on board DRAM is one bank, the EN302 can support two 16-bit wide banks. J1 is a jumper which can select one of the EN302 two bank select signals PA7-RAS0, PA12-RAS1. There are also parity bits DISCPU-PARITY0 (D8-D15), BUSW- PARITY1(D0-D7) The DRAM SIMM are not installed on the ENA Ethernet Controller (Sheet 3) This sheet consist of a Motorola MC68160 EEST device (U8 in sheet 3), and 6,J3-J8 jumpers for controlling the EEST control pins. The MC68160 provides two Ethernet interfaces, twisted-pair on P1 and AUI on P2. The LEDs LD1-LD6 are controlled by the EEST, and they provide indications about the status of the Ethernet ports activity Ethernet AUI Port Signal Description The AUI port connector P2 is a 15 pin, female, D-type connector as shown in FIGURE 3-3. FIGURE 3-3 Ethernet AUI Port Connector GND ACX+ ATX+ GND ARX+ GND N.C. GND ACX- 10 ATX- 11 GND 12 ARX V 14 GND 15 N.C. 29

30 OPERATING INSTRUCTIONS nc. The list below describes the port signals.the directions I, O, and I/O are relative to the M68302FADS- ENA board. (I.E. I means input to the EN302) ACX+ (I) - Collision Input (positive). ATX+ (O) - Transmit Data (positive). ARX+ (I) - Receive Data (positive). ACX- (I) - Collision Input (negative). ATX- (O) - Transmit Data (negative). ARX- (I) - Receive Data (negative). +12V (O) - +12V power supply from P Ethernet Twisted-Pair Port Signal Description The twisted-pair port connector P1 is a 8 pin, RJ-45 connector as shown infigure 3-4. FIGURE 3-4 Ethernet Twisted-Pair Port Connector TPTX+ 1 TPTX- 2 TPRX+ 3 N.C. 4 N.C. 5 TPRX- N.C. N.C. The list below describes the port signals.the directions I, O, and I/O are relative to the M68302FADS- ENA board. (I.E. I means input to the EN302) TPTX+ (O) - Transmit Data (positive). TPTX- (O) - Transmit Data (negative). TPRX+ (I) - Receive Data (positive). TPRX- (I) - Receive Data (negative) P12,P9 CONNECTORS (Sheets 4,5) These two male connectors contain all the EN302 pins except of the Ethernet and the DRAM pins. P12 contains the three EN302 s SCC,P9 contain the Address, data, control signals and portb signals. Through these connectors the EN302 operate and control all the peripheral on the FADS board. NOTE. Signal EXTORCKO (Extal Or CLKO) connected on P9 pin C25 is connected to CLKO of the 302FADS P3,P5 ARE 96PIN FEMALE EXPANSION CONNECTOR (Sheet 6,7) These two female Din connectors contain of all the M68EN302 pins for the user hardware uses Clock Circuit Crystal or Clock Oscillator (Sheet 8) The M68EN302 is clocked by clock oscillator it is possible to drive the clock by crystal, in order to do so the user should remove R18 and add C28,C30,XT2,R19,R28 to the board. 30

31 nc. SUPPORT INFORMATION CHAPTER 4 - SUPPORT INFORMATION 4 1 INTRODUCTION This chapter provides the interconnection signals, parts list, and schematic diagrams of the M68302FADS- ENA board. 4 2 INTERCONNECT SIGNALS The M68302FADS-ENA board interconnects with external devices through the following connectors, listed in Table Table 4-1 Board interconnection Reference Type Function P1 8 pin, female RJ-45 connector TP port P2 15 pin, female D type connector AUI port P3, P5 96 pin, male Din Type connector expansion port connectors P4 2 pin male, male connector 12V Power Supply Connector For AUI Connector P9,P12 96 pin, female Din type connector ENA to connect to M68302FADS Connector Connector P1 Interconnect Signals Connector P1 is 8 pin, RJ-45 connector. It is the twisted-pair Ethernet port of the M68302FADS-ENA board. Table 4-2 describes the P1 connector signals. Table 4-2 Connector P1Table 2-4 Interconnect Signals Pin No. Signal Name Description 1 TPTX+ Twisted-Pair Transmit Data positive output from the ENA. 2 TPTX- Twisted-Pair Transmit Data negative output from the ENA. 3 TPRX+ Twisted-Pair Receive Data positive input to the ENA. 4 - Not connected 5 - Not connected 6 TPRX- Twisted-Pair Receive Data negative input to the ENA. 7 - Not connected 8 - Not connected 31

32 SUPPORT INFORMATION nc Connector P2 Interconnect Signals Connector P2 is 15 pin, female D type connector. It is the AUI Ethernet port of the M68302FADS-ENA board. Table 4-2 describes the P2 connector signals. Table 4-3 Connector P2 Interconnect Signals Pin No. Signal Name Description 1 GND Ground signal of the ENA. 2 ACX+ Collision detect positive input to the ENA. 3 ATX+ Transmit Data positive output from the ENA. 4 GND Ground signal of the ENA. 5 ARX+ Receive Data positive input to the ENA. 6 GND Ground signal of the ENA. 7 - Not connected 8 GND Ground signal of the ENA. 9 ACX- Collision detect negative input to the ENA. 10 ATX- Transmit Data negative output from the ENA. 11 GND Ground signal of the M68360QUADS. 12 ARX- Receive Data negative input to the ENA. 13 VPP +12V power supply from the ENA. 14 GND Ground signal of the ENA Not connected Connector P3 interconnect signals P3 is a 3 row, 96 pin female DIN connector. Processor signals, are directly routed to P3 and P5 connectors, for user hardware applications. P3 connector signals, are listed in Table 4-4. Table 4-4 Connector P3 interconnect signals Pin NO Signal name Description A1 VCC Board common +5V supply A2 VCC Board common +5V supply A3 GND Board common ground A4 PB0 port B bit 0 A5 PB1 port B bit 1 A6 PB2 port B bit 2 A7 PB3 port B bit 3 A8 PB4 port B bit 4 A9 PB5 port B bit 5 A10 PB6 port B bit 6 A11 PB7 port B bit 7 A12 PB8 port B bit 8 A13 PB9 port B bit 9 A14 PB10 port B bit 10 A15 PB11 port B bit 11 32

33 nc. SUPPORT INFORMATION Table 4-4 Connector P3 interconnect signals Pin NO Signal name Description A16 GND Board common ground A17 TMS Jtag pin A18 Not connected A19 TCK Jtag pin A20 Not connected A21 TRST~ Jtag pin A22 TDO Jtag pin A23 TDI Jtag pin A24 GND Board common ground A25 GND Board common ground A26 RXD1 SCC1 receive data A27 TXD1 SCC1 transmit data A28 CD1~ SCC1 carrier detect A29 CTS1~ SCC1 clear to send A30 RTS1~ SCC1 request to send A31 GND Board common ground A32 GND Board common ground B1 VCC Board common +5V supply B2 EXTNMI~ external level 7 interrupt source B3 GND Board common ground B4 TX Ethernet Transmit Data B5 Not connected B6 TCLK Ethernet Transmit Clock B7 Not connected B8 RCLK Ethernet Receive Clock B9 GND Board common ground B10 CLSN Ethernet Collision Signal. B11 Not connected B12 TENA Ethernet Transmit Enable Input Signal. B13 GND Board common ground B14 PARITYE~ DRAM Paritye signal B15 B16 TEST302 Factory test pin B17 GND Board common ground B18 Not connected B19 Not connected B20 Not connected B21 GND Board common ground B22 RX Ethernet Receive Data Signal B23 RENA Ethernet Receive Enable Output. 33

34 SUPPORT INFORMATION nc. Table 4-4 Connector P3 interconnect signals Pin NO Signal name Description B24 GND Board common ground B25 DISCPU disable CPU B26 GND Board common ground B27 GND Board common ground B28 GND Board common ground B29 GND Board common ground B30 GND Board common ground B31 VCC Board common +5V supply B32 VCC Board common +5V supply C1 VCC Board common +5V supply C2 GND Board common ground C3 GND Board common ground C4 PA0 port A bit 0 C5 PA1 port A bit 1 C6 PA2 port A bit 2 C7 PA3 port A bit 3 C8 PA4 port A bit 4 C9 PA5 port A bit 5 C10 PA6 port A bit 6 C11 PA7 port A bit 7 C12 PA8 port A bit 8 C13 PA9 port A bit 9 C14 PA10 port A bit 10 C15 PA11 port A bit 11 C16 PA12 port A bit 12 C17 PA13 port A bit 13 C18 PA14 port A bit 14 C19 PA15 port A bit 15 C20 GND Board common ground C21 BRG1 baud rate generator 1 C22 GND Board common ground C23 RCLK1 SCC 1 receive clock C24 Not connected C25 TCLK1 SCC 1 transmit clock C26 GND Board common ground C27 CTS3~ SCC 3 clear to send C28 RTS3~ SCC 3 request to send C29 CD3 SCC 3 carrier detect C30 GND Board common ground C31 GND Board common ground 34

35 nc. SUPPORT INFORMATION Table 4-4 Connector P3 interconnect signals Pin NO Signal name Description C32 VCC board common +5V supply Connector P4 Interconnect Signals Connector P4 is 2 pin connector for 12v power supply for AUI. The connector is supplied with 2 pin plug for convenient connection to the power supply. Table 4-2 describes the P4 connector signals. Table 4-5 Connector P4 Interconnect Signals Pin No. Signal Name Description 1 VPP +12V connection to the power supply. 2 GND Ground connection to the power supply Connector P5 interconnect signals P5 is a 3 row, 96 pin female DIN connector. All processors signals, are routed directly to P3 and P5, for user HW application. P5 signals are listed in Table 4-6. Table 4-6 Connector P5 interconnect signals Pin NO Signal name Description A1 GND Board common ground A2 GND Board common ground A3 GND Board common ground A4 A7 address line bit 7 A5 A4 address line bit 4 A6 A9 address line bit 9 A7 A14 address line bit 14 A8 A19 address line bit 19 A9 A16 address line bit 16 A10 A21 address line bit 21 A11 FC2 function code bit 2 A12 Not connected A13 CS3~ chip select 3 A14 PB3 port B bit 3 A15 IAC internal access A16 GND common A17 PB1 port B bit 1 A18 FC1 function code bit 1 A19 D14 data bit 14 A20 D11 data bit 11 A21 R/W~ output enable/read write 35

36 SUPPORT INFORMATION nc. Table 4-6 Connector P5 interconnect signals Pin NO Signal name Description A22 D6 data bit 6 A23 DTACK~ data transfer acknowledge A24 BERR~ bus error A25 IPL1~ interrupt priority level 1 A26 IPL2~ interrupt priority level 1 A27 PA15 port A bit 15 A28 BGACK~ bus grant acknowledge A29 FRZ~ freeze A30 PA13 port A bit 13 A31 BG~ bus grant A32 VCC board common +5V supply B1 GND Board common ground B2 A1 address bit 1 B3 GND Board common ground B4 A2 address bit 2 B5 A5 address bit 5 B6 A10 address bit 10 B7 A15 address bit 15 B8 A12 address bit 12 B9 A17 address bit 17 B10 A22 address bit 22 B11 FC0 function code 0 B12 CS0~ chip select bit 0 B13 PB11 port B bit 11 B14 PB10 port B bit 10 B15 PB2 port B bit 2 B16 PB8 port B bit 8 B17 PB4 port B bit 4 B18 UDS~ upper data strobe B19 D10 data bit 10 B20 D13 data bit 13 B21 AS~ address strobe B22 D9 data bit 9 B23 D2 data bit 2 B24 AVEC~ auto vector B25 IPL0~ interrupt priority 0 B26 BR~ bus request B27 EXTAL EN302 input clock B28 RST~ reset B29 PA12 port A bit 12 36

37 nc. SUPPORT INFORMATION Table 4-6 Connector P5 interconnect signals Pin NO Signal name Description B30 D3 data bit 3 B31 BUSW EN302 Bus width B32 VCC board common +5V supply C1 GND board common ground C2 GND board common ground C3 GND board C4 A3 address bit 3 C5 A6 address bit 6 C6 A11 address bit 11 C7 A8 address bit 8 C8 A13 address bit 13 C9 A18 address bit 18 C10 A23 address bit 23 C11 A20 address bit 20 C12 CS1~ chip select 1 C13 CS2~ chip select 2 C14 PB6 port B bit 6 C15 PB5 port B bit 5 C16 PB7 port B bit 7 C17 PB9 port B bit 9 C18 PB0 port B bit 0 C19 D15 data bit 15 C20 D12 data bit 12 C21 LDS lower data strobe C22 D8 data bit 8 C23 D7 data bit 7 C24 D1 data bit 1 C25 CLKO EN302 clockout C26 D5 data bit 5 C27 Not connected C28 D4 data bit 4 C29 D0 data bit 0 C30 HALT~ halt control C31 PA14 port A bit 14 C32 VCC board common +5V supply 37

38 SUPPORT INFORMATION nc Connector P9 interconnect signals P9 is a 3 row, 96 pin male DIN connector. Most of the processors signals, are routed directly to P9 and P12, for Connecting to the M68302FADS. P9 signals are listed in Table 4-6. Table 4-7 Connector P9 interconnect signals Pin NO Signal name Description A1 GND Board common ground A2 GND Board common ground A3 GND Board common ground A4 A7 address line bit 7 A5 A4 address line bit 4 A6 A9 address line bit 9 A7 A14 address line bit 14 A8 A19 address line bit 19 A9 A16 address line bit 16 A10 A21 address line bit 21 A11 FC2 function code bit 2 A12 Not connected A13 CS3~ chip select 3 A14 PB3 port B bit 3 A15 IAC internal access A16 GND common A17 PB1 port B bit 1 A18 FC1 function code bit 1 A19 D14 data bit 14 A20 D11 data bit 11 A21 R/W~ read write A22 D6 data bit 6 A23 DTACK~ data transfer acknowledge A24 BERR~ bus error A25 IPL1~ interrupt priority level 1 A26 IPL2~ interrupt priority level 1 A27 PA15 port A bit 15 A28 BGACK~ bus grant acknowledge A29 FRZ~ freeze A30 PA13 port A bit 13 A31 BG~ bus grant A32 VCC board common +5V supply B1 GND Board common ground B2 A1 address bit 1 B3 GND Board common ground B4 A2 address bit 2 B5 A5 address bit 5 38

39 nc. SUPPORT INFORMATION Table 4-7 Connector P9 interconnect signals Pin NO Signal name Description B6 A10 address bit 10 B7 A15 address bit 15 B8 A12 address bit 12 B9 A17 address bit 17 B10 A22 address bit 22 B11 FC0 function code 0 B12 CS0~ chip select bit 0 B13 PB11 port B bit 11 B14 PB10 port B bit 10 B15 PB2 port B bit 2 B16 PB8 port B bit 8 B17 PB4 port B bit 4 B18 UDS~ upper data strobe B19 D10 data bit 10 B20 D13 data bit 13 B21 AS~ address strobe B22 D9 data bit 9 B23 D2 data bit 2 B24 AVEC~ auto vector B25 IPL0~ interrupt priority 0 B26 BR~ bus request B27 Not connected B28 RST~ reset B29 PA12 port A bit 12 B30 D3 data bit 3 B31 Not connected B32 VCC board common +5V supply C1 GND board common ground C2 GND board common ground C3 GND board C4 A3 address bit 3 C5 A6 address bit 6 C6 A11 address bit 11 C7 A8 address bit 8 C8 A13 address bit 13 C9 A18 address bit 18 C10 A23 address bit 23 C11 A20 address bit 20 C12 CS1~ chip select 1 C13 CS2~ chip select 2 39

40 SUPPORT INFORMATION nc. Table 4-7 Connector P9 interconnect signals Pin NO Signal name Description C14 PB6 port B bit 6 C15 PB5 port B bit 5 C16 PB7 port B bit 7 C17 PB9 port B bit 9 C18 PB0 port B bit 0 C19 D15 data bit 15 C20 D12 data bit 12 C21 LDS write enable low/lower data strobe C22 D8 data bit 8 C23 D7 data bit 7 C24 D1 data bit 1 C25 EXTORCKO clock or extal out C26 D5 data bit 5 C27 Not connected C28 D4 data bit 4 C29 D0 data bit 0 C30 HALT~ halt control C31 PA14 port A bit 14 C32 VCC board common +5V supply Connector P12 Interconnect Signals P12 is a 3 row, 96 pin, male DIN connector. This connector, together with P9, has all processor pins for easy interfacing to the M68302FADS. P12 signals, are listed in Table 4-8 Table 4-8 Connector P12 interconnect signals Pin NO Signal name Description A1 VCC Board common power A2 VCC Board common power A3 GND Board common ground A4 IPB0 port B bit 0 A5 IPB1 port B bit 1 A6 IPB2 port B bit 2 A7 IPB3 port B bit 3 A8 IPB4 port B bit 4 A9 IPB5 port B bit 5 A10 IPB6 port B bit 6 A11 IPB7 port B bit 7 A12 IPB8 port B bit 8 A13 IPB9 port B bit 9 A14 IPB10 port B bit 10 40

41 nc. SUPPORT INFORMATION Table 4-8 Connector P12 interconnect signals Pin NO Signal name Description A15 IPB11 port B bit 11 A16 GND Board common ground A17 Not Connected A18 Not Connected A19 Not Connected A20 Not Connected A21 Not Connected A22 Not Connected A23 Not Connected A24 GND Board common ground A25 GND Board common ground A26 RXD1 SCC1 receive data input A27 TXD1 SCC1 transmit data output A28 CD1~ SCC1 carrier detect A29 CTS1~ SCC1 clear to send A30 RTS1~ SCC1 request to sent A31 GND Board common ground A32 GND Board common ground B1 VCC Board common power B2 EXTNMI~ External Nmi B3 GND Board common ground B4 Not Connected B5 Not Connected B6 Not Connected B7 Not Connected B8 No Connected B9 GND Board common ground B10 Not Connected B11 Not Connected B12 Not Connected B13 GND Board common ground B14 Not Connected B15 Not Connected B16 Not Connected B17 GND Board common ground B18 Not Connected B19 Not Connected B20 Not Connected B21 GND Board common ground B22 41

42 SUPPORT INFORMATION nc. Table 4-8 Connector P12 interconnect signals Pin NO Signal name Description B23 B24 GND Board common ground B25 B26 GND Board common ground B27 GND Board common ground B28 GND Board common ground B29 GND Board common ground B30 GND Board common ground B31 VCC Board common power B32 VCC Board common power C1 VCC Board common power C2 GND Board common ground C3 GND Board common ground C4 PA0 port A bit 0 C5 PA1 port A bit 1 C6 PA2 port A bit 2 C7 PA3 port A bit 3 C8 PA4 port A bit 4 C9 PA5 port A bit 5 C10 PA6 port A bit 6 C11 PA7 port A bit 7 C12 PA8 port A bit 8 C13 PA9 port A bit 9 C14 PA10 port A bit 10 C15 PA11 port A bit 11 C16 PA12 port A bit 12 C17 PA13 port A bit 13 C18 PA14 port A bit 14 C19 PA15 port A bit 15 C20 GND Board common ground C21 BRG1~ baud rate generator 1 output C22 GND Board common ground C23 RCLK1 SCC 1 receive clock C24 C25 TCLK1 SCC 1 receive clock C26 GND Board common ground C27 CTS3~ SCC3 clear to send C28 RTS3~ SCC3 request to send C29 CD3~ SCC 3 carrier detect C30 GND Board common ground 42

43 nc. SUPPORT INFORMATION Table 4-8 Connector P12 interconnect signals Pin NO Signal name Description C31 GND Board common ground C32 VCC Board common ground 43

44 SUPPORT INFORMATION nc. The table below contain the M68302FADS-ENA part list. Table M69302FADS-ENA Part List Reference PartNO/Value Manufacture Total C1,C29 100uF/25V Nippon 2 C2,C3,C4,C5,C6,C7,C8,C9,C10,C11, C12,C13,C14,C15,C16,C17,C18,C19,C21,C22,C31,C32,C33 0.1uF 25 C26,C27 (SMD 1206) C20,C25 (SMD 1206) 68PF 2 C23 (SMD 1206) 0.039UF 1 C24 (SMD 1210) 3900PF 1 C28,C30 (SMD 1206) 10pF 2 D1 MBRD620CT Motorola 1 D2 1SMC12AT3 Motorola 1 FU1 FUSE - 1A 1 J1,J2,J3,J4,J5,J6,J7,J8,J9 3 Pin Jumper 9 J10,J11 2 Pin Jumper 2 LED1,LED2,LED4 (SMD 1210) 3 LED3 (SMD 1210) 1 LED5,LED6 (SMD 1210) 2 P /2 MOLEX 1 P2 D CONN 15Pin KCC-DN15SRCZ Keltron 1 P3,P5 96DIN CONN female Elco 2 P9,P12 96DIN CONN male Elco 2 P4 8113S wieland bamberg 1 R1 (SMD 1206) 240 ohm 1 R2,R3,R4,R5,R6 (SMD 1206) 330 ohm 5 R28 not mounted (SMD 1206) 330 ohm 1 R7,R10 not mounted (SMD 1206) 1K ohm 2 R9,R30,R33 (SMD 1206) 0ohm 3 R8,R11,R29 not mounted (SMD 1206) 0ohm 3 R12,R14 (SMD 1206) 39.1 ohm 2 R13,R16,R31 (SMD 1206) 100 ohm 3 R15 (SMD 1206) 10K ohm 1 R17,R20,R21,R32 (SMD 1206) 4.7K ohm 4 R18 (SMD 1206) 0 ohm 1 R19 not mounted (SMD 1206) 470K ohm 1 R22 (SMD 1206) 2K ohm 1 R23 (SMD 1206) 294 ohm 1 R24,R25,R26,R27 (SMD 1206) 39 ohm 4 R34,R35 (SMD 1206) 200 ohm 2 U1,U2 (not populated) MCM94000 Motorola 2 44

45 nc. SUPPORT INFORMATION Table M69302FADS-ENA Part List Reference PartNO/Value Manufacture Total U3 PE68026 PULSE 1 U4 40MHz 1 U5 74ACT74 Motorola 1 U6 MC68EN302RC Motorola 1 U RN14BUS 1 U8 MC68160 Motorola 1 U9 PE64503 PULSE 1 XT1 20MHz 1 XT2 (not populated) 20MHz 1 45