Evaluating the Impact of Transactional Characteristics on the Performance of Transactional Memory Applications

Transcription

1 Evaluating the Impact of Transactional Characteristics on the Performance of Transactional Memory Applications Fernando Rui, Márcio Castro, Dalvan Griebler, Luiz Gustavo Fernandes Pontifícia Universidade Católica do Rio Grande do Sul - PUCRS - GMAP Universidade Federal do Rio Grande do Sul - UFRGS - INF February / 6

2 / 6 Summary Introduction Methodology Performance Evaluation Conclusions References

3 / 6 Introduction Motivation Multi-core Applications are not embarrassingly parallel Traditional synchronization structures (locks, mutexes and semaphores) Low-level mechanisms Cause Blocking Hard to manage Vulnerable to failures and faults

4 / 6 Introduction Transactional Memory (TM) High-level abstraction Allows to write parallel code as transactions In runtime detect conflicts and solve them

5 / 6 Introduction Challenge of TM systems What kind of applications can really take advantage of TM? Why some TM applications present low performance? Contributions of this research Performance evaluation of the state-of-art STM systems and applications Extend the analysis of [], including the RSTM [] system We find out characteristics that affect the performance TM We identify bottlenecks of TM App. that limit their scalability We show possible improvements to achieve better performance.

6 6 / 6 Methodology Comparative Analysis Four state-of-the-art STM systems using the Stanford Transactional Applications for Multi-Processing (STAMP) benchmark []; Evaluation of STM systems using EigenBench []; We evaluate the impact of certain transactional characteristics using EigenBench. Environment of Tests All experiments were performed on a Dell PowerEdge R6 machine with two quad-core Intel Xeon E.7 GHz processors with 8MB of L cache and 6GB of shared memory; All results are arithmetic means of at least runs to guarantee a confidence level of 9%.

7 7 / 6 STM Systems Using STAMP Benchmark STM Systems Transactional Locking (TL) []: second version of the original TL; TinySTM []: uses shared counter as clock to control the conflicts between transactions and locks to protect shared memory locations; SwissTM [6]: its innovations is the hybrid conflict detection scheme; Rochester Software Transactional Memory (RSTM) []: reduces cache misses by employing a single level of indirection to access shared objects.

8 STM Systems Using STAMP Benchmark Performance Evaluation SwissTM RSTM Speedups bayes genome intruder kmeans labyrinth TinySTM ssca vacation yada bayes genome intruder kmeans labyrinth TL ssca vacation yada bayes genome intruder kmeans labyrinth Legend ssca vacation yada Applications cores cores 8 cores bayes genome intruder kmeans labyrinth ssca vacation yada 8 / 6

9 9 / 6 SwissTM vs. RSTM using EigenBench Set-up: STM systems which presented better performance; STAMP applications with poor (ssca), medium (intruder and vacation) and good (labyrinth and genome) scalability; The evaluation is based on speedup and aborts per commit (ApC). EigenBench Input Parameters Table: Applications characteristics from STAMP benchmark Characteristic ssca intruder vacation labyrinth genome Working-set Size MB MB 6 MB 6 MB MB Transactional Lenght Pollution % % % % % Temporal Locality Contention.% %.% %.% Predominance Low Low High Low High Density High High High Low High

10 SwissTM vs. RSTM using EigenBenach (Cont.) Performance Evaluation SwissTM Speedups genome intruder labyrinth ssca Applications vacation Aborts per commit 6% % % % 8% 6% % % % 8 Number of cores RSTM Legend Speedups genome intruder labyrinth ssca Applications cores cores 8 cores vacation 6% % % % % % % Legend Aborts per commit 8 Number of cores genome intruder labyrinth ssca vacation / 6

11 / 6 SwissTM vs. RSTM using EigenBenach (Cont.) Findings TM applications that use large amounts of memory did not present good performance, since STM systems need to keep track of much more data to detect conflicts; The variation in terms of transaction lengths during the execution is not well treated by most of the STM systems; Low degrees of predominance and density help TM applications to perform better; High levels of ApC generally limit the performance of TM applications.

12 / 6 Evaluating the Impact of Transactional Characteristics Genome - Transactional Length Intruder - Temporal Locality Speedups Original V V V V Ssca - Working-set Size Original V V V V Vacation - Working-set Size Original V V V V Versions Original V V V V Legend cores cores 8 cores

13 / 6 Conclusions About this paper Some Characteristics drive the performance of TM applications; Applications must be analysed carefully to identify relevant characteristics; Future Opportunities We intend to extend this work using some tracing mechanisms as proposed in [7]; We intend to study the impact of the TM characteristics on the performance of TM applications when executed on a real HTM processor such as the Intel Haswell.

14 References I Sungpack Hong et al. Eigenbench: A Simple Exploration Tool for Orthogonal TM Characteristics. In IEEE International Symposium on Workload Characterization (IISWC), pages, Washington, USA,. IEEE Computer Society. Virendra J. Marathe, Michael F. Spear, Christopher Heriot, Athul Acharya, David Eisenstat, William N. Scherer III, and Michael L. Scott. Lowering the Overhead of Nonbacterial Software Transactional Memory. In ACM SIGPLAN Workshop on Transactional Computing. Jun 6. Cao Minh et al. STAMP: Stanford Transactional Applications for Multi-Processing. In IEEE International Symposium on Workload Characterization (IISWC), pages 6, Seattle, USA, 8. IEEE Computer Society. Dave Dice et al. Transactional Locking II. In International Symposium on Distributed Computing (DISC), pages 9 8, 6. Pascal Felber, Christof Fetzer, and Torvald Riegel. Dynamic Performance Tuning of Word-based Software Transactional Memory. In Symposium on Principles and Practice of Parallel Programming (PPoPP), pages 7 6, Salt Lake City, USA, 8. ACM. Aleksandar Dragojević, Rachid Guerraoui, and Michal Kapalka. Stretching Transactional Memory. In Programming Language Design and Implementation (PLDI), pages 6, 9. / 6

15 References II Márcio Castro et al. Analysis and Tracing of Applications Based on Software Transactional Memory on Multicore Architectures. In Euromicro International Conference on Parallel, Distributed and Network-Based Computing (PDP), pages IEEE Computer Society,. / 6

16 Evaluating the Impact of Transactional Characteristics on the Performance of Transactional Memory Applications Fernando Rui, Márcio Castro, Dalvan Griebler, Luiz Gustavo Fernandes Pontifícia Universidade Católica do Rio Grande do Sul - PUCRS - GMAP Universidade Federal do Rio Grande do Sul - UFRGS - INF February 6 / 6