Work Report: Lessons learned on RTM

Transcription

1 Work Report: Lessons learned on RTM Sylvain Genevès IPADS September 5, 2013 Sylvain Genevès Transactionnal Memory in commodity hardware 1 / 25

2 Topic Context Intel launches Restricted Transactional Memory (RTM) on commodity architecture Focused on: Try to characterize RTM Which tools could ease the use of RTM? Sylvain Genevès Transactionnal Memory in commodity hardware 2 / 25

3 Restricted Transactionnal Memory Goals: Best-effort mechanism to improve fast-paths Simple interface to define critical sections Intel RTM API (Intel [2013]): XBEGIN XEND XABORT XTEST Programmer needs to provide fallback handler Lifecycle: Critical sections are executed optimistically Check for conflicts using cache coherency protocol Commited to global memory only upon validation Aborted and Rollbacked otherwise Sylvain Genevès Transactionnal Memory in commodity hardware 3 / 25

4 Our Objectives Main questions How to characterize RTM? Impact of RTM on applications? How to precisely pinpoint data conflict? Provide tools to characterize and profile RTM We first discover implementation-dependent RTM features Study RTM behavior on standard applications Provide facilities to help profile and debug RTM applications Sylvain Genevès Transactionnal Memory in commodity hardware 4 / 25

5 Outline 1 Part 1: Characteristics 2 Part 2: STAMP-RTM 3 Part 3: Profiling RTM conflicts 4 Conclusions Sylvain Genevès Transactionnal Memory in commodity hardware 5 / 25

6 Interactions between RTM and non-rtm code Strong atomicity Non-RTM code can conflict with RTM (when they access the same data) Thread 1 Thread 2 no TSX TSX R/W Abort Time Running Sylvain Genevès Transactionnal Memory in commodity hardware 6 / 25

7 RTM capacity Read/write sets Determines max TX working set Write set tracked in L1 cache Private Bloom filter structure to track read set Write set size is L1 cache capacity (32KB) Read set size 10 * write set size Sylvain Genevès Transactionnal Memory in commodity hardware 7 / 25

8 Read/Write sets competition RTM and HyperThreading Read and Write sets are tracked per core L1 cache is shared among hardware threads Sylvain Genevès Transactionnal Memory in commodity hardware 8 / 25

9 Other characteristics Nesting transactions RTM allows simple nesting (max depth=7 on Haswell) Only the outermost transaction aborts or commits Illegal instructions in RTM (syscalls, debug, ring transitions,...) Most interrupts trigger RTM aborts RTM is a best-effort mechanism Sylvain Genevès Transactionnal Memory in commodity hardware 9 / 25

10 Outline 1 Part 1: Characteristics 2 Part 2: STAMP-RTM STAMP Introduction Evaluation 3 Part 3: Profiling RTM conflicts 4 Conclusions Sylvain Genevès Transactionnal Memory in commodity hardware 10 / 25

11 Outline 1 Part 1: Characteristics 2 Part 2: STAMP-RTM STAMP Introduction Evaluation 3 Part 3: Profiling RTM conflicts 4 Conclusions Sylvain Genevès Transactionnal Memory in commodity hardware 11 / 25

12 STAMP benchmark suite (Cao Minh et al. [2008]) 8 different applications: Bayes (machine learning) Genome (bioinformatics) Intruder (security) Vacation (online processing) Kmeans (data mining) Labyrinth (engineering) Ssca2 (scientific) Yada (scientific) All of them use transactionnal memory Sylvain Genevès Transactionnal Memory in commodity hardware 12 / 25

13 Work done Added support for RTM in STAMP Only modified the transaction layer, not the applications Policy: Each transaction tries RTM twice, then fallback Mutex-protected fallback handler Put the lock in the RTM read set Gather abort statistics Sylvain Genevès Transactionnal Memory in commodity hardware 13 / 25

14 Outline 1 Part 1: Characteristics 2 Part 2: STAMP-RTM STAMP Introduction Evaluation 3 Part 3: Profiling RTM conflicts 4 Conclusions Sylvain Genevès Transactionnal Memory in commodity hardware 14 / 25

15 STAMP-RTM Speedup 5.00 Speedup of STAMP-RTM 4.00 Speedup bayes genome intruder kmeans (low) kmeans (high) labyrinth ssca2 vacation (low) vacation (high) yada number of threads Sylvain Genevès Transactionnal Memory in commodity hardware 15 / 25

16 Performances Only 2 applications scale: Kmeans ans Ssca2 8 threads uses HyperThreading, does not allow linear scaling with RTM Labyrinth Uses only 1 thread, regardless of its arguments (Most likely a bug) Sylvain Genevès Transactionnal Memory in commodity hardware 16 / 25

17 Performance analysis Negative scaling Yada, vacation and genome perform best at 1 core Intruder and Bayes perform best at 2 cores Main issue: contention on the fallback lock Abort rate for those applications is very high: from 40% to 80% (at 8 threads) First source of abort is conflict aborts Followed by capacity aborts Aborts due to interrupts are relatively low Sylvain Genevès Transactionnal Memory in commodity hardware 17 / 25

18 Outline 1 Part 1: Characteristics 2 Part 2: STAMP-RTM 3 Part 3: Profiling RTM conflicts 4 Conclusions Sylvain Genevès Transactionnal Memory in commodity hardware 18 / 25

19 Aborts decrease performance Conflicts will cause aborts Conflict cause is hard to determine Transactionnal rollback doesn t help To understand conflict abort cause One needs: Killer IP (not necessarily inside RTM) Killed IP Data accessed We intend to provide those using Intel PEBS a and DataLA b facilities a Precise Event-Based Sampling b Data Linear Address Sylvain Genevès Transactionnal Memory in commodity hardware 19 / 25

20 Detecting sharing Existing tools don t provide enough information PEBS on RTM abort provides: Instruction Pointer (can be unprecise if abort is asynchronous) Abort reason (conflict, capacity,...) Pinpointing a whole transaction is not precise enough Sylvain Genevès Transactionnal Memory in commodity hardware 20 / 25

21 Detecting sharing By monitoring cache coherency MEM LOAD UOPS L3 HIT RETIRED.XSNP HITM Retired load uops which data sources were HitM responses from shared L3 Unexpectedly has some TSX information! (undocumented feature) IP (inside and outside of RTM) Address of accessed data We monitor both Cache Coherency and Abort events simultaneously Our tool: Get the maximum information we can Bypass Perf s standard ouput (perf report) Use the raw PEBS record (provided by Andy Kleen s pmu-tools) Parse&compile the results (KillerIP, KilledIP, Data, AbortInfo) Sylvain Genevès Transactionnal Memory in commodity hardware 21 / 25

22 Outline 1 Part 1: Characteristics 2 Part 2: STAMP-RTM 3 Part 3: Profiling RTM conflicts 4 Conclusions Sylvain Genevès Transactionnal Memory in commodity hardware 22 / 25

23 Summary HTM goes mainstream RTM is now present on commodity hardware We studied several aspects of RTM: RTM implementation-dependent features Performance evaluation on STAMP-RTM Profile conflict abort causes Sylvain Genevès Transactionnal Memory in commodity hardware 23 / 25

24 Future Work Possible uses of RTM Performance: transacionnal data structures In security: detect malicious memory access Watchpoints facility Dynamic Alias analysis Race detection Record/Replay framework... Sylvain Genevès Transactionnal Memory in commodity hardware 24 / 25

25 Thanks for your attention! Sylvain Genevès Transactionnal Memory in commodity hardware 25 / 25

26 Backup slides Chi Cao Minh, JaeWoong Chung, Christos Kozyrakis, and Kunle Olukotun. STAMP: Stanford transactional applications for multi-processing. In IISWC 08: Proceedings of The IEEE International Symposium on Workload Characterization, September Intel. Intel 64 and ia-32 architectures software developer s manual, http: //download.intel.com/products/processor/manual/ pdf. Sylvain Genevès Transactionnal Memory in commodity hardware