Autonomic Thread Parallelism and Mapping Control for Software Transactional Memory

Transcription

1 Autonomic Thread Parallelism and Mapping Control for Software Transactional Memory Presented by Naweiluo Zhou PhD Supervisors: Dr. Gwenae l Delaval Dr. E ric Rutten Prof. Jean-Franc ois Me haut PhD Defence October 21, 2016

2 The era of multi-core processors Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence 2 / 49

3 Introduction Single-core processors used to be dominant... Single-core processors Increment of clock frequency is approaching a physical end Multi-core processors 1 Include multiple cores on a single chip 2 Give high performance with more cores Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 3 / 49

4 Introduction Parallel applications enables high performance Tasks of an application are processed by multiple cores Execution accelerates as tasks are processed in parallel Transactional memory provides a good platform to deal with tasks in parallel therefore, utilised in this thesis Memory L3 C0 C1 C2 C3 L3 C4 C5 C6 C7 An overview of multi-core processor Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 4 / 49

5 Introduction More cores, higher performance, but... issues of parallel programs Concept: parallelism degree is the number of active threads (tn) Synchronisation time, computing time, data access time A high parallelism degree may decline computing time, but increase synchronisation time. More threads maybe higher synchronisation The trade-off between synchronisation and computation? Multi-core processors hold complicated memory architecture How to reduce data access time to memory? The behaviour of an application can vary during its execution How to control a system at runtime? Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 5 / 49

6 Introduction Contributions This thesis contributes to: High performance computing Autonomic computing: techniques that can manage systems automatically High Performance Computing Autonomic Computing Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence 6 / 49

7 Introduction Overview 1 Background on TM and Autonomic Computing Transactional Memory Thread Mapping Autonomic Computing Techniques 2 Autonomic Parallelism and Mapping Control Feedback Control Loop Overview Four Groups of Decision Functions 3 Performance Evaluation 4 Related Work 5 Conclusion and Future Work Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 7 / 49

8 Background on TM and Autonomic Computing Outline 1 Background on TM and Autonomic Computing Transactional Memory Thread Mapping Autonomic Computing Techniques 2 Autonomic Parallelism and Mapping Control Feedback Control Loop Overview Four Groups of Decision Functions 3 Performance Evaluation 4 Related Work 5 Conclusion and Future Work Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 8 / 49

9 Background on TM and Autonomic Computing Transactional Memory How to address synchronisation issues threads need to synchronise Locks A conventional way for synchronisation. But: Deadlocks, vulnerability to failures, faults... Difficult to detect deadlocks (e.g. not always reproducible) Hard to analyse interaction among concurrent operations Transactional Memory Lock-free, easy to implement concurrent operations Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 9 / 49

10 Background on TM and Autonomic Computing Transactional Memory Concepts of transactional memory Shared data access is wrapped into transactions A transaction is an atomic block Concurrent access is performed inside transactions Transactions are executed speculatively Can be implemented in STM (e.g. TinySTM, SwissTM...), HTM and HyTM 1 r/w conflict r r r r r w w... thread1 thread2 thread OK No OK Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 10 / 49

11 a Autonomic Thread Parallelism & Mapping Control for STM Background on TM and Autonomic Computing Transactional Memory Transactional Memory a transaction can either commit or abort, no intermediate status conflict Three concepts 1 Commit: a transaction succeeds changes are made to memory 2 Abort: a transaction has a conflict changes are discarded 3 Rollback: re-execute the aborted transactions abort Tx start rollback no conflict commit 1 r/w conflict r r r r w r w thread1 thread2 thread OK No OK Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 11 / 49

12 Background on TM and Autonomic Computing Transactional Memory Transactional memory Example Three threads access data from different memory locations Threads execute transactions Case1 thread1 reads object3 thread2 reads object3 1 r/w conflict r r r r w r w Case2 thread2 reads object7 thread3 writes object7 thread1 thread2 thread OK No OK Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 12 / 49

13 Background on TM and Autonomic Computing Transactional Memory How to deal with conflicts in TM When conflicts happen Many designs to solve conflicts: abort others, abort itself... 1 r/w conflict Case1 Thread1 Thread2 progress r r r r w r w... thread1 thread2 thread Case2: resolving conflicts one transaction aborts one transaction continues OK No OK Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 13 / 49

14 Background on TM and Autonomic Computing Thread Mapping Multi-core processors also bring complexity Data access latency differs Data access latency to different levels of memory differs Data access latency differs from one core to another How to place threads on cores to better use resources? 1 GB Primary Memory 60ns Memory 256 KB 32 KB 100 bytes cache L1 cache CPU registers 4ns 1ns < 1ns L3 data C0 C1 C2 C3 L3 C4 C5 C6 C7 Example of access latency Example of multi-core processor Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 14 / 49

15 Background on TM and Autonomic Computing Thread Mapping Thread mapping Concept: assign threads to specific cores 1 Better use of interconnects: using intra-chip interconnects 2 Reduce invalidation misses: reduce misses caused by two private caches: holding the same data and continuously invalidating each other 3 Reduce compulsory misses: caused by competition for the same cache. Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 15 / 49

16 Background on TM and Autonomic Computing Thread Mapping Thread mapping strategies Thread mapping: assign threads to specific cores We map threads to different cores to gain better performance 1 Compact threads are physically placed on sibling cores 2 Scatter threads are distributed across different processors 3 Round-Robin threads share higher level of cache (e.g. L3) but not the lower ones 4 Linux default thread scheduling based on priorities L3 L3 C0 C1 C2 C3 C0 C1 C2 C3 Compact Round-Robin L3 L3 C4 C5 C6 C7 C4 C5 C6 C7 L3 C0 C1 C2 C3 L3 C0 C1 C2 C3 thread mapping strategies 1 [1]: courtesy of Castro Scatter Linux L3 C4 C5 C6 C7 L3 C4 C5 C6 C7 thread migration Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 16 / 49

17 Background on TM and Autonomic Computing Autonomic Computing Techniques Restrictions of HPC systems: Restrictions from TM systems TM sytems are complicated and incorporate numerous tunable parameters (e.g. parallelism degrees) these parameters of TM are usually set offline few actions can be made to adapt them to runtime behaviour Hardware complexity brings more tunable parameters Autonomic computing techniques are capable of: Monitoring behaviour dynamically Tuning parameters accordingly to ameliorate performance Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence 17 / 49

18 Background on TM and Autonomic Computing Autonomic Computing Techniques Autonomic computing autonomic computing techniques enable systems to be self-adaptive This concept is first proposed by IBM in 2003 Autonomic control systems have at least one of the properties: Self-optimisation: seek to improve performance & efficiency Self-configuration: a new component learns the system configurations Self-healing: recover from failures Self-protection: defend against attacks Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 18 / 49

19 Background on TM and Autonomic Computing Autonomic Computing Techniques Autonomic computing Elements of a feedback control loop: 1 Managed element: any software or hardware resource 2 Autonomic manager a software component: monitor, plan, knowledge 3 Sensor: collect information 4 Effector: carry out changes Autonomic Element Autonomic Manager Analyse Plan Monitors Knowledge Execute sensors effectors Managed Elements A feedback control loop Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 19 / 49

20 Background on TM and Autonomic Computing Autonomic Computing Techniques Autonomic computing Components of the autonomic manager: 1 Monitor: sampling 2 Analyser 3 Knowledge 4 Plan: use the knowledge of the system to do computation 5 Execute: make changes Autonomic Element Autonomic Manager Analyse Plan Monitors Knowledge Execute sensors effectors Managed Elements A feedback control loop Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 20 / 49

21 Background on TM and Autonomic Computing Autonomic Computing Techniques What we want to address thread parallelism + App performance on + - muticore processors - thread mapping Our work considers two factors that can impact on performance Alas... Difficult to set a parallelism degree offline Difficult to decide thread locations offline Especially for applications with online behaviour variations Autonomic computing techniques can tackle the above issues Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 21 / 49

22 Autonomic Parallelism and Mapping Control Outline 1 Background on TM and Autonomic Computing Transactional Memory Thread Mapping Autonomic Computing Techniques 2 Autonomic Parallelism and Mapping Control Feedback Control Loop Overview Four Groups of Decision Functions 3 Performance Evaluation 4 Related Work 5 Conclusion and Future Work Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 22 / 49

23 Autonomic Parallelism and Mapping Control Problems of control both parallelism and thread mapping 1 Is thread mapping necessary? e.g. when tn<core number, mapping can be performed 2 The order of decisions: parallelism or thread mapping first? 3 If parallelism changes, its mapping strategy differs? 4 Frequency of changing thread mapping strategy? Performance lost by thread migration Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 23 / 49

24 Autonomic Parallelism and Mapping Control The solutions 1 Predict parallelism degree first 2 Predict the thread mapping strategy 3 Mapping is re-profiled when parallelism degree varies parallelism degree half of core number The reasons 1 The maximum parallelism degree requires no thread mapping (by Castro2012) 2 High parallelism degree may give unstable behaviour regardless of mapping (based on experimental observation) 3 Influence of parallelism is more significant (based on experimental observation) Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 24 / 49

25 Autonomic Parallelism and Mapping Control Metrics What we measure 1 parameters: commits, aborts, time 2 commit ratio (CR)= commits/(commits+aborts), throughput=commits/time CR range : detect phase change CR fluctuates within the range during the same phase High CR low contention, high throughput fast execution Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 25 / 49

26 Autonomic Parallelism and Mapping Control Feedback Control Loop Overview The feedback control loop Autonomic Element Autonomic Manager th inc and tn change and tn<=core_num/2 mapping & CR range process informa on make decisions start predict tn true verify true true no thread control parameters we measure sensors control ac ons effectors Transac onal memory Applica ons Mul core HW managed elements The feedback control loop overview of system architecture th dec stop profile ((CR>CR_UP or CR=1 ) and tn<tn_max ). or (CR<CR_LOW and tn>tn_min) The structure of autonomic manager in an automaton shape Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 26 / 49

27 Autonomic Parallelism and Mapping Control Feedback Control Loop Overview The feedback control loop 1 Control objectives: maximise throughput and reduce application execution time 2 Inputs: commits, aborts, time 3 Outputs: inc/dec parallelism degree, set thread mapping strategy Autonomic Element Autonomic Manager Analyse CR, th CR range Plan mapping, opt tn Monitors Knowledge online && offline Execute system info commits, aborts, profile flag, mapping sensors me inc/dec tn effectors TinySTM benchmarks Mul core HW Managed Elements The feedback control loop in MAPE-K shape Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 27 / 49

28 Autonomic Parallelism and Mapping Control Four Groups of Decision Functions Four groups of decision functions Decision functions of: 1 Parallelism 2 Thread mapping strategy 3 CR range (phase detection) 4 Thread profile start predict tn true verify th inc and tn change and tn<=core_num/2 th dec mapping & CR range true stop profile true ((CR>CR_UP or CR=1 ) and tn<tn_max ). or (CR<CR_LOW and tn>tn_min) no thread control The structure of autonomic manager Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 28 / 49

29 Autonomic Parallelism and Mapping Control Four Groups of Decision Functions Parallelism decision functions: two models Simple model No action unless a phase change is detected Keep inc/dec tn by one until throughput decreases Inc tn when CR > cr up; dec tn when CR < cr low Probabilistic model Directly compute the near-optimum parallelism degree Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 29 / 49

30 Autonomic Parallelism and Mapping Control Four Groups of Decision Functions Parallelism decision function: probabilistic model The number of transactions N executed during L 0 : N = L 0 L n = α n (1) within a fixed period L 0 (N=aborts+commits) assuming the average length of transactions is L The probability of a commit: Pr = (1 p) (N N n ) = q (N N n ) (2) p (independent of n): probability of a conflict between two txs; n is parallelism degree. Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 30 / 49

31 Autonomic Parallelism and Mapping Control Four Groups of Decision Functions Parallelism decision function: probabilistic model Pr = (1 p) (N N n ) = q (N N n ) (2) Equation (2) relies on two assumptions The same amount of transactions (txs) are executed in each active threads during a fixed period Enough amount of tx are executed making the probability of a conflict between two txs approaches a constant Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 31 / 49

32 Autonomic Parallelism and Mapping Control Four Groups of Decision Functions Parallelism decision function: probabilistic model P(X i = 1) = q (N N n ) = q α(n 1) (3) X i = 1 commit, X i = 0 aborts T is a random variable, T = X i T follows a binomial distribution: B(N, q (N N n ) ) Hence the expected value of T is: E[T ] = N.q (N N n ) = αnq α(n 1) (4) T (n) = α n q α(n 1) (5) T is throughput, α = L 0 L CR is the commit ratio Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 32 / 49

33 Autonomic Parallelism and Mapping Control Four Groups of Decision Functions Parallelism decision function: probabilistic model T (n) = αq α(n 1) + α 2 nq α(n 1) ln(q) = 0 (6) Hence the optimum parallelism degree: q = CR 1 α(n 1) (7) n opt = n 1 ln CR (8) n opt is optimum parallelism n is the active thread number CR is the commit ratio Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 33 / 49

34 Autonomic Parallelism and Mapping Control Four Groups of Decision Functions Two CR range decision functions Simple phase detection algorithm 1 Obtain the optimum tn 2 Obtain CR when inc/dec optimum tn by one Advanced phase detection algorithm: 1 cr up = cr opt + cr opt δ 2 cr low = cr opt cr opt δ cr opt : CR generated by the optimum tn and mapping δ inc 1% when a false phase change happens Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 34 / 49

35 Autonomic Parallelism and Mapping Control Four Groups of Decision Functions Thread mapping decision function Conditions for mapping strategies tn half the core number tn has changed Obtain the optimum mapping Profile each strategy Optimum strategy: generates the highest throughput start predict tn true verify th dec mapping & CR range stop profile ((CR>CR_UP or CR=1 ) and tn<tn_max). th inc and tn change and tn<=core_num/2 true or true (CR<CR_LOW and tn>tn_min) no thread control The structure of autonomic manager Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 35 / 49

36 Autonomic Parallelism and Mapping Control Four Groups of Decision Functions Thread profile decision function stop thread profile Current throughput previous throughput? set back old tn After thread mapping and CR range decision start predict tn true verify th inc and tn change and tn<=core_num/2 th dec mapping & CR range true stop profile true no thread control start thread profile CR falls out the CR range? ((CR>CR_UP or CR=1 ) and tn<tn_max ). or (CR<CR_LOW and tn>tn_min) The structure of autonomic manager Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 36 / 49

37 Performance Evaluation Outline 1 Background on TM and Autonomic Computing Transactional Memory Thread Mapping Autonomic Computing Techniques 2 Autonomic Parallelism and Mapping Control Feedback Control Loop Overview Four Groups of Decision Functions 3 Performance Evaluation 4 Related Work 5 Conclusion and Future Work Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 37 / 49

38 Performance Evaluation Experimental platforms Configurations for the UMA number of cores 24 number of sockets 4 clock (GHz) 2.66 cache capacity (KB) 3072 (each) L3 cache capacity(mb) 16 (each) DRAM capacity (GB) 64 L3 L3 Memory bus L3 L3 C0 C1 C2 C3 C4 C5 C6 c7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 STM and benchmarks for evaluation STM: TinySTM Benchmarks: EigenBench: artificial but highly configurable STAMP: generic but less configurable (include: yada etc.) Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 38 / 49

39 Performance Evaluation Time comparison with static parallelism average of 10-time executions dot is execution time for static parallelism our approaches outperform the static parallelism execution time (second) para para & mapping execution time (second) para para & mapping thread number thread number EigenBench yada (from STAMP) Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 39 / 49

40 Performance Evaluation Runtime thread number and mapping strategy variation runtime behaviour of one execution applications with multiple phases show necessity of runtime para & mapping adaptation thread number para para & mapping Scatter Compact thread number Compact 0 para para & mapping logic time (1.4K commits) logic time (10K commits) EigenBench yada (from STAMP) Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 40 / 49

41 Performance Evaluation How to verify the adaptive approaches Throughputs indicate program progress The throughputs by the autonomic control approaches: compare with max throughputs at each phase approach or exceed the max throughputs Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence 41 / 49

42 Performance Evaluation Online throughput variation runtime behaviour of one execution the throughputs from our methods approach or exceed those of the static parallelism throughput( ktx/s) threads 4thread 8threads 16threads 24threads para only para & mapping throughput( ktx/s) threads 4thread 8threads 16threads 24threads para only para & mapping logic time (1.4k commits) logic time (10k commits) EigenBench yada (from STAMP) Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 42 / 49

43 Performance Evaluation Discussion Limitations 1 The probabilistic parallelism predictor is based on ideal situations. The prediction can be sub-optimum de facto. 2 The optimum mapping strategy can differ over several executions: throughputs are affected by thread migration some mapping strategies show similar performance Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 43 / 49

44 Related Work Outline 1 Background on TM and Autonomic Computing Transactional Memory Thread Mapping Autonomic Computing Techniques 2 Autonomic Parallelism and Mapping Control Feedback Control Loop Overview Four Groups of Decision Functions 3 Performance Evaluation 4 Related Work 5 Conclusion and Future Work Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 44 / 49

45 Related Work Related work on parallelism and mapping static and dynamic adaptation 1 Parallelism adaptation using control techniques (Ansari2008, Rughetti2014) requires offline training procedure to obtain predictor less sensitive to online behaviour change 2 Thread mapping adaptation (Castro2012, Diener2010) dynamic mapping adaptation using machine learning on STM offline searching for optimum mapping on non-tm platforms 3 Coordination of parallelism and adaptation no previous work on adapting both parallelism & mapping dynamically for TM systems some studies show insights into offline adaptation for non-tm platforms (Wang2009, Corbalan2000) Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 45 / 49

46 Conclusion and Future Work Outline 1 Background on TM and Autonomic Computing Transactional Memory Thread Mapping Autonomic Computing Techniques 2 Autonomic Parallelism and Mapping Control Feedback Control Loop Overview Four Groups of Decision Functions 3 Performance Evaluation 4 Related Work 5 Conclusion and Future Work Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 46 / 49

47 Conclusion and Future Work Conclusion 1 Introduce feedback control loops to dynamically control: parallelism degree thread mapping coordination of the above 2 Propose: two models for sub-optimum parallelism detection two phase detection algorithms 3 Compare the performance of static parallelism with: adjusting parallelism only adjusting parallelism and thread mapping together Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 47 / 49

48 Conclusion and Future Work Future Work 1 Thread mapping new mapping strategies prediction of mapping strategies with assistance of compilers 2 From STM to HTM 3 Coordination of multiple feedback control loops 4 Feedback control loops for other parallel platforms (e.g. OpenMP) Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 48 / 49

49 Publications Publications 1 N. Zhou, G. Delaval, B. Robu, É. Rutten, and J.-F. Méhaut, Autonomic Parallelism and Thread Mapping Control on Software Transactional Memory, in ICAC th IEEE International Conference on Autonomic Computing, (Wursburg, Germany), July N. Zhou, G. Delaval, B. Robu, É. Rutten, and J.-F. Méhaut, Control of Autonomic Parallelism Adaptation on Software Transactional Memory, in International Conference on High Performance Computing & Simulation (HPCS), (Innsbruck, Austria), July (Outstanding Paper Nomination) 3 N. Zhou, G. Delaval, B. Robu, É. Rutten, and J.-F. Méhaut, Autonomic Parallelism Adaptation for Software Transactional Memory, in Conférence d informatique en Parallélisme, Architecture et Système (COMPAS), (Lorient, France), July N. Zhou, G. Delaval, B. Robu, É. Rutten, and J.-F. Méhaut, Autonomic Parallelism Adaptation on Software Transactional Memory, Research Report RR-8887, Univ. Grenoble Alpes ; INRIA Grenoble, Mar Grenoble Alpes University/INRIA,France Naweiluo Zhou, PhD thesis defence naweiluo.zhou@inria.fr 49 / 49