NuSpeech Family N5132 High Sound Quality Voice Synthesizer Technical Reference Manual

Transcription

1 NuSpeech Family N5132 High Sound Quality Voice Synthesizer Technical Reference Manual The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NuVoice microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. November 7, 2014 Page 1 of 20 Rev. 1.0

2 Table of Contents Table of Contents... 2 List of Tables... 3 List of Figures General Description Features Pin Configuration Pin Assignment (SOP20) Pin Description SPI interface SPI Command Summary The command protocol type The limitations of SPI command protocol The maximum SPI bus serial clock rate Intervals between successive SPI commands Send PLAY commands continually How to wake up N Status Register The Calibration of System Clock Application Circuit Revision History November 7, 2014 Page 2 of 20 Rev. 1.0

3 List of Tables Table 4-1: The SPI command summary... 8 Table 6-1: The method to enable the output of 250 Hz clock List of Figures Figure 4-1: N5132 supports SPI bus protocol Mode Figure 4-2: The common features of all command protocol types... 9 Figure 4-3: N5132 receives the PLAY command correctly Figure 4-4: The N5132 will not execute this PLAY command Figure 4-5: The desired protocol sequence for READ_ID command Figure 4-6: The N5132 does not execute the READ_ID command Figure 4-7: Open the Product ID menu Figure 4-8: The SPI bus timing of READ_ID command Figure 4-9: N5132 receives a valid command based on the command protocol Figure 4-10: N5132 will not execute the received command once ABANDON-code is received.. 13 Figure 4-11: The SPI bus serial clock rate can be up to 12.5KHz Figure 4-12: The intervals between two successive SPI transitions must be longer than 1 ms Figure 4-13: Send STOP command to terminate the previous playback Figure 4-14: The method to wake up N5132 from standby mode Figure 7-1: The application circuit for 3 batteries Figure 7-2: The application circuit for 2 batteries November 7, 2014 Page 3 of 20 Rev. 1.0

4 1 GENERAL DESCRIPTION The N5132 is a high sound quality Voice Synthesizer with advanced 5-bit MDPCM algorithm. It includes 4-bit C with SPI interface to communicate with external and PWM output to playback voice.. Note1: Please refer to data sheet for electrical related spec and typical applications. 2 FEATURES Wide operation voltage: 2.2~5.5V Embedded 2M-bit OTP System clock: 8MHz generated by ring oscillation Hardware synthesis 1 channel with 5-bit MDPCM data format The voice file will be encoded to MDPCM data format by playlist editor tool. The playlist editor tool possesses friendly GUI to allow user to define voices combination. Built-in PWM to drive speaker directly Provide Watch Dog Timer Low Voltage Reset (LVR) to avoid lock up Provide SPI interface to communicate with external The N5132 operates in SPI bus protocol mode 3 only. The N5132 will serve as a slave device while external microcontroller is a master. The SPI bus serial clock rate can be up to 12.5KHz Package type: SOP 20-pin Die form November 7, 2014 Page 4 of 20 Rev. 1.0

5 3 PIN CONFIGURATION 3.1 Pin Assignment (SOP20) NC 1 20 BP32 (0: Enable CLK250HZ output) VSS1 BP33 (CLK250HZ output) VDD1 VPP PWM+ /RESET VDD_SPK PWM- 5 N5132 (SOP20) 15 VDD OSC VSS_SPK VSS TEST BP13 () V33O BP12 () () BP BP11 () 3.2 Pin Description Name Type Power Description 1. SPI interface (BP10) I/O VDD The chip select pin of SPI interface. The alternate function is used to program OTP memory. (BP11) I/O VDD The serial clock pin of SPI interface. The alternate function is used to program OTP memory. (BP12) I/O VDD The master data input/slave data output pin of SPI interface. The alternate function is used to program OTP memory. (BP13) I/O VDD The master data output/slave data input pin of SPI interface. The alternate function is used to program OTP memory. 2. Oscillator OSC I V33O Ring oscillator input. Connect one resistor of 150K ohm to VSS. 3. Speaker Driver PWM+ O VDD_SPK PWM drive positive output. PWM- O VDD_SPK PWM drive negative output. VDD_SPK P - Power supply for PWM drive. VSS_SPK P - Ground for PWM drive. 4. Power VDD1 P - Power supply for BP32 and BP33. It must connect to VDD. November 7, 2014 Page 5 of 20 Rev. 1.0

6 VSS1 P - Ground pin. It must connect to VSS. VDD P - Power supply. VSS P - Ground pin. V33O Pout VDD 3.3V regulator output. It is for chip internal use only, cannot connect to external device. VPP P - Power supply 7.5V input for OTP memory programming. 5. Other NC for normal operation. /RESET I VDD Chip reset input pin with Schmitt trigger, internal pull-high. TEST I VDD Test pin, internal pull-high. The alternate function is used to program OTP memory. BP32 I VDD1 To connect BP32 to GND will enable the output of 250 Hz clock at BP33. But the BP32 setting can take effect only when the SPI CLK250HZ_EN command is not issued from host. Please refer to Chapter 6 for detailed description. BP33 O VDD1 This pin will output 250 Hz clock for calibration once SPI command CLK250HZ_EN is received, or BP32 is connected to GND. Please refer to Chapter 6 for detailed description. This pin will change to input type when the N5132 enters standby mode. November 7, 2014 Page 6 of 20 Rev. 1.0

7 4 SPI INTERFACE The N5132 uses an industry standard SPI interface to communicate with microcontroller host. However, the SPI bus protocol includes 4 modes. But the N5132 operates in mode 3 only. These SPI modes determine the relationship between the serial clock and the data bits. Many common microcontrollers contain built-in hardware SPI ports. Some of these controllers make the SPI mode fully programmable, others allow a more limited selection. In order to have direct compatibility with the N5132, the user should select Mode 3. Attempting to communicate in modes other than 3 will cause the N5132 to behave unpredictably. In some cases, users will be emulating the SPI protocol in software using general-purpose port pins. In this case, the software can be written to manipulate the port pins to achieve the correct relationship. The correct relationship for Mode 3 is shown in the Figure 4-1. Shift out Shift in MSB LSB MSB LSB Figure 4-1: N5132 supports SPI bus protocol Mode 3 For mode 3, the signal must fall low prior to the first falling edge of. The data input at pin is latched on the rising edge of serial clock () and data output at pin shifts out on the falling edge of. Finally the is raised to high level to close this SPI transaction. November 7, 2014 Page 7 of 20 Rev. 1.0

8 4.1 SPI Command Summary The microcontroller host can send commands through the SPI interface to achieve the intended functions. The SPI commands supported by the N5132 are listed in Table 4-1. Table 4-1: The SPI command summary Command Format Function description Command Protocol 1. END 0x01 END-code at the end of SPI transaction All protocol types 2. READ_ID 0x10 Read identification typed in playlist generation Protocol type 2 3. READ_ 0x11 Query the value of status register of N5132 Protocol type 3 4. PLAY 0x7F Play the selected playlist specified by the INDEX byte which follows the PLAY command. The INDEX byte indicates the playlist number. Protocol type 1 5. STOP 0x80 Stop playback Protocol type 3 6. PWR_DOWN 0x82 N5132 enters standby mode. N5132 will consume minimum power. Protocol type 3 7. CLK250HZ_EN 0x83 Enable the output of 250 Hz clock at BP33 pin Protocol type 3 8. CLK250HZ_DIS 0x84 Disable the output of 250 Hz clock at BP33 pin Protocol type 3 9. ABANDON 0xE0 ABANDON-code at the end of SPI transaction. All protocol types 10. VOL1 0xF1 Small volume Protocol type VOL2 0xF2 Set volume larger than VOL1 setting Protocol type VOL3 0xF3 Set volume larger than VOL2 setting Protocol type VOL4 0xF4 Full volume Protocol type 3 The N5132 incorporates three types of command protocol to send the SPI commands. A complete explanation of the command protocol types is described in the section 4.2. But all the command protocol types possess the common features listed below. The SPI command is shifted into the first byte of SPI transaction. And the command s MSB bit is the first bit to be sent by the microcontroller host. The value of status register of N5132 is always shifted out as the first byte at pin. And the MSB of status register is the first bit to be shifted out by the N5132. The received SPI command by N5132 will be to pin after status byte November 7, 2014 Page 8 of 20 Rev. 1.0

9 (Feature 1) command (Feature 2) Command (Feature 3) Figure 4-2: The common features of all command protocol types November 7, 2014 Page 9 of 20 Rev. 1.0

10 4.2 The command protocol type The N5132 incorporates the command protocols to prevent inadvertent write cycles caused by spurious system level signals that may exist during power transition. The feature of command protocol allows microcontroller host to examine in time whether or not the N5132 receives the instructions correctly. Command protocol type 1 This command protocol 1 is applied to PLAY command only. The Figure 4-3 shows that the PLAY command is transmitted successfully. The host can close the SPI transaction after sending three bytes and N5132 will execute the PLAY command to play the selected playlist specified by the INDEX. The INDEX byte indicates the playlist number. PLAY command INDEX END-code (0x01) PLAY command INDEX Figure 4-3: N5132 receives the PLAY command correctly. If the PLAY command is not correctly, the microcontroller should send an ABANDON-code following the INDEX byte. The N5132 will not execute the PLAY command. The command protocol to abort this PLAY command is shown in Figure 4-4. PLAY command INDEX ABANDON-code (0xE0) Wrong command INDEX Figure 4-4: The N5132 will not execute this PLAY command. November 7, 2014 Page 10 of 20 Rev. 1.0

11 Command protocol type 2 This command protocol 2 is applied to READ_ID only. The READ_ID command is used to read the 4 bytes of product ID bonded to the set of playlists. When user creates the playlists using the playlist editor tool, user can assign 4-byte hexadecimal codes as the specified product ID at the same time. In order to do validation of connected chip, the microcontroller host can compare the product ID by using the READ_ID command. Once READ_ID command is received at the beginning of SPI transaction, N5132 will shift out the product ID following the command. The desired protocol sequence is shown in Figure READ_ID command x** 0x** 0x** 0x** END-code (0x01) Command ID[31:24] ID[23:16] ID[15:8] ID[7:0] 0x** = means do not care Figure 4-5: The desired protocol sequence for READ_ID command. The microcontroller host can terminate this SPI transaction using the command scheme shown in Figure 4-6 if the command is wrong. READ_ID command 0x** ABANDON-code (0xE0) Wrong command 0x** 0x** = means do not care Figure 4-6: The N5132 does not execute the READ_ID command. To create your product ID, on the Project tab, click the Set product ID menu (Figure 4-7). On the menu, type 8 alphanumeric characters as your product ID related to this created project. The Figure 4-8 shows the SPI bus timing to shift the 8 alphanumeric characters to host in detail. November 7, 2014 Page 11 of 20 Rev. 1.0

12 Figure 4-7: Open the Product ID menu. READ_ID command 0x10 0x** 0x10 0x** 0xD4 0x** 0xC3 0x** 0xB2 0x01 0xA1 0x** = means do not care ID[31:24] ID[23:16] ID[15: 8] ID[ 7: 0] Figure 4-8: The SPI bus timing of READ_ID command. November 7, 2014 Page 12 of 20 Rev. 1.0

13 Command protocol type 3 For the other commands except PLAY and READ_ID commands, the command protocol 3 can achieve the intended functions. The protocol timing is illustrated in Figure 4-9. The microcontroller host can send the command followed by one END-code and then closes this SPI transaction. The first byte shifted out at pin by the N5132 is the value of status register which will be described in section 4.4. The second byte shifted out by N5132 is the received command at pin. So microcontroller host can examine the command to know whether or not the N5132 receives the command correctly in time. In most cases the microcontroller can acknowledge that this SPI transaction is valid by closing this SPI transaction after sending an END-code. Command END-code (0x01) Command Figure 4-9: N5132 receives a valid command based on the command protocol 1. By contrast, if N5132 returns a wrong command which is not the same to what microcontroller sends, the microcontroller host can expect the interference occurs at SPI bus, and N5132 does not receive the command correctly. Then microcontroller can send an ABANDON-code following the END-code to abort this SPI transaction. While the N5132 receives the ABANDON code, it will not execute the received wrong command. So this protocol scheme with ABANDON-code can offer protection against mis-operation. The protocol scheme with ABANDON-code is shown in Figure By comparing to Figure 4-10 and Figure 4-6, the microcontroller host always sends END-code following the command in this protocol sequence. Command END-code (0x01) ABANDON-code (0xE0) Wrong command 0x01 Figure 4-10: N5132 will not execute the received command once ABANDON-code is received. November 7, 2014 Page 13 of 20 Rev. 1.0

14 4.3 The limitations of SPI command protocol Users need to notice three operating limitations to use the SPI command protocol of N The maximum SPI bus serial clock rate The N5132 can tolerate 12.5 KHz of SPI bus serial clock rate maximally, i.e. the microcontroller host cannot send the serial clock too quick. The maximum clock rate is 12.5 KHz. The microcontroller host cannot send the serial clock beyond 12.5 KHz. Command Command Figure 4-11: The SPI bus serial clock rate can be up to 12.5KHz Intervals between successive SPI commands The SPI transaction is designed to send one command and it may apply certain command protocol type suitable to the command. When microcontroller host wants to send commands continually, the intervals between two successive SPI transitions must be longer than 1ms. Otherwise both successive commands will be ignored by the N5132. ³ 1 ms Command 1 Command 2 Figure 4-12: The intervals between two successive SPI transitions must be longer than 1 ms Send PLAY commands continually Before the PLAY command is issued, the register should be check to ensure the previous playback is completed. If the speech is still busy, and the microcontroller host wants to terminate the previous playback, then STOP command should be issued prior to next PLAY command. November 7, 2014 Page 14 of 20 Rev. 1.0

15 playback is still busy ³ 1 ms ³ 1 ms PLAY command INDEX END-code (0x01) STOP command END-code (0x01) PLAY command INDEX END-code (0x01) PLAY command INDEX Command PLAY command INDEX Figure 4-13: Send STOP command to terminate the previous playback How to wake up N5132 The N5132 will enter standby mode to consume minimum power after it receives the PWR_DOWN command. User should notice there is not a specified command to wake up the N5132 from standby mode. The method to wake up N5132 is to send two successive commands. The N5132 will ignore the first command and execute the second command. So the first command is a redundant command and the second command is what microcontroller host would really intend to issue. N5132 enters standby mode ³ 1 ms PWR_DOWN Command END-code Command (0x01) Command END-code (0x01) Command Wrong command Command The redundant command. The second command is what microcontroller host would really intend to issue. Figure 4-14: The method to wake up N5132 from standby mode. November 7, 2014 Page 15 of 20 Rev. 1.0

16 5 REGISTER The N5132 has one status register indicating the real-time operating status. It is an 8-bit register and the MSB bit is the first bit to be shifted out at the beginning of SPI transfer. Status Register SP_BUSY VALID Reserved VOL Bits Description [7] SP_BUSY [6] VALID Playback status 0 = N5132 has stopped playing speech. 1 = N5132 is playing speech. The result of SPI command in previous SPI transaction 0 = The previous SPI command is an invalid command. The reason may be one of below three conditions. (1) The first byte of previous SPI transfer is not the specified SPI command. (2) Wrong command protocol type. (3) The INDEX value following PLAY command is greater than the number of available playlists. (4) The last byte of previous SPI transfer is the ABANDON code (0xE0), so the previous SPI command is not executed. 1 = The command in previous SPI transaction is received correctly and N5132 has executed completely. [5:3] Reserved Reserved. [7:0] VOL The volume level of PWM drive 1 = Small volume. 2 = Volume larger than VOL=1 setting. 3 = Volume larger than VOL=2 setting. 4 = Full volume. November 7, 2014 Page 16 of 20 Rev. 1.0

17 6 THE CALIBRATION OF SYSTEM CLOCK The desired system clock of N5132 is 8,192 KHz. The system clock is generated by the ring oscillator which connects 150K ohm resistor at OSC pin to ground. That 150K ohm resistor is labeled as Rosc. Somehow the built-in ring oscillation circuit may vary from lot to lot. In this case, the 8,192 KHz of system clock will relate to different Rosc value. The N5132 has one method to calibrate the system clock. The BP33 will output 250 Hz clock signal when the system clock operates at 8,192 KHz exactly. When the clock frequency of BP33 signal is more than 250 Hz, it means the system clock is more than 8,192 KHz. In this case, Rosc can be changed to a higher value of 150K ohm. On the other hand, when the clock frequency of BP33 signal is less than 250 Hz, it means the system clock is less than 8,192 KHz, then Rosc can be changed to a lower value of 150K ohm. The BP33 is a pull-high input pin by default. In order to facilitate measurement the N5132 provides two schemes to enable the output of 250 Hz clock signal. One method is to connect BP32 to low and another method is to send the CLK250HZ_EN command through the SPI command protocol. One is hardware method and the other is software method to do the same function. These two methods may conflict at the same time. So the Table 6-1 comes out a truth table to enable the output of 250 Hz clock. Table 6-1: The method to enable the output of 250 Hz clock. N5132 pins SPI command BP32 BP33 CLK250HZ_EN CLK250HZ_DIS 1/0 1 0 Ignore 250Hz clock No clock 250Hz clock The interpretation of Table 6-1 is that the SPI command CLK250HZ_EN will force the output of 250 Hz clock at BP33 no matter the setting of BP32 pin. The BP32 setting can take effect only when the CLK250HZ_EN command is not issued or the clock output function is disabled after CLK250HZ_DIS command is issued. The 250 Hz clock can occur at BP33 continually no matter playback occurs or not when the clock output is enabled using the above scheme. November 7, 2014 Page 17 of 20 Rev. 1.0

18 7 APPLICATION CIRCUIT 1 NC VSS1 N5132 (SOP20) BP32 20 BP33 SPEAKER VCC VDD1 PWM+ VPP /RESET 0.1uF VCC VCC 5 VDD_SPK PWM- VDD OSC ohm 0.1uF 4.7uF Microcontroller Host VSS_SPK VSS TEST () BP13 0.1uF 10 V33O BP10 () () BP12 () BP11 11 Figure 7-1: The application circuit for 3 batteries. 1 NC VSS1 N5132 (SOP20) BP32 20 BP33 SPEAKER VCC VDD1 PWM+ VPP /RESET 0.1uF VCC VCC 5 VDD_SPK PWM- VDD OSC ohm 0.1uF 4.7uF Microcontroller Host VSS_SPK VSS VCC TEST () BP13 0.1uF 10 V33O BP10 () () BP12 () BP11 11 Figure 7-2: The application circuit for 2 batteries. November 7, 2014 Page 18 of 20 Rev. 1.0

19 8 REVISION HISTORY VERSION DATE PAGE/ CHAP. DESCRIPTION V1.0 Nov., Initial release. November 7, 2014 Page 19 of 20 Rev. 1.0

20 Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, Insecure Usage. Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer s risk, and in the event that third parties lay claims to Nuvoton as a result of customer s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton. November 7, 2014 Page 20 of 20 Rev. 1.0