N76E003 Series Errata Sheet

Transcription

1 N76E003 Series Errata Sheet Errata Sheet for 8-bit 8051 Family Rev Dec. 6, 2017 Document Information Abstract Apply to This errata sheet describes the functional problems known at the release date of this document. N76E003 Series. Rev Dec. 6, of 6

2 Table of Contents 1 OVERVIEW FUNCTIONAL PROBLEMS POR issue after Power down Wake up WDT Reset Fail Issue after N76E003 Power down REVISION HISTORY... 6 Rev Dec. 6, of 6

3 1 Overview Functional Problem POR issue after Power down Wake up WDT Reset Fails after N76E003 Power Down Description Each timer wakeup from power down mode maybe cause reset by POR. Suggest disable POR function before N76E003 into power down mode. When system clock divider enable WDT reset function will be fail after N76E003 run into power down mode. Suggest use WKT to wake up MCU when power down. Rev Dec. 6, of 6

4 2 Functional Problems 2.1 POR issue after Power down Wake up Description: Each timer wakeup from power down mode maybe cause reset by POR. Suggest disable POR function before N76E003 into power down mode. Problem: Each N76E003 with a function macro named as POR, The power-on detection function is designed for detecting power up after power voltage reaches to a level where system can work. But Since the POR detect voltage is always stable at one value, the actually is from 1.3 V ~1.5 V. When N76E003 run in power down mode, MCU only run under a low power consumption condition each time wake up from power down mode, to change the condition to normal power consumption, maybe cause the MCU power glitch to under 1.5V, then the POR will be trig, and MCU will reset. Workaround: Since POR only for VDD power on, after power on the system power detect is use LVR, and when power down mode wakeup system power no any change. So strong suggest to disable POR function each time after power on reset at the initial part of Customer code. How to disable POR: At SFR address FDH is the PORDIS register to control disable POR function throng software. PORDIS POR disable (TA protected) PORDIS[7:0] W Address: FDH, Page: 0 Reset value: b Bit Name Description 7:0 PORDIS[7:0] POR disable To first writing 5AH to the PORDIS and immediately followed by a writing of A5H will disable POR. Rev Dec. 6, of 6

5 Since PORDIS register is TA protected, please always follow list code step to disable POR. sfr PORDIS = 0XFD; TA =0XAA; TA= 0X55; PORDIS = 0X5A; TA=0XAA; TA=0X55; PORDIS = 0XA5; 2.2 WDT Reset Fails after N76E003 Power Down Description: When system clock divider is enabled, the WDT reset function will fail after N76E003 enters Power-down mode. Problem: When CKDIV writes in data not equal to 0x00, the system clock divider is enabled. Under this condition, when MCU enters Power-down mode, the WDT flag will not be set, and thus WDT reset will fail. Workaround: Since the N76E003 supports WKT wake up from Power-down mode function, it is suggested to use WKT instead of WDT reset function, use WDT interrupt to avoid code abnormal run, and use WKT for power down wake up. Rev Dec. 6, of 6

6 3 Revision History Revision Date Description 1.00 May. 1, 2017 Initially issued Dec. 6, 2017 Added section 2.2 Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, Insecure Usage. Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer s risk, and in the event that third parties lay claims to Nuvoton as a result of customer s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton. Rev Dec. 6, of 6