SIC: Provably Timing-Predictable Strictly In-Order Pipelined Processor Core
|
|
|
- Geoffrey Carr
- 5 years ago
- Views:
Transcription
1 SIC: Provably Timing-Predictable Strictly In-Order Pipelined Processor Core Sebastian Hahn and Jan Reineke RTSS, Nashville December, 2018 saarland university computer science
2 SIC: Provably Timing-Predictable Strictly In-Order Pipelined Processor Core Sebastian Hahn and Jan Reineke RTSS, Nashville December, 2018 saarland university computer science
3 State-of-the-Art Timing Analysis Taskset running on Hardware platform All tasks meet their deadline. At least one task misses its deadline. Sebastian Hahn Strictly In-Order Core RTSS / 17
4 State-of-the-Art Timing Analysis per task Taskset running on Hardware platform Task-Level Analysis All tasks meet their deadline. At least one task misses its deadline. Sebastian Hahn Strictly In-Order Core RTSS / 17
5 State-of-the-Art Timing Analysis per task Task-Level Analysis Taskset running on Hardware platform characteristics per task, e.g. WCET C i All tasks meet their deadline. At least one task misses its deadline. Sebastian Hahn Strictly In-Order Core RTSS / 17
6 State-of-the-Art Timing Analysis per task Taskset running on Hardware platform Task-Level Analysis characteristics per task, e.g. WCET C i Schedulability Analysis All tasks meet their deadline. At least one task misses its deadline. Sebastian Hahn Strictly In-Order Core RTSS / 17
7 State-of-the-Art Timing Analysis per task Taskset running on Hardware platform Task-Level Analysis characteristics per task, e.g. WCET C i Schedulability Analysis All tasks meet their deadline. At least one task misses its deadline. Inside Schedulability Analysis: R i := C i + j hp(i) Ri T j C j Sebastian Hahn Strictly In-Order Core RTSS / 17
8 State-of-the-Art Timing Analysis Multi-Core System per task Taskset running on Hardware platform Task-Level Analysis characteristics per task, e.g. WCET C i, #BusAcc.,... Schedulability Analysis All tasks meet their deadline. At least one task misses its deadline. Inside Schedulability Analysis: R i := C i + j hp(i) Ri T j C j Sebastian Hahn Strictly In-Order Core RTSS / 17
9 State-of-the-Art Timing Analysis Multi-Core System per task Taskset running on Hardware platform Task-Level Analysis characteristics per task, e.g. WCET C i, #BusAcc.,... Schedulability Analysis All tasks meet their deadline. At least one task misses its deadline. Inside Schedulability Analysis: R i := C i + j hp(i) Ri I bus (i, R i ): worst-case interference on shared bus T j C j + I bus (i, R i ) penalty +... Sebastian Hahn Strictly In-Order Core RTSS / 17
10 State-of-the-Art Timing Analysis Multi-Core System per task Taskset running on Hardware platform Task-Level Analysis characteristics per task, e.g. WCET C i, #BusAcc.,... Schedulability Analysis All tasks meet their deadline. At least one task misses its deadline. Inside Schedulability Analysis: R i := C i + j hp(i) Ri Requires I bus Compositionality for Soundness (i, R i ): worst-case interference on shared bus T j C j + I bus (i, R i ) penalty +... Does not hold even for simple hardware platforms [Hahn et al., RTNS 16] Sebastian Hahn Strictly In-Order Core RTSS / 17
11 Why Task-Level Analysis is Expensive Microarchitectural State Space Exploration Set of System States Processor Cycle Sebastian Hahn Strictly In-Order Core RTSS / 17
12 Why Task-Level Analysis is Expensive Microarchitectural State Space Exploration + Longest Path Search Set of System States Processor Cycle Sebastian Hahn Strictly In-Order Core RTSS / 17
13 Why Task-Level Analysis is Expensive Microarchitectural State Space Exploration + Longest Path Search cache miss... Set of System States Processor Cycle cache hit Sebastian Hahn Strictly In-Order Core RTSS / 17
14 Why Task-Level Analysis is Expensive Microarchitectural State Space Exploration + Longest Path Search cache miss... Set of System States Processor Cycle cache hit State Space Explosion due to Timing Anomalies Sebastian Hahn Strictly In-Order Core RTSS / 17
15 Compositionality + Anomaly Freedom = Timing Predictability Sebastian Hahn Strictly In-Order Core RTSS / 17
16 Timing Anomalies and Execution Progress cache miss cache hit Sebastian Hahn Strictly In-Order Core RTSS / 17
17 Timing Anomalies and Execution Progress cache miss cache hit Sebastian Hahn Strictly In-Order Core RTSS / 17
18 Timing Anomalies and Execution Progress cache miss cache hit less progress Sebastian Hahn Strictly In-Order Core RTSS / 17
19 Timing Anomalies and Execution Progress cache miss cache hit less progress more progress Sebastian Hahn Strictly In-Order Core RTSS / 17
20 Timing Anomalies and Execution Progress cache miss cache hit less progress more progress Timing anomaly Cycle behaviour is non-monotonic Sebastian Hahn Strictly In-Order Core RTSS / 17
21 Timing Anomalies and Execution Progress cache miss cache hit less progress more progress Timing anomaly Cycle behaviour is non-monotonic Cycle behaviour is monotonic No timing anomalies Sebastian Hahn Strictly In-Order Core RTSS / 17
22 Monotonicity w.r.t. Progress is Key to... Anomaly Freedom c miss cache miss cache hit less progress c hit Sebastian Hahn Strictly In-Order Core RTSS / 17
23 Monotonicity w.r.t. Progress is Key to... Anomaly Freedom c miss cache miss cache hit less progress c hit less progress less progress less progress Sebastian Hahn Strictly In-Order Core RTSS / 17
24 Monotonicity w.r.t. Progress is Key to... Anomaly Freedom c miss cache miss cache hit less progress c hit less progress less progress less progress finish(c miss) finish(c hit) Sebastian Hahn Strictly In-Order Core RTSS / 17
25 Monotonicity w.r.t. Progress is Key to... Timing Compositionality with Penalty p c miss cache miss cache hit c hit p cycles c rectified Sebastian Hahn Strictly In-Order Core RTSS / 17
26 Monotonicity w.r.t. Progress is Key to... Timing Compositionality with Penalty p c miss cache miss cache hit c hit p cycles c rectified finish(c miss ) = finish(c rectified ) + p Sebastian Hahn Strictly In-Order Core RTSS / 17
27 Monotonicity w.r.t. Progress is Key to... Timing Compositionality with Penalty p c miss cache miss cache hit c hit p cycles more progress c rectified finish(c miss ) = finish(c rectified ) + p Sebastian Hahn Strictly In-Order Core RTSS / 17
28 Monotonicity w.r.t. Progress is Key to... Timing Compositionality with Penalty p c miss cache miss cache hit c hit p cycles more progress c rectified finish(c miss ) = finish(c rectified ) + p finish(c rectified ) finish(c hit ) Sebastian Hahn Strictly In-Order Core RTSS / 17
29 Monotonicity w.r.t. Progress is Key to... Timing Compositionality with Penalty p c miss cache miss cache hit c hit p cycles more progress c rectified finish(c miss ) = finish(c rectified ) + p finish(c rectified ) + p finish(c hit ) + p Sebastian Hahn Strictly In-Order Core RTSS / 17
30 Even Simple Microarchitectures Behave Non-Monotonically Conventional In-Order Pipeline Fetch Decode Execute Memory Write-Back Instruction Cache Data Cache Memory Sebastian Hahn Strictly In-Order Core RTSS / 17
31 Even Simple Microarchitectures Behave Non-Monotonically Conventional In-Order Pipeline Fetch Decode Execute Memory Write-Back add, 5 load ready Sebastian Hahn Strictly In-Order Core RTSS / 17
32 Even Simple Microarchitectures Behave Non-Monotonically Conventional In-Order Pipeline Fetch Decode Execute Memory Write-Back add, 5 load ready add load ready Sebastian Hahn Strictly In-Order Core RTSS / 17
33 Even Simple Microarchitectures Behave Non-Monotonically Conventional In-Order Pipeline Fetch Decode Execute Memory Write-Back add, 5 load ready add load ready cycle cycle add fetch miss load data miss Sebastian Hahn Strictly In-Order Core RTSS / 17
34 Even Simple Microarchitectures Behave Non-Monotonically Conventional In-Order Pipeline Fetch Decode Execute Memory Write-Back add, 5 load ready add load ready cycle cycle add fetch miss load data miss add, 4 load ready Sebastian Hahn Strictly In-Order Core RTSS / 17
35 Even Simple Microarchitectures Behave Non-Monotonically Conventional In-Order Pipeline Fetch Decode Execute Memory Write-Back add, 5 load ready add load ready cycle add, 4 load ready add cycle load, ml add fetch miss load data miss Sebastian Hahn Strictly In-Order Core RTSS / 17
36 Even Simple Microarchitectures Behave Non-Monotonically Conventional In-Order Pipeline Fetch Decode Execute Memory Write-Back add, 5 load ready add load ready cycle cycle add fetch miss load data miss add, 4 load ready add load, ml Sebastian Hahn Strictly In-Order Core RTSS / 17
37 Even Simple Microarchitectures Behave Non-Monotonically Conventional In-Order Pipeline Fetch Decode Execute Memory Write-Back add, 5 load ready add load ready add fetch miss Relative progress ofcycle instructions influences ordercycle of bus accesses load data miss add, 4 load ready add load, ml Sebastian Hahn Strictly In-Order Core RTSS / 17
38 Even Simple Microarchitectures Behave Non-Monotonically Conventional In-Order Pipeline Relative progress of instructions influences order of bus accesses Sebastian Hahn Strictly In-Order Core RTSS / 17
39 Even Simple Microarchitectures Behave Non-Monotonically Conventional In-Order Pipeline Relative progress of instructions influences order of bus accesses Idea: Make order of bus accesses independent of relative progress Sebastian Hahn Strictly In-Order Core RTSS / 17
40 Even Simple Microarchitectures Behave Non-Monotonically Conventional In-Order Pipeline Relative progress of instructions influences order of bus accesses Idea: Make order of bus accesses independent of relative progress Mechanism: Prioritise data accesses over instruction fetches Sebastian Hahn Strictly In-Order Core RTSS / 17
41 SIC: Strictly In-Order Pipelined Core Enforce Monotonic Behaviour Implementation: Prevent bus accesses of instruction fetches while Implementation: data-accessing instructions in the pipeline Sebastian Hahn Strictly In-Order Core RTSS / 17
42 SIC: Strictly In-Order Pipelined Core Enforce Monotonic Behaviour Implementation: Prevent bus accesses of instruction fetches while Implementation: data-accessing instructions in the pipeline Fetch Decode Execute Memory Write-Back Instruction Cache Data Cache Memory Sebastian Hahn Strictly In-Order Core RTSS / 17
43 SIC: Strictly In-Order Pipelined Core Enforce Monotonic Behaviour Implementation: Prevent bus accesses of instruction fetches while Implementation: data-accessing instructions in the pipeline fetch ins Fetch Decode Execute Memory Write-Back Instruction Cache Data Cache Memory Sebastian Hahn Strictly In-Order Core RTSS / 17
44 SIC: Strictly In-Order Pipelined Core Enforce Monotonic Behaviour Implementation: Prevent bus accesses of instruction fetches while Implementation: data-accessing instructions in the pipeline fetch ins Fetch Decode Execute Memory Write-Back ins misses Instruction Cache Data Cache Memory Sebastian Hahn Strictly In-Order Core RTSS / 17
45 SIC: Strictly In-Order Pipelined Core Enforce Monotonic Behaviour Implementation: Prevent bus accesses of instruction fetches while Implementation: data-accessing instructions in the pipeline load/store pending? fetch ins Fetch Decode Execute Memory Write-Back ins misses Instruction Cache Data Cache Memory Sebastian Hahn Strictly In-Order Core RTSS / 17
46 SIC: Strictly In-Order Pipelined Core Enforce Monotonic Behaviour Implementation: Prevent bus accesses of instruction fetches while Implementation: data-accessing instructions in the pipeline load/store pending? fetch ins Fetch Decode Execute Memory Write-Back ins misses Instruction Cache Data Cache blocked Memory Sebastian Hahn Strictly In-Order Core RTSS / 17
47 SIC: Strictly In-Order Pipelined Core Enforce Monotonic Behaviour Implementation: Prevent bus accesses of instruction fetches while Implementation: data-accessing instructions in the pipeline load/store pending? fetch ins Fetch Decode Execute Memory Write-Back ins misses Instruction Cache Data Cache blocked Memory strict bus access order Sebastian Hahn Strictly In-Order Core RTSS / 17
48 In Our Paper Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core Sebastian Hahn and Jan Reineke Saarland University Saarland Informatics Campus Saarbrücken, Germany {sebastian.hahn, reineke}@cs.uni-saarland.de Abstract We introduce the strictly in-order core (SIC), a share resources such as buses, caches, or memory channels timing-predictable pipelined processor core. SIC is provably among multiple cores. As a consequence, the execution time timing compositional and free of timing anomalies. This enables of a task depends on the interference on shared resources that precise and efficient worst-case execution time (WCET) and multi-core timing analysis. it experiences due to co-running tasks on other cores. SIC s key underlying property is the monotonicity of its As in single-core WCET analysis, assuming the worst-case transition relation w.r.t. a natural partial order on its microarchitectural states. This monotonicity is achieved by carefully elimi- option as it would result in highly pessimistic execution time latency upon every shared-resource access is not a viable nating some of the dependencies between consecutive instructions bounds. The greatest analysis precision would be achieved by from a standard in-order pipeline design. SIC preserves most of the benefits of pipelining: it is only fully-integrated timing analyses [6] [8]: such analyses simultaneously analyze the tasks running on different cores of a multi about 6-7% slower than a conventional pipelined processor. Its timing predictability enables orders-of-magnitude faster WCET core, precisely capturing all possible interleavings of resource and multi-core timing analysis than conventional designs. accesses from different cores. Unfortunately, this approach appears to be practically infeasible for realistic systems due I. INTRODUCTION to the astronomical number of system states to explore. The One of the main challenges for timing analysis is the most promising approach to multi-core timing analysis to date dependence of the execution time on the state of the underlying is compositional timing analysis [9] [18], which can be seen hardware platform. Even simple single-core processors feature as a natural extension of the classical two-step approach to stateful performance-enhancing mechanisms such as pipelining and caches. In the presence of such stateful mechanisms WCET analysis, computes the resource demand of each task timing analysis: low-level analysis, corresponding to classical an individual instruction s execution time may vary widely for each shared resource. Given such task characterizations, depending on the state of the hardware when the instruction is schedulability analysis then determines, whether each task executed. For example, a cache miss usually takes significantly can be guaranteed to meet its deadlines, accounting for the longer than a cache hit. interference it may experience on each of the shared resources. Simply assuming the worst-case latency of instructions Compositional timing analysis relies on the assumption that throughout a program s execution would result in a dramatic the response time of a task may be decomposed into contributions from different resources, which can each be efficiently overestimation of its worst-case execution time (WCET). To achieve accurate results, WCET analysis thus needs to precisely take into account in which hardware states a program s We have shown in previous work that, unfortunately, even analyzed separately. instructions are executed. State-of-the-art static WCET analysis tools [1] explore a program s possible executions on a given do not admit compositional timing analysis [19]. simple in-order pipelined cores feature timing anomalies and hardware platform by a combination of explicit and implicit Based on preliminary ideas presented in [20], in this paper, techniques. It is desirable to employ implicit techniques, we introduce the strictly in-order core (SIC), a pipelined such as abstractions [2], to efficiently explore large sets of processor core that is provably free of timing anomalies and states. While precise and efficient abstractions are known that admits compositional timing analysis. for caches [3], the efficient implicit analysis of pipelining is The starting point of this work has been the observation impeded by the presence of timing anomalies [4], [5]. Due that the presence of timing anomalies in conventional inorder pipelines can be traced back to the non-monotonicity of to timing anomalies it is not safe for WCET analysis to only explore local worst-case successors of pipeline states; nor their timing behavior. This non-monotonicity is due to dependencies between consecutive instructions, where progress of is it possible to devise efficient abstractions in which sets of concrete pipeline states are represented by individual abstract one instruction may be detrimental to the progress of another pipeline states. instruction. The key property of SIC is the monotonicity of Timing analysis for applications deployed on multi-core its timing behavior, which is enforced by carefully eliminating processors is even more challenging. Multi-core processors some of the dependencies between instructions in the pipeline. Formal definition of progress Definition of strictly in-order behaviour Proof of monotonicity Corollary: anomaly freedom Corollary: timing compositionality Sebastian Hahn Strictly In-Order Core RTSS / 17
49 Evaluation Questions 1.) Performance Overhead of Enforcing Access Order 2.) Gain in Analysis Efficiency Sebastian Hahn Strictly In-Order Core RTSS / 17
50 Performance SIC versus Conventional In-Order 1.5 performance degradation of SIC versus in-order 0.5 cache size sets 256 sets 1024 sets 64 sets 256 sets 1024 sets 64 sets 256 sets 1024 sets memory latency 4 cycles 12 cycles 100 cycles Sebastian Hahn Strictly In-Order Core RTSS / 17
51 Performance SIC versus Conventional In-Order FPGA implementation overhead 0.2% 1.5 FPGA simulation performance degradation of SIC versus in-order cache size 0 64 sets 256 sets 1024 sets 64 sets 256 sets 1024 sets 64 sets 256 sets 1024 sets memory latency 4 cycles 12 cycles 100 cycles Sebastian Hahn Strictly In-Order Core RTSS / 17
52 Performance SIC versus Conventional In-Order performance degradation of SIC versus in-order cache size sets sets sets sets sets FPGA simulation static analysis sets sets sets sets memory latency 4 cycles 12 cycles 100 cycles Sebastian Hahn Strictly In-Order Core RTSS / 17
53 Performance Single PTARM-Thread versus SIC A Precision-Timed (PRET) Microarchitecture Implementation [Liu et al., ICCD 12] performance degradation of PTARM versus SIC cache size sets sets 1024 sets sets 256 sets FPGA simulation static analysis 1024 sets 64 sets sets sets memory latency 4 cycles 12 cycles 100 cycles Sebastian Hahn Strictly In-Order Core RTSS / 17
54 Task-Level Analysis Cost PTARM slowdown in analysis runtime relative to SIC cache size 64 sets 256 sets 1024 sets 64 sets 256 sets 1024 sets 64 sets 256 sets 1024 sets memory latency 4 cycles 12 cycles 100 cycles Sebastian Hahn Strictly In-Order Core RTSS / 17
55 Task-Level Analysis Cost PTARM in-order (anomalies) slowdown in analysis runtime relative to SIC cache size 64 sets 256 sets 1024 sets 64 sets 256 sets 1024 sets 64 sets 256 sets 1024 sets memory latency 4 cycles 12 cycles 100 cycles Sebastian Hahn Strictly In-Order Core RTSS / 17
56 Task-Level Analysis Cost Compositional Base Bound [Hahn et al., RTNS 16] slowdown in analysis runtime relative to SIC cache size sets sets sets PTARM in-order (anomalies) in-order (using compositional base bound) sets 256 sets 1024 sets sets 256 sets 1024 sets memory latency 4 cycles 12 cycles 100 cycles Sebastian Hahn Strictly In-Order Core RTSS / 17
57 Conclusions Strictly in-order pipeline designed to behave monotonically provably timing-predictable: anomaly freedom + compositionality c miss cache miss cache hit less progress c hit c miss cache miss cache hit c hit less progress less progress p cycles more progress less progress c rectified yet performant practical: low implementation overhead Sebastian Hahn Strictly In-Order Core RTSS / 17
Design and Analysis of Time-Critical Systems Timing Predictability and Analyzability + Case Studies: PTARM and Kalray MPPA-256
Design and Analysis of Time-Critical Systems Timing Predictability and Analyzability + Case Studies: PTARM and Kalray MPPA-256 Jan Reineke @ saarland university computer science ACACES Summer School 2017
Enabling Compositionality for Multicore Timing Analysis
Enabling Compositionality for Multicore Timing Analysis Sebastian Hahn Saarland University Saarland Informatics Campus Saarbrücken, Germany sebastian.hahn@cs.unisaarland.de Michael Jacobs Saarland University
Design and Analysis of Real-Time Systems Microarchitectural Analysis
Design and Analysis of Real-Time Systems Microarchitectural Analysis Jan Reineke Advanced Lecture, Summer 2013 Structure of WCET Analyzers Reconstructs a control-flow graph from the binary. Determines
Timing analysis and timing predictability
Timing analysis and timing predictability Architectural Dependences Reinhard Wilhelm Saarland University, Saarbrücken, Germany ArtistDesign Summer School in China 2010 What does the execution time depends
Timing Analysis of Embedded Software for Families of Microarchitectures
Analysis of Embedded Software for Families of Microarchitectures Jan Reineke, UC Berkeley Edward A. Lee, UC Berkeley Representing Distributed Sense and Control Systems (DSCS) theme of MuSyC With thanks
Impact of Resource Sharing on Performance and Performance Prediction: A Survey
Impact of Resource Sharing on Performance and Performance Prediction: A Survey Andreas Abel, Florian Benz, Johannes Doerfert, Barbara Dörr, Sebastian Hahn, Florian Haupenthal, Michael Jacobs, Amir H. Moin,
Timing Anomalies and WCET Analysis. Ashrit Triambak
Timing Anomalies and WCET Analysis Ashrit Triambak October 20, 2014 Contents 1 Abstract 2 2 Introduction 2 3 Timing Anomalies 3 3.1 Retated work........................... 4 3.2 Limitations of Previous
Design and Analysis of Real-Time Systems Predictability and Predictable Microarchitectures
Design and Analysis of Real-Time Systems Predictability and Predictable Microarcectures Jan Reineke Advanced Lecture, Summer 2013 Notion of Predictability Oxford Dictionary: predictable = adjective, able
ait: WORST-CASE EXECUTION TIME PREDICTION BY STATIC PROGRAM ANALYSIS
ait: WORST-CASE EXECUTION TIME PREDICTION BY STATIC PROGRAM ANALYSIS Christian Ferdinand and Reinhold Heckmann AbsInt Angewandte Informatik GmbH, Stuhlsatzenhausweg 69, D-66123 Saarbrucken, Germany info@absint.com
Precise and Efficient FIFO-Replacement Analysis Based on Static Phase Detection
Precise and Efficient FIFO-Replacement Analysis Based on Static Phase Detection Daniel Grund 1 Jan Reineke 2 1 Saarland University, Saarbrücken, Germany 2 University of California, Berkeley, USA Euromicro
CS 426 Parallel Computing. Parallel Computing Platforms
CS 426 Parallel Computing Parallel Computing Platforms Ozcan Ozturk http://www.cs.bilkent.edu.tr/~ozturk/cs426/ Slides are adapted from ``Introduction to Parallel Computing'' Topic Overview Implicit Parallelism:
Design and Analysis of Time-Critical Systems Introduction
Design and Analysis of Time-Critical Systems Introduction Jan Reineke @ saarland university ACACES Summer School 2017 Fiuggi, Italy computer science Structure of this Course 2. How are they implemented?
CACHE-RELATED PREEMPTION DELAY COMPUTATION FOR SET-ASSOCIATIVE CACHES
CACHE-RELATED PREEMPTION DELAY COMPUTATION FOR SET-ASSOCIATIVE CACHES PITFALLS AND SOLUTIONS 1 Claire Burguière, Jan Reineke, Sebastian Altmeyer 2 Abstract In preemptive real-time systems, scheduling analyses
Evaluating compositional timing analyses
Saarland University Faculty of Natural Sciences and Technology I Department of Computer Science Master thesis Evaluating compositional timing analyses submitted by Claus Michael Faymonville submitted September
This is a repository copy of Response-time analysis for fixed-priority systems with a write-back cache.
This is a repository copy of Response-time analysis for fixed-priority systems with a write-back cache. White Rose Research Online URL for this paper: http://eprints.whiterose.ac.uk/129693/ Version: Published
Hardware-Software Codesign. 9. Worst Case Execution Time Analysis
Hardware-Software Codesign 9. Worst Case Execution Time Analysis Lothar Thiele 9-1 System Design Specification System Synthesis Estimation SW-Compilation Intellectual Prop. Code Instruction Set HW-Synthesis
Dissecting Execution Traces to Understand Long Timing Effects
Dissecting Execution Traces to Understand Long Timing Effects Christine Rochange and Pascal Sainrat February 2005 Rapport IRIT-2005-6-R Contents 1. Introduction... 5 2. Long timing effects... 5 3. Methodology...
4. Hardware Platform: Real-Time Requirements
4. Hardware Platform: Real-Time Requirements Contents: 4.1 Evolution of Microprocessor Architecture 4.2 Performance-Increasing Concepts 4.3 Influences on System Architecture 4.4 A Real-Time Hardware Architecture
MAKING DYNAMIC MEMORY ALLOCATION STATIC TO SUPPORT WCET ANALYSES 1 Jörg Herter 2 and Jan Reineke 2
MAKING DYNAMIC MEMORY ALLOCATION STATIC TO SUPPORT WCET ANALYSES 1 Jörg Herter 2 and Jan Reineke 2 Abstract Current worst-case execution time (WCET) analyses do not support programs using dynamic memory
Worst Case Analysis of DRAM Latency in Multi-Requestor Systems. Zheng Pei Wu Yogen Krish Rodolfo Pellizzoni
orst Case Analysis of DAM Latency in Multi-equestor Systems Zheng Pei u Yogen Krish odolfo Pellizzoni Multi-equestor Systems CPU CPU CPU Inter-connect DAM DMA I/O 1/26 Multi-equestor Systems CPU CPU CPU
Scheduling of Parallel Real-time DAG Tasks on Multiprocessor Systems
Scheduling of Parallel Real-time DAG Tasks on Multiprocessor Systems Laurent George ESIEE Paris Journée du groupe de travail OVSTR - 23 mai 2016 Université Paris-Est, LRT Team at LIGM 1/53 CONTEXT: REAL-TIME
Predicting the Worst-Case Execution Time of the Concurrent Execution. of Instructions and Cycle-Stealing DMA I/O Operations
ACM SIGPLAN Workshop on Languages, Compilers and Tools for Real-Time Systems, La Jolla, California, June 1995. Predicting the Worst-Case Execution Time of the Concurrent Execution of Instructions and Cycle-Stealing
CONTENTION IN MULTICORE HARDWARE SHARED RESOURCES: UNDERSTANDING OF THE STATE OF THE ART
CONTENTION IN MULTICORE HARDWARE SHARED RESOURCES: UNDERSTANDING OF THE STATE OF THE ART Gabriel Fernandez 1, Jaume Abella 2, Eduardo Quiñones 2, Christine Rochange 3, Tullio Vardanega 4 and Francisco
An extensible framework for multicore response time analysis
Real-Time Syst (2018) 54:607 661 https://doi.org/10.1007/s11241-017-9285-4 An extensible framework for multicore response time analysis Robert I. Davis 1,2 Sebastian Altmeyer 3 Leandro S. Indrusiak 1 Claire
A Template for Predictability Definitions with Supporting Evidence
A Template for Predictability Definitions with Supporting Evidence Daniel Grund 1, Jan Reineke 2, and Reinhard Wilhelm 1 1 Saarland University, Saarbrücken, Germany. grund@cs.uni-saarland.de 2 University
UNIT I (Two Marks Questions & Answers)
UNIT I (Two Marks Questions & Answers) Discuss the different ways how instruction set architecture can be classified? Stack Architecture,Accumulator Architecture, Register-Memory Architecture,Register-
Single-Path Programming on a Chip-Multiprocessor System
Single-Path Programming on a Chip-Multiprocessor System Martin Schoeberl, Peter Puschner, and Raimund Kirner Vienna University of Technology, Austria mschoebe@mail.tuwien.ac.at, {peter,raimund}@vmars.tuwien.ac.at
Supra-linear Packet Processing Performance with Intel Multi-core Processors
White Paper Dual-Core Intel Xeon Processor LV 2.0 GHz Communications and Networking Applications Supra-linear Packet Processing Performance with Intel Multi-core Processors 1 Executive Summary Advances
Impact of Platform Abstractions on the Development Workflow
Impact of Platform Abstractions on the Development Workflow Johannes Pletzer, Wolfgang Pree Technical Report September 7, 2009 C. Doppler Laboratory Embedded Software Systems University of Salzburg Austria
15-740/ Computer Architecture Lecture 20: Main Memory II. Prof. Onur Mutlu Carnegie Mellon University
15-740/18-740 Computer Architecture Lecture 20: Main Memory II Prof. Onur Mutlu Carnegie Mellon University Today SRAM vs. DRAM Interleaving/Banking DRAM Microarchitecture Memory controller Memory buses
Predictable Programming on a Precision Timed Architecture
Predictable Programming on a Precision Timed Architecture Ben Lickly, Isaac Liu, Hiren Patel, Edward Lee, University of California, Berkeley Sungjun Kim, Stephen Edwards, Columbia University, New York
COSC 6385 Computer Architecture - Memory Hierarchy Design (III)
COSC 6385 Computer Architecture - Memory Hierarchy Design (III) Fall 2006 Reducing cache miss penalty Five techniques Multilevel caches Critical word first and early restart Giving priority to read misses
Caches in Real-Time Systems. Instruction Cache vs. Data Cache
Caches in Real-Time Systems [Xavier Vera, Bjorn Lisper, Jingling Xue, Data Caches in Multitasking Hard Real- Time Systems, RTSS 2003.] Schedulability Analysis WCET Simple Platforms WCMP (memory performance)
History-based Schemes and Implicit Path Enumeration
History-based Schemes and Implicit Path Enumeration Claire Burguière and Christine Rochange Institut de Recherche en Informatique de Toulouse Université Paul Sabatier 6 Toulouse cedex 9, France {burguier,rochange}@irit.fr
Meltdown or "Holy Crap: How did we do this to ourselves" Meltdown exploits side effects of out-of-order execution to read arbitrary kernelmemory
Meltdown or "Holy Crap: How did we do this to ourselves" Abstract Meltdown exploits side effects of out-of-order execution to read arbitrary kernelmemory locations Breaks all security assumptions given
Precision Timed (PRET) Machines
Precision Timed (PRET) Machines Edward A. Lee Robert S. Pepper Distinguished Professor UC Berkeley BWRC Open House, Berkeley, CA February, 2012 Key Collaborators on work shown here: Steven Edwards Jeff
Evaluating Static Worst-Case Execution-Time Analysis for a Commercial Real-Time Operating System
Evaluating Static Worst-Case Execution-Time Analysis for a Commercial Real-Time Operating System Daniel Sandell Master s thesis D-level, 20 credits Dept. of Computer Science Mälardalen University Supervisor:
Predictability Considerations in the Design of Multi-Core Embedded Systems
Predictability Considerations in the Design of Multi-Core Embedded Systems Christoph Cullmann 1, Christian Ferdinand 1, Gernot Gebhard 1, Daniel Grund 2, Claire Maiza (Burguière) 2, Jan Reineke 3, Benoît
Chapter 2: Memory Hierarchy Design Part 2
Chapter 2: Memory Hierarchy Design Part 2 Introduction (Section 2.1, Appendix B) Caches Review of basics (Section 2.1, Appendix B) Advanced methods (Section 2.3) Main Memory Virtual Memory Fundamental
Blocking Analysis of FIFO, Unordered, and Priority-Ordered Spin Locks
On Spin Locks in AUTOSAR: Blocking Analysis of FIFO, Unordered, and Priority-Ordered Spin Locks Alexander Wieder and Björn Brandenburg MPI-SWS RTSS 2013 12/04/2013 Vancouver, Canada Motivation: AUTOSAR:
Worst Case Analysis of DRAM Latency in Hard Real Time Systems
Worst Case Analysis of DRAM Latency in Hard Real Time Systems by Zheng Pei Wu A thesis presented to the University of Waterloo in fulfillment of the thesis requirement for the degree of Master of Applied
Building Timing Predictable Embedded Systems
Building Timing Predictable Embedded Systems PHILIP AXER and ROLF ERNST, TU Braunschweig HEIKO FALK, Ulm University ALAIN GIRAULT, INRIA and University of Grenoble DANIEL GRUND, Saarland University NAN
WCET-Aware C Compiler: WCC
12 WCET-Aware C Compiler: WCC Jian-Jia Chen (slides are based on Prof. Heiko Falk) TU Dortmund, Informatik 12 2015 年 05 月 05 日 These slides use Microsoft clip arts. Microsoft copyright restrictions apply.
Architecture Tuning Study: the SimpleScalar Experience
Architecture Tuning Study: the SimpleScalar Experience Jianfeng Yang Yiqun Cao December 5, 2005 Abstract SimpleScalar is software toolset designed for modeling and simulation of processor performance.
This is the published version of a paper presented at MCC14, Seventh Swedish Workshop on Multicore Computing, Lund, Nov , 2014.
http://www.diva-portal.org This is the published version of a paper presented at MCC14, Seventh Swedish Workshop on Multicore Computing, Lund, Nov. 27-28, 2014. Citation for the original published paper:
Chapter 5A. Large and Fast: Exploiting Memory Hierarchy
Chapter 5A Large and Fast: Exploiting Memory Hierarchy Memory Technology Static RAM (SRAM) Fast, expensive Dynamic RAM (DRAM) In between Magnetic disk Slow, inexpensive Ideal memory Access time of SRAM
Timing Anomalies Reloaded
Gernot Gebhard AbsInt Angewandte Informatik GmbH 1 of 20 WCET 2010 Brussels Belgium Timing Anomalies Reloaded Gernot Gebhard AbsInt Angewandte Informatik GmbH Brussels, 6 th July, 2010 Gernot Gebhard AbsInt
250P: Computer Systems Architecture. Lecture 9: Out-of-order execution (continued) Anton Burtsev February, 2019
250P: Computer Systems Architecture Lecture 9: Out-of-order execution (continued) Anton Burtsev February, 2019 The Alpha 21264 Out-of-Order Implementation Reorder Buffer (ROB) Branch prediction and instr
Lecture: SMT, Cache Hierarchies. Topics: memory dependence wrap-up, SMT processors, cache access basics and innovations (Sections B.1-B.3, 2.
Lecture: SMT, Cache Hierarchies Topics: memory dependence wrap-up, SMT processors, cache access basics and innovations (Sections B.1-B.3, 2.1) 1 Problem 0 Consider the following LSQ and when operands are
Improving Timing Analysis for Matlab Simulink/Stateflow
Improving Timing Analysis for Matlab Simulink/Stateflow Lili Tan, Björn Wachter, Philipp Lucas, Reinhard Wilhelm Universität des Saarlandes, Saarbrücken, Germany {lili,bwachter,phlucas,wilhelm}@cs.uni-sb.de
arxiv: v2 [cs.ds] 22 Jun 2016
![arxiv: v2 [cs.ds] 22 Jun 2016](/thumbs/88/115676278.jpg "arxiv: v2 [cs.ds] 22 Jun 2016")
Federated Scheduling Admits No Constant Speedup Factors for Constrained-Deadline DAG Task Systems Jian-Jia Chen Department of Informatics, TU Dortmund University, Germany arxiv:1510.07254v2 [cs.ds] 22
Lecture: SMT, Cache Hierarchies. Topics: memory dependence wrap-up, SMT processors, cache access basics and innovations (Sections B.1-B.3, 2.
Lecture: SMT, Cache Hierarchies Topics: memory dependence wrap-up, SMT processors, cache access basics and innovations (Sections B.1-B.3, 2.1) 1 Problem 1 Consider the following LSQ and when operands are
Time Triggered and Event Triggered; Off-line Scheduling
Time Triggered and Event Triggered; Off-line Scheduling Real-Time Architectures -TUe Gerhard Fohler 2004 Mälardalen University, Sweden gerhard.fohler@mdh.se Real-time: TT and ET Gerhard Fohler 2004 1 Activation
Main Points of the Computer Organization and System Software Module
Main Points of the Computer Organization and System Software Module You can find below the topics we have covered during the COSS module. Reading the relevant parts of the textbooks is essential for a
Lecture: SMT, Cache Hierarchies. Topics: SMT processors, cache access basics and innovations (Sections B.1-B.3, 2.1)
Lecture: SMT, Cache Hierarchies Topics: SMT processors, cache access basics and innovations (Sections B.1-B.3, 2.1) 1 Thread-Level Parallelism Motivation: a single thread leaves a processor under-utilized
FIFO Cache Analysis for WCET Estimation: A Quantitative Approach
FIFO Cache Analysis for WCET Estimation: A Quantitative Approach Abstract Although most previous work in cache analysis for WCET estimation assumes the LRU replacement policy, in practise more processors
Timing Analysis - timing guarantees for hard real-time systems- Reinhard Wilhelm Saarland University Saarbrücken
Timing Analysis - timing guarantees for hard real-time systems- Reinhard Wilhelm Saarland University Saarbrücken Structure of the Lecture 1. Introduction 2. Static timing analysis 1. the problem 2. our
Selfish-LRU: Preemption-Aware Caching for Predictability and Performance
Selfish-LRU: Preemption-Aware Caching for Predictability and Performance Jan Reineke, Sebastian Altmeyer, Daniel Grund, Sebastian Hahn, and Claire Maiza Saarland University, Saarbrücken, Germany reineke@cs.uni-saarland.de,
Lecture 11: SMT and Caching Basics. Today: SMT, cache access basics (Sections 3.5, 5.1)
Lecture 11: SMT and Caching Basics Today: SMT, cache access basics (Sections 3.5, 5.1) 1 Thread-Level Parallelism Motivation: a single thread leaves a processor under-utilized for most of the time by doubling
ECE 30 Introduction to Computer Engineering
ECE 0 Introduction to Computer Engineering Study Problems, Set #9 Spring 01 1. Given the following series of address references given as word addresses:,,, 1, 1, 1,, 8, 19,,,,, 7,, and. Assuming a direct-mapped
Cache Optimization. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University
Cache Optimization Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Cache Misses On cache hit CPU proceeds normally On cache miss Stall the CPU pipeline
COSC 6385 Computer Architecture. - Memory Hierarchies (II)
COSC 6385 Computer Architecture - Memory Hierarchies (II) Fall 2008 Cache Performance Avg. memory access time = Hit time + Miss rate x Miss penalty with Hit time: time to access a data item which is available
Cycle Time for Non-pipelined & Pipelined processors
Cycle Time for Non-pipelined & Pipelined processors Fetch Decode Execute Memory Writeback 250ps 350ps 150ps 300ps 200ps For a non-pipelined processor, the clock cycle is the sum of the latencies of all
Write only as much as necessary. Be brief!
1 CIS371 Computer Organization and Design Midterm Exam Prof. Martin Thursday, March 15th, 2012 This exam is an individual-work exam. Write your answers on these pages. Additional pages may be attached
15-740/ Computer Architecture Lecture 22: Superscalar Processing (II) Prof. Onur Mutlu Carnegie Mellon University
15-740/18-740 Computer Architecture Lecture 22: Superscalar Processing (II) Prof. Onur Mutlu Carnegie Mellon University Announcements Project Milestone 2 Due Today Homework 4 Out today Due November 15
Microkernel/OS and Real-Time Scheduling
Chapter 12 Microkernel/OS and Real-Time Scheduling Hongwei Zhang http://www.cs.wayne.edu/~hzhang/ Ack.: this lecture is prepared in part based on slides of Lee, Sangiovanni-Vincentelli, Seshia. Outline
Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software. Yau-Tsun Steven Li Sharad Malik Andrew Wolfe
Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software Yau-Tsun Steven Li Sharad Malik Andrew Wolfe 1 Introduction Paper examines the problem of determining the bound on the worst
A Lost Cycles Analysis for Performance Prediction using High-Level Synthesis
A Lost Cycles Analysis for Performance Prediction using High-Level Synthesis Bruno da Silva, Jan Lemeire, An Braeken, and Abdellah Touhafi Vrije Universiteit Brussel (VUB), INDI and ETRO department, Brussels,
ESE532: System-on-a-Chip Architecture. Today. Message. Real Time. Real-Time Tasks. Real-Time Guarantees. Real Time Demands Challenges
ESE532: System-on-a-Chip Architecture Day 9: October 1, 2018 Real Time Real Time Demands Challenges Today Algorithms Architecture Disciplines to achieve Penn ESE532 Fall 2018 -- DeHon 1 Penn ESE532 Fall
SISTEMI EMBEDDED. Computer Organization Pipelining. Federico Baronti Last version:
SISTEMI EMBEDDED Computer Organization Pipelining Federico Baronti Last version: 20160518 Basic Concept of Pipelining Circuit technology and hardware arrangement influence the speed of execution for programs
HW/SW Codesign. WCET Analysis
HW/SW Codesign WCET Analysis 29 November 2017 Andres Gomez gomeza@tik.ee.ethz.ch 1 Outline Today s exercise is one long question with several parts: Basic blocks of a program Static value analysis WCET
Timing Analysis Enhancement for Synchronous Program
Timing Analysis Enhancement for Synchronous Program Extended Abstract Pascal Raymond, Claire Maiza, Catherine Parent-Vigouroux, Fabienne Carrier, and Mihail Asavoae Grenoble-Alpes University Verimag, Centre
Modeling and Simulating Discrete Event Systems in Metropolis
Modeling and Simulating Discrete Event Systems in Metropolis Guang Yang EECS 290N Report December 15, 2004 University of California at Berkeley Berkeley, CA, 94720, USA guyang@eecs.berkeley.edu Abstract
Classification of Code Annotations and Discussion of Compiler-Support for Worst-Case Execution Time Analysis
Proceedings of the 5th Intl Workshop on Worst-Case Execution Time (WCET) Analysis Page 41 of 49 Classification of Code Annotations and Discussion of Compiler-Support for Worst-Case Execution Time Analysis
Sireesha R Basavaraju Embedded Systems Group, Technical University of Kaiserslautern
Sireesha R Basavaraju Embedded Systems Group, Technical University of Kaiserslautern Introduction WCET of program ILP Formulation Requirement SPM allocation for code SPM allocation for data Conclusion
Preemption-Aware Caching for Predictability and Performance
Selfish-LRU: Preemption-ware aching for Predictability and Performance Jan Reineke Sebastian ltmeyer aniel Grund Sebastian Hahn laire Maiza S a a r l a n d U n i v e r s i t y, G e r m a n y University
Overview: Memory Consistency
Overview: Memory Consistency the ordering of memory operations basic definitions; sequential consistency comparison with cache coherency relaxing memory consistency write buffers the total store ordering
15-740/ Computer Architecture Lecture 21: Superscalar Processing. Prof. Onur Mutlu Carnegie Mellon University
15-740/18-740 Computer Architecture Lecture 21: Superscalar Processing Prof. Onur Mutlu Carnegie Mellon University Announcements Project Milestone 2 Due November 10 Homework 4 Out today Due November 15
Abstract PRET Machines
Abstract PRET Machines Invited TCRTS award paper Edward A. Lee (award recipient) UC Berkeley Berkeley, CA 94720 Email: eal@eecs.berkeley.edu Jan Reineke Saarland University Saarland Informatics Campus
CS 654 Computer Architecture Summary. Peter Kemper
CS 654 Computer Architecture Summary Peter Kemper Chapters in Hennessy & Patterson Ch 1: Fundamentals Ch 2: Instruction Level Parallelism Ch 3: Limits on ILP Ch 4: Multiprocessors & TLP Ap A: Pipelining
Caches in Real-Time Systems. Instruction Cache vs. Data Cache
Caches in Real-Time Systems [Xavier Vera, Bjorn Lisper, Jingling Xue, Data Caches in Multitasking Hard Real- Time Systems, RTSS 2003.] Schedulability Analysis WCET Simple Platforms WCMP (memory performance)
Comparative evaluation of limited preemptive methods
Comparative evaluation of limited preemptive methods Gang Yao, Giorgio Buttazzo and Marko Bertogna Scuola Superiore Sant Anna, Pisa, Italy, {g.yao, g.buttazzo, m.bertogna}@sssup.it Abstract Schedulability
Computer Architecture
Computer Architecture Slide Sets WS 2013/2014 Prof. Dr. Uwe Brinkschulte M.Sc. Benjamin Betting Part 10 Thread and Task Level Parallelism Computer Architecture Part 10 page 1 of 36 Prof. Dr. Uwe Brinkschulte,
Automatic Qualification of Abstract Interpretation-based Static Analysis Tools. Christian Ferdinand, Daniel Kästner AbsInt GmbH 2013
Automatic Qualification of Abstract Interpretation-based Static Analysis Tools Christian Ferdinand, Daniel Kästner AbsInt GmbH 2013 2 Functional Safety Demonstration of functional correctness Well-defined
Improving Real-Time Performance on Multicore Platforms Using MemGuard
Improving Real-Time Performance on Multicore Platforms Using MemGuard Heechul Yun University of Kansas 2335 Irving hill Rd, Lawrence, KS heechul@ittc.ku.edu Abstract In this paper, we present a case-study
Event-Driven Scheduling. (closely following Jane Liu s Book)
Event-Driven Scheduling (closely following Jane Liu s Book) Real-Time Systems, 2006 Event-Driven Systems, 1 Principles Assign priorities to Jobs At events, jobs are scheduled according to their priorities
Last Time. Response time analysis Blocking terms Priority inversion. Other extensions. And solutions
Last Time Response time analysis Blocking terms Priority inversion And solutions Release jitter Other extensions Today Timing analysis Answers a question we commonly ask: At most long can this code take
Principles in Computer Architecture I CSE 240A (Section ) CSE 240A Homework Three. November 18, 2008
Principles in Computer Architecture I CSE 240A (Section 631684) CSE 240A Homework Three November 18, 2008 Only Problem Set Two will be graded. Turn in only Problem Set Two before December 4, 2008, 11:00am.
A Time-Predictable Instruction-Cache Architecture that Uses Prefetching and Cache Locking
A Time-Predictable Instruction-Cache Architecture that Uses Prefetching and Cache Locking Bekim Cilku, Daniel Prokesch, Peter Puschner Institute of Computer Engineering Vienna University of Technology
Pipelining, Branch Prediction, Trends
Pipelining, Branch Prediction, Trends 10.1-10.4 Topics 10.1 Quantitative Analyses of Program Execution 10.2 From CISC to RISC 10.3 Pipelining the Datapath Branch Prediction, Delay Slots 10.4 Overlapping
Transforming Execution-Time Boundable Code into Temporally Predictable Code
Transforming Execution-Time Boundable Code into Temporally Predictable Code Peter Puschner Institut for Technische Informatik. Technische Universitdt Wien, Austria Abstract: Traditional Worst-Case Execution-Time
Static Memory and Timing Analysis of Embedded Systems Code
Static Memory and Timing Analysis of Embedded Systems Code Christian Ferdinand Reinhold Heckmann Bärbel Franzen AbsInt Angewandte Informatik GmbH Science Park 1, D-66123 Saarbrücken, Germany Phone: +49-681-38360-0
Rely-Guarantee References for Refinement Types over Aliased Mutable Data
Rely-Guarantee References for Refinement Types over Aliased Mutable Data Colin S. Gordon, Michael D. Ernst, and Dan Grossman University of Washington PLDI 2013 Static Verification Meets Aliasing 23 x:ref
Worst-Case Execution Time Analysis for Dynamic Branch Predictors
Worst-Case Execution Time Analysis for Dynamic Branch Predictors Iain Bate and Ralf Reutemann Department of Computer Science, University of York York, United Kingdom e-mail: {ijb,ralf}@cs.york.ac.uk Abstract
Large-Scale Network Simulation Scalability and an FPGA-based Network Simulator
Large-Scale Network Simulation Scalability and an FPGA-based Network Simulator Stanley Bak Abstract Network algorithms are deployed on large networks, and proper algorithm evaluation is necessary to avoid
Lecture 12: An Overview of Scheduling Theory
Lecture 12: An Overview of Scheduling Theory [RTCS Ch 8] Introduction Execution Time Estimation Basic Scheduling Approaches Static Cyclic Scheduling Fixed Priority Scheduling Rate Monotonic Analysis Earliest
Precise Continuous Non-Intrusive Measurement-Based Execution Time Estimation. Boris Dreyer, Christian Hochberger, Simon Wegener, Alexander Weiss
Precise Continuous Non-Intrusive Measurement-Based Execution Time Estimation Boris Dreyer, Christian Hochberger, Simon Wegener, Alexander Weiss This work was funded within the project CONIRAS by the German
Introduction to Real-time Systems. Advanced Operating Systems (M) Lecture 2
Introduction to Real-time Systems Advanced Operating Systems (M) Lecture 2 Introduction to Real-time Systems Real-time systems deliver services while meeting some timing constraints Not necessarily fast,
Static WCET Analysis: Methods and Tools
Static WCET Analysis: Methods and Tools Timo Lilja April 28, 2011 Timo Lilja () Static WCET Analysis: Methods and Tools April 28, 2011 1 / 23 1 Methods 2 Tools 3 Summary 4 References Timo Lilja () Static
MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding
www.bsc.es MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding Enrique Díaz¹,², Mikel Fernández¹, Leonidas Kosmidis¹, Enrico Mezzetti¹, Carles Hernandez¹, Jaume Abella¹,